Abstract: A semiconductor device includes a data compression circuit that performs sequential processes based on timings of an external clock signal. The sequential processes include compressing data input in parallel, latching the compressed data, and outputting the latched data.

Abstract: A memory device is adapted to be connected in a daisy chain with a memory controller and one or more other memory devices. The memory device includes at least one data input port and at least one data output port for communicating data along the daisy-chain between the memory devices and the memory controller. The memory device is adapted to selectively enable/disable at least one of the data input or data output ports in response to whether a command received from the memory controller is intended for the memory device, or for one of the other memory devices.

Abstract: A semiconductor memory device includes a memory cell array, a data input/output terminal, a data input/output circuit, and a test circuit. The data input/output circuit is provided between the memory cell array and the data input/output terminal. The data input/output circuit includes a main amplifier that amplifies data written into selected memory cells in the memory cell array during data write operation and that amplifies data read from the selected memory cells during read operation, and a memory element provided accompanying the main amplifier in order to repair a defective memory cell in the memory cell array. The test circuit starts up in test mode, writes data into the memory element through the data input/output terminal, and read data from the memory element into the data input/output terminal regardless of access address information to the memory cell.

Abstract: A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.

Abstract: A circuit which can reduce time taken by a clock alignment training operation in a semiconductor memory device is provided. The semiconductor memory device, which includes: a clock inputting unit configured to receive a system clock and a data clock; a clock dividing unit configured to divide a frequency of the data clock to generate a data division clock, wherein the clock dividing unit determines a phase of the data division clock in response to an inversion division control signal; a phase dividing unit configured to generate a plurality of multiple phase data division clocks having respective predetermined phase differences in response to the data division clock; a data serializing unit configured to serialize predetermined parallel pattern data in correspondence with the multiple phase data division clocks; and a signal transmitting unit configured to transmit an output signal of the data serializing unit to the outside.

Abstract: A semiconductor memory device capable of reducing a whole area thereof includes a plurality of data input circuits configured to reflect inversion information on data inputted thereto, a plurality of global lines for transferring data outputted from the plurality of data input circuits, and a plurality of memory banks for storing data transferred from the plurality of global lines.

Abstract: An address counter includes FIFO units and first and second command counters that control the groups. The first command counter has a first mode in which any one of input gates is conducted in response to a first internal command and a second mode in which a plurality of input gates are conducted in response to an internal command. The second command counter has a first mode in which any one of output gates is conducted in response to one of second and third internal commands and second mode in which corresponding output gates are each conducted in response to one of the second and third internal commands. Thereby, when tCCD is small, the first mode can be selected, and when the tCCD is large, the second mode can be selected.

Abstract: A delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a master-slave DLL to the system provides an accurate, PVT insensitive translation of the echo clocks into the read data eye. Solidifying the timing critical drive and receive logic which directly interfaces to the I/O buffers reduces the pin-to-pin skews. Utilizing clock phase outputs of the DLL in the solidified drive and receive logic blocks reduces further the skew between the clock and related data signals, and also removes the reliance on a differential clock. The system allows a much more relaxed constraint on clock duty cycle. Design of circuitry within the solidified drive and receive logic blocks permits simple logic modeling for fit within an ASIC flow. Physical design of the solidified drive and receive logic blocks permits simple fit within ASIC place and route flows for increased ease of implementation and ease of reuse.

Abstract: A memory system with a flexible serial interface and a memory accessing method thereof are provided. The memory system includes at least one of memories and a memory controller. The memory controller flexibly sets up serial link connection with each of the memories through serial ports regardless of a physical location and an order of the serial ports. The memory controller also transmits and receives memory data in a serial mode through the serial link connection.

Abstract: Control information needed for executing data transmission/reception through a data terminal is received via its own control terminal in a first operation mode, and the control information is received by using the own control terminal and also a control terminal of at least one of the other ports in a second operation mode.

Abstract: A semiconductor memory device may include,.but is not limited to, a storing unit and a selecting unit. The storing unit stores serial input data at at least one of a first type edge and a second type edge of a clock signal. The selecting unit receives the input data from the storing unit. The selecting unit selects the input data. The selecting unit outputs the selected input data in parallel.

Abstract: A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the data strobe signal to capture respective bits of data corresponding to the data signal. A decoder receives a memory command signal and generates a data start signal after a delay period from receiving the memory command signal if the command signal corresponds to a read or a write command. The receipt of read or write command signals is used by a control circuit to identify the start of valid read or write data signals. The control circuit then outputs the captured data signals responsive to the data start signal, thereby ignoring the transitions in the preamble of the data strobe signal.

Abstract: A multi-port memory device includes a plurality of ports located at a center region of the multi-port memory device, each for performing a data communication with a corresponding external device; a plurality of banks arranged at upper and lower regions of the multi-port memory device in a row direction on the basis of the plurality of ports; and first and second global I/O data buses arranged in the row direction between the banks and the ports, each for independently performing a data transmission between the banks and the ports.

Abstract: A data conversion circuit for a semiconductor memory apparatus includes a data conversion unit that has a plurality of latches for storing input data and outputting stored data as output data in response to a clock, and an operation mode selection unit that selects either a first operation mode to convert serial data to parallel data during a write operation or a second operation mode to convert parallel data to serial data during a read operation, to thereby drive the data conversion unit.

Abstract: Semiconductor memory device for high-speed data input/output includes a first serializer configured to partially serialize input 8-bit parallel data to output first to fourth serial data, a second serializer configured to partially serialize the first to fourth serial data to output fifth and sixth serial data and a third serializer configured to serialize the fifth and sixth serial data to output seventh serial data.

Abstract: A memory interface to bridge a parallel memory bus and a serial memory bus. A printed circuit board includes at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Abstract: A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.

Abstract: A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchronously with an internal clock, and continuously outputs two data simultaneously read from different mini arrays, synchronously with the internal clock. In testing the semiconductor memory device according to the present invention, one data is written during a period when an external clock having a cycle of an integer times cycle of the internal clock is fixed to a high level or a low level. With this arrangement, continuous data can be assigned to mutually different mini arrays.

Abstract: A data input circuit for a semiconductor memory apparatus includes a data latch block that, according to a data strobe signal, latches data and outputs the latched data; a data output controlling unit that determines a phase difference between the data strobe signal and a clock signal, and activates a data output control signal; and a data delay block that, when the data output control signal is activated, delays the data output from the data latch block for a predetermined time, and outputs the delayed data.

Abstract: An input circuit can minimize a circuit area required for data prefetch operation for an increased bit number of prefetch data. A control signal generating unit generates a plurality of control signals in response to a clock signal and a data strobe signal, wherein external data are input in synchronism with the data strobe signal. A synchronizing unit for aligns the input data into N-bit data in parallel by performing a data alignment operation at least three times, N being a positive integer larger than one.

Abstract: A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.

Abstract: A data input and data output control device and method in which a plurality of write or read data composed of m (2n+k) bits (where m, n, and k are all integers) may be accessed within one clock of external input clock.

Abstract: A memory device is configured for communicating with one of two different serial protocols, respectively an LPC or an SPI protocol, as well as with a parallel communication protocol through a multi-protocol interface while requiring only a single additional pin as compared to a standard memory device accessible with a parallel communication protocol. This result is achieved by exploiting the same pin for providing a timing signal for serial mode communications or an address multiplexing signal for parallel mode communications. The additional pin is used for conveying a start signal of an A/AMUX parallel communication protocol. The interface includes logic circuits that generate an enable signal for the standard memory core of the memory device.

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

Abstract: An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Abstract: A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response to the input control signal, arranges the parallel data in response to the selection signal, and sequentially outputs the arranged parallel data as serial data in synchronization with the output timing signal.

Abstract: A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing the address after the trigger signal. A hexadecimal counter counts a clock that is faster than the divided clock as the counted number circulates every one period of the divided clock . A trigger information latch latches the counted number of the counter when the trigger signal arrives and provides it to a MUX. The MUX selects data in a pair of the parallel data provided at first and second inputs I1 and I2 to produce rearranged parallel data bits according to the latched counted number. A parallel to serial converter receives the rearranged parallel data to convert it to serial data according to the clock.

Abstract: A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in synchronization with an internal clock; and an output buffer circuit which includes L FIFO buffers each for latching each bit of the L bits input from the internal bus and extracts stored data from each of the L FIFO buffers in accordance with an input sequence in synchronization with an external clock so as to transfer the data serially to outside, wherein each of the L FIFO buffers includes an M-bit latch circuit and an N-bit latch circuit, and paths of the M-bit and N-bit latch circuits can be selectively switched.

Abstract: A pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same. The pipe latch circuit includes a selection signal generator and a pipe latch unit. The selection signal generator generates input selection signals in response to an input control signal and a first selection control signal. The pipe latch unit inverts pre-fetch data received in parallel through a plurality of GIO (Global Input and Output) lines into serial pipe output data in response to input selection signals, a second selection control signal and output control signals and then outputs them at an output node. The pipe latch unit includes an input selection unit for selectively changing a parallel order of pre-fetch data respectively received through a plurality of GIO lines in response to an input selection signals and then respectively outputting input selection data at a plurality of internal data lines in accordance with the change result.

Abstract: Method and memory circuits capable of allowing M memory addresses of an N-port memory to be accessed concurrently, wherein N and M both are a natural number, and M is larger than N. Accordingly, a higher-order multi-port memory can be replaced by a lower-order multi-port or single-port memory. Consequently, smaller chip area or higher data access rate can be achieved.

Abstract: A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output terminals to allow a plurality of bits to be transmitted at the same time improving the data transmission rate at the slower serial clock speed.

Abstract: Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

Abstract: A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract: A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the memory cell array; a WR sense amplifier block (second memory unit) that stores first divided data to be written into the first bit and second divided data to be written into the second bit, the first divided data being formed by dividing the data into predetermined units, the second divided data being formed by dividing the data into predetermined units; and a control circuit that writes the second divided data into the first bit of the memory cells of the memory cell array (step S28) after writing the first divided data into the second bit of the memory cells of the memory cell array (step S22).

Abstract: A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Abstract: A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

Abstract: A data conversion circuit for a semiconductor memory apparatus includes a data conversion unit that has a plurality of latches for storing input data and outputting stored data as output data in response to a clock, and an operation mode selection unit that selects either a first operation mode to convert serial data to parallel data during a write operation or a second operation mode to convert parallel data to serial data during a read operation, to thereby drive the data conversion unit.

Abstract: A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor memory.

Abstract: Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial data output, with a processor, which has a parallel data input, is provided. The coupling device may include a serial data interface configured to receive data, a parallel data interface configured to transmit data, and a cache memory coupled to the serial data interface and to the parallel data interface, wherein the cache memory is configured to receive and store data, which have been received in a serial data format via the serial data interface, and to transmit data stored in the cache memory to the parallel data interface.

Abstract: A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.

Abstract: A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to an internal portion and serial converting parallel data applied from the internal portion and outputting the serial converted data to the IO circuit.

Abstract: A memory device is disclosed that has a longer read time than write time and implements a parallel-read operation. The parallel-read operation saves reading time and thus accelerates a write operation that comprises a step of comparing incoming data with memory data that were stored in the memory before. The arrangement is especially applicable to an MRAM memory with 0T1MTJ memory cells. The parallel-read operation involves reading in parallel a large amount of data or all data to be compared from the memory into a first temporary memory. The write data is stored in a second temporary memory. The memory data contained in the first temporary memory is compared with the corresponding write data contained in the second temporary memory and allocated to the same address information. Only that write data is written to the memory, which is different from the corresponding memory data.

Abstract: Techniques and circuitry for transferring data from memory arrays of a memory device to output pins via a FIFO structure are provided. Input and output stages of the FIFO structure may be operated independently, allowing data to be loaded into the FIFO structure at a first frequency and unloaded from the FIFO structure at a second frequency.

Abstract: A memory device compensates for delay time variations among multi-bit data. The device includes a first stage and a second stage of data storage units. The first stage of data storage units store first to nth data bits in response to a latch clock signal. The second stage of data storage units store the first to nth data contents output from the first stage of data storage units in response to a reference clock signal. The latch clock signal is obtained by delaying the reference clock signal. The latch clock signal includes first to nth sub latch signals. The sub latch signals are generated at different times according to propagation delay time periods of the corresponding first to nth data contents.

Abstract: A semiconductor memory includes a converter configured to convert each read-data of plural bits read from a memory core into serial data, respectively, in synchronization with a read clock to generate converted read-data. An output register holds the converted read-data in synchronization with the read clock. A selector selects one bit from each plural bits of the converted read-data, in accordance with a control data, and to supply the selected bit to the output register.

Abstract: In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data input or output to/from the selected memory blocks are loaded, memory cell data output from the selected memory blocks are sequentially output to the selected data I/O pads, and data input to the selected data I/O pads are sequentially input to the selected memory blocks, so that read and write operations are independently accomplished in each of data I/O pads. The data I/O width can be adjusted according to the word length which is selectively set up, and power consumption can be reduced due to partial activation of the memory block.

Abstract: A high-speed interface circuit is implemented in a semiconductor memory chip including a memory core, a first interface circuit section, and a second interface circuit section. The first interface circuit section is connectable to a write data-/command and address signal bus, includes a write data-/command and address re-driver/transmitter path (which may be transparent) and does not include any clock signal synchronizing circuitry, and a main write signal path including a serial-to-parallel converting and synchronizing device to synchronize with a reference clock signal received write data-/command and address signals and delivering the parallel converted write signals to the memory core.

Abstract: A semiconductor storage device has a data transfer circuit capable of reducing the latency, including a control circuit for frequency-dividing external clock signal to generate readout clocks, first to fourth amplifier circuits for amplifying read data corresponding to first and fourth addresses, based on readout clock signals, a first multiplexer receiving and selectively outputting temporally preceding and temporally succeeding first and second output data from two amplifier circuits associated with two even addresses, a second multiplexer receiving and selectively outputting temporally preceding and temporally succeeding third and fourth output data from two amplifier circuits associated with two odd addresses, first and second latch circuits for latching and outputting second and fourth output data, a third multiplexer receiving first and third data and outputting the latched data in the read address sequence, a fourth multiplexer receiving second and fourth data and outputting the latched data in the rea

Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.