Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: An apparatus for interleave includes a serial-parallel circuit which transforms a data form of an input data from serial into parallel and which outputs a plurality of parallel data, a first switch circuit which arranges order of the parallel data based on a first control signal and which outputs a plurality of first arranged data, a memory circuit which stores the first arranged data based on the first control signal and which outputs the stored first arranged data based on a second control signal, a second switch circuit which arranges order of the stored first arranged data based on the second control signal and which outputs a plurality of second arranged data, and a parallel-serial circuit which transforms a data form of the second arranged data from parallel into serial and which outputs a serial output data.

Abstract: A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to write N data bits in parallel and a write data path that is configured to serially receive 2N data bits from an external terminal. The write data path includes 2N write data buffers that are configured to store the 2N data bits, 2N switches, and N data lines that are configured to connect at least N of the 2N switches to the memory cell array to write therein N data bits in parallel. A reduced number of local data lines and/or global data lines may be provided.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract: A plurality of logic circuits access a DRAM block by way of an access circuit. The operation clock for the DRAM block is set at a higher frequency than the system clock for the logic circuits. Outputs of a first bit width from the logic circuits are subjected to serial/parallel conversion into data of a second bit width and the data is written into the DRAM block.

Abstract: A nonvolatile memory with a memory array arranged in rows and columns of memory cells in NOR configuration, the memory cells arranged on a same column being connected to one of a plurality of bit lines and a column decoder. The column decoder comprises a plurality of selection stages, each of which is connected to respective bit lines and receives first bit line addressing signals. The selection stages comprise word programming selectors controlled by the first bit line addressing signals and supplying a programming voltage to only one of the bit lines of each selection stage. Each selection stage moreover comprises a string programming selection circuit controlled by second bit line addressing signals thereby simultaneously supplying the programming voltage to a plurality of the bit lines of each selection stage.

Abstract: The present invention provides a speculatively loaded memory for use in a data processing system. The present invention may include a memory block including rows each identified by an address. A first register may store a first address of the memory block and a second register may store a second address of the memory block. A control circuit may be coupled to the first and second registers, and may receive control signals. The control circuit causes contents of the first register to be stored into the second register in response to a first state of the control signals, and the control circuit causes contents of the second register to be stored into the first register in response to a second state of the control signals.

Abstract: A conventional semiconductor integrated circuit device suffers from the increasing difficulty in definitely setting the output state of a redundancy circuit as the number of conductor layers increases. To overcome this inconvenience, according to the present invention, a semiconductor integrated circuit device has a first semiconductor chip having a nonvolatile memory for storing redundancy information, and has a second semiconductor chip having a conversion circuit for converting the redundancy information output in the form of serial data from the nonvolatile memory into parallel data and a redundancy circuit of which the output state is definitely set by receiving the parallel data output from the conversion circuit.

Abstract: An improved memory for graphics displays includes an improved memory cell. Data may be written and read from the single bit cell simultaneously, eliminating the need for additional memory circuits to service an N column driver for a display. Additionally, the architecture of the memory allows for a signal input port for writing the data to the cell while allowing for multiple parallel output ports for reading the data. The unique architecture eliminates the need for addressing logic and refresh circuitry for display applications.

Abstract: A control system includes a nonvolatile memory chip and a controller. The controller transfers a group of data from exterior to the nonvolatile memory chip based on the capacity of the nonvolatile memory, and enables the programming of the transferred data in the nonvolatile memory chip while transferring a new group of data. When transferring the group of data to the memory chip, the controller determines whether all the data are transferred from the exterior to the controller, and, if the all the data are transferred to the controller, transfers the group of data to the memory chip. Also, the controller controls the period of the data programming according to the capacity of the nonvolatile memory. Thus, data transfer and program operations are performed at the same time regardless of the memory capacity.

Abstract: Integrated circuit memory devices include a memory cell array that is configured to output data bits in parallel at a first data rate. An output circuit is configured to serially output the data bits to an external terminal at the first data rate in a normal mode of operation, and to serially output the data bits to the external terminal at a second data rate that is lower than the first data rate in a test mode of operation. Accordingly, the memory cell array can operate at a first data rate while allowing the output circuit to output data to an external terminal at a second data rate that is lower than the first data rate, in a test mode of operation.

Abstract: A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.

Abstract: A nonvolatile memory device, in a continuous read operation, requires no dummy bytes between receipt of a read command and commencement of a scanning out of a first target data byte. The highest order bits of a range of possible target data bytes are speculatively read while only a partial set of the highest order address bits are received. The proper set of highest order target data bits is available and scanned out at a time a complete target data address is received. During this scan out time, the remainder of the target data byte is read and prepared for scanning out starting at the next highest order bit. In this way, the data byte targeted by a read command is available immediately and continuously after receipt of the full read command and address.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: Data can be buffered for an integrated circuit memory device by converting a plurality of serial data bits into a parallel format such that even ones of the plurality of serial data bits are provided at a first conversion output node and odd ones of the plurality of serial data bits are provided at a second conversion output node wherein a first odd data bit, a first even data bit, a second odd data bit, and a second even data bit comprise four consecutive data bits of the plurality of serial data bits. The first even and odd data bits from the first and second conversion output nodes are provided at first and second latch output nodes during a first period of time, and the second even and odd data bits from the first and second conversion output nodes are provided at third and fourth latch output nodes during a second period of time wherein the first and second periods of time are non-overlapping.

Abstract: A filter register bank, for example, for a CAN module provides parallel and serial access. The filter bank comprises a plurality of memory cells arranged in a matrix of columns and rows, wherein for parallel access all memory cells within a row are selectable and coupled with a first plurality of bus lines and for serial access all memory cells within a column are selectable and coupled with a second plurality of bus lines.

Abstract: An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. The first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. As a result, the external outputting of data can be brought forward in time, and the operating frequency can thus be increased.

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract: A circuit for converting signals between a memory interface and a memory array is disclosed. The memory interface is not the same type as the memory array such that the signals between the interface and the array need to be synchronized and translated. The circuit includes an interface converter for shifting the logic levels of the signals between the memory interface and the memory array. Furthermore, the circuit has a translation block for translating and synchronizing the signals. In this respect signals between the memory array and the memory interface are synchronized and translated such that the memory array can be used with a memory interface of a different type.

Abstract: A FIFO memory device for use in data transfer between data processing apparatuses having different data bus widths, has an input circuit 11 with a data bus width of k bits, an output circuit 12 with a data bus width of N×k bits (where N>1) that outputs data within the FIFO memory device, a writing pointer 2 that points to a data writing address of the FIFO memory device, a reading pointer 4 that points to a data reading address of the FIFO memory device, and a valid/invalid indicating circuit 6 that indicates whether or not data output to the output circuit 12 is valid.

Abstract: An integrated memory comprises a memory cell array with memory cells and a connection area for externally tapping data of the memory cells which are to be read out. The memory is operated using a prefetch architecture, in which, when there is a memory access operation, a first data group of memory cells from a first zone and a second data group of further memory cells from a second zone of the memory cell array are fed in parallel to an output circuit and the first and second data groups are output successively via the connection area. The first and second zones are always defined for a plurality of memory access operations in such a way that the first data group has a shorter signal transit time to the connection area than the second data group. As a result, the external outputting of data can be brought forward in time, and the operating frequency can thus be increased.

Abstract: Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.

Abstract: A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.

Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

Abstract: The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/serial converted by a parallel/serial converter circuit (21) in synchronism with a clock signal cycle are output for every cycle when the column address signal (CASADR) is changed. Parallel data input to the memory block and serial/parallel converted by a serial/parallel converter circuit (25) in synchronism with the clock signal cycle are written in the memory cell array. In this way, the access specification that the column address strobe signal is varied once per n cycles of the clock signal allows for a more rapid memory operation.

Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

Abstract: Disclosed is low power type Rambus DRAM including top/bottom memory bank units respectively comprising a plurality of banks for storing data, top and bottom serial/parallel shifter units, an interface logic circuit unit, a delay lock loop (DLL) unit and an input/output block unit. The top serial/parallel shifter unit is connected between the top memory bank unit and the input/output block unit and the bottom serial/parallel shifter unit is connected between the bottom memory bank unit and the input/output block unit. The interface logic circuit unit generates a signal for selecting the top or the bottom memory bank unit according to read or write command received from the external. The DLL unit generates a clock signal according to the signal outputted from the interface logic circuit unit. The input/output block unit generates a signal for selectively controlling the operation of top and bottom serial/parallel shifter units by buffering the clock signal generated from the DLL unit.

Abstract: A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks.

Abstract: A semiconductor integrated circuit having therein a plurality of memories, realizing an improved yield by efficiently repairing a defective bit in a memory. This semiconductor integrated circuit has: a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code or not and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the setting information from the setting circuit, converting the setting information to parallel data, and transferring the parallel data to the plurality of circuit blocks.

Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

Abstract: A multiport memory has a plurality of RAMs and a port expansion unit electrically connected to access ports of the RAMs. The port expansion unit includes an input circuit which allows access control information for activating the RAMs in parallel every memory cycles to be collectively inputted thereto by a plurality of memory cycles, a timing generator which generates internal clock signals capable of serially prescribing each memory cycle plural times during one cycle of a clock signal (ck), and a logic circuit capable of sequentially supplying the access control information inputted to the input circuit to the plurality of RAMs in parallel in parts every serial memory cycles synchronized with the internal clock signals. The port expansion unit allows access to the access ports with the plurality of RAMs as a single multiport memory apparently.

Abstract: Outside core circuit, link circuits are concentratedly arranged in an LT link portion. The LT link information sent from the LT link portion is serially transferred to transfer control circuit. Transfer control portion converts the serially transferred link information to parallel information, and transfers the parallel information to latch circuits arranged in the core circuit and corresponding to circuits requiring the LT link information. An influence on an interconnection layout by laser trimmable link elements is eliminated.

Abstract: A circuit having an address circuit and a memory. The address circuit may be configured to (i) receive an address as a parallel input signal and as a serial input signal, (ii) present the address as an output address in one of an asynchronous mode, a synchronous mode, and a shift mode, and (iii) change the second address one by unit in a counter mode. The memory may be configured to receive the output address.

Abstract: A synchronous semiconductor memory device includes a plurality of main data lines each coupled between a block sense amplifier array and a data output buffer. Each main data line prefetches a plurality of cell data segments from memory cells corresponding to an input/output port and transmits the cell data to the data output buffer. The memory device also includes a pass/latch part connected to one or more corresponding block sense amplifiers within a corresponding block sense amplifier array. The pass/latch part receives a plurality of cell data segments in parallel from the block sense amplifiers and transmits them in series to a corresponding main data line. This invention reduces a chip size and peak electric current of the semiconductor device by minimizing the number of main data lines required for prefetch operations.

Abstract: A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

Abstract: A semiconductor integrated circuit can efficiently repair a defective bit in a memory and comprises a plurality of circuit blocks (RAM macro cells) each having an identification code coincidence detecting circuit for determining whether an input identification code coincides with a self identification code and a reception data latch and performing an operation according to latched data; a setting circuit capable of setting the identification code and information corresponding to the identification code and serially outputting the set information; and a control circuit capable of sequentially reading the set information from the setting circuit, converting the set information to parallel data, and transferring the parallel data to the plurality of circuit blocks. Each of the plurality of circuit blocks captures and holds the set information transferred when the identification code coincidence detecting circuit determines that the input identification code and the self identification code coincide.

Abstract: An interface circuit providing serial access to a non-volatile memory in an integrated circuit has at least two memory-access scan registers and at least one selection scan register coupled in common to a data input terminal of the integrated circuit. These registers are also coupled through a multiplexer to a data output terminal of the integrated circuit. The memory-access scan registers receive serial data such as address data and data to be written in the non-volatile memory at the specified addresses. The selection scan register receives a code for selecting the memory-access scan registers. Serial access to the non-volatile memory is speeded up because the memory-access scan registers can be accessed individually.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: A data input/output circuit includes an S/P data conversion circuit which converts serial data input to a data terminal into a parallel data and transmits the parallel data to write data lines, a P/S data conversion circuit which converts parallel data on read data lines to serial data and outputs the serial data to the data terminal, and an input/output test circuit placed between the write data lines and the read data lines. The input/output test circuit responds to an input/output test signal to directly transfer data on the write data lines respectively to the read data lines without passing them through a memory cell array.

Abstract: A nonvolatile semiconductor memory device includes nonvolatile memory cells (C), constant voltage circuits for applying one of different verify voltages to control gates of the nonvolatile memory cells C in response to control data introduced into the memory device from the exterior, and writing and sensing circuit circuits for applying a potential to drains of the nonvolatile memory cells C in response to write data introduced into the memory device and for detecting and amplifying currents between drains and sources of the nonvolatile memory cells. By dividing the memory cell array 501 and a serial register 502 into some parts and by connecting an external SRAM 503 so as to progress the transfer of data from the memory cell array 501 to the serial register 502 and the transfer of data from the serial register 502 to the external SRAM 503 in parallel, the read speed is increased.

Abstract: Even input bit lines, a first latch circuit group and a second latch circuit group are provided in a logical circuit. The first latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a first timing. The second latch circuit group has a plurality of latch circuits which simultaneously latch a plurality of signal bits propagating the even input bit lines, respectively, in a second timing. The output ends of a plurality of latch circuits are wired-OR to a first node, the plurality of latch circuits latching signal bits which propagate one half of the even input hit lines. The output ends of a plurality of latch circuits are wired-OR to a second node, the plurality of latch circuits latching signal bits which propagate remaining one half of the even input bit lines. The first and the second nodes, are wired-OR to a third node.

Abstract: A semiconductor memory circuit includes a plurality of memory cell arrays arranged in rows and columns. A decoder circuit selects a predetermined number of memory cell arrays from among the plurality of the memory cell arrays. Sense amplifiers sense data read from selected memory cell arrays. The plurality of memory cell arrays are grouped into a first type of memory cell arrays each having a redundant memory cell and a second type of memory cell arrays each having no redundant memory cell.

Abstract: A transmission device and an integrated circuit improved in quality and reliability of digital transmission control. A memory stores an input signal, write address generating means generates a write address for writing in the memory, and read address generating means generates a read address for reading from the memory. Phase state monitoring means monitors a transition from a steady phase state in which writing/reading in/from the memory is normally performed or from a startup state to a coincident phase state in which address values of the write and read addresses coincide with each other or to an unstable phase state in which a phase fluctuation margin is one-sided. When the coincident phase state or the unstable phase state is detected, reset signal output means outputs a reset signal to the write and read address generating means such that the phase relation between the write and read addresses is brought to an optimum phase relation.

Abstract: A SDR and QDR converter and an interface, a motherboard and a memory module interface using the same. The converter of SDR and QDR has a QDR interface, a SDR interface and a conversion core. The QDR interface is used to exchange a signal with QDR devices. The SDR interface is used to exchange a signal with SDR devices. The conversion core is used to convert QDR command and data formats into SDR command and data formats, and to convert SDR command and data formats into QDR command and data formats.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: Outside core circuit, link circuits are concentratedly arranged in an LT link portion. The LT link information sent from the LT link portion is serially transferred to transfer control circuit. Transfer control portion converts the serially transferred link information to parallel information, and transfers the parallel information to latch circuits arranged in the core circuit and corresponding to circuits requiring the LT link information. An influence on an interconnection layout by laser trimmable link elements is eliminated.

Abstract: A data input/output circuit includes an S/P data conversion circuit which converts serial data input to a data terminal into a parallel data and transmits the parallel data to write data lines, a P/S data conversion circuit which converts parallel data on read data lines to serial data and outputs the serial data to the data terminal, and an input/output test circuit placed between the write data lines and the read data lines. The input/output test circuit responds to an input/output test signal to directly transfer data on the write data lines respectively to the read data lines without passing them through a memory cell array.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.