Abstract: There are provided a memory controller and a memory system having the same. A memory controller includes: a command queue for queuing commands and outputting command information including information of a previous command and a subsequent command; a command detector for outputting a detection signal according to the command information; and a command generator for generating the command and outputting a management command for managing a last command immediately following the previous command in response to the detection signal.

Abstract: A data storage device may include a nonvolatile memory apparatus and a controller. The controller may be configured to translate a logical address into a physical address when receiving a host command (such as a write command or a read command) including the logical address from a host device, to generate a pre-command including the physical address, to transmit the generated pre-command to the nonvolatile memory apparatus before completing one or more remaining operations of the operations used to process the host command, and to transmit a confirm command to the nonvolatile memory apparatus when the remaining operations are complete. The controller may perform the remaining operations and the transmission of the pre-command to the nonvolatile memory apparatus at the same time.

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

Abstract: A memory includes a memory array, a sense amplifier, and a reference circuit. The memory array includes a memory cell. The sense amplifier includes a first terminal coupled to the memory cell and a second terminal. The reference circuit includes a first reference cell, a second reference cell, and a switch. The first reference cell has a first reference threshold voltage for providing a first reference current, based on a first reference word line voltage. The second reference cell has a second reference threshold voltage for providing a second reference current, based on a second reference word line voltage. The switch selectively provides one of the first and the second reference currents to the second terminal in response to a control signal. The first and the second reference word line voltages correspond to different voltage levels.

Abstract: Systems and methods are provided for digital transport of paramagnetic particles. The systems and methods may include providing a magnetic garnet film having a plurality of magnetic domain walls, disposing a liquid solution on a surface of the magnetic garnet film, wherein the liquid solution includes a plurality of paramagnetic particles, and applying an external field to transport at least a portion of the paramagnetic particles from a first magnetic domain wall to a second magnetic domain wall of the plurality of magnetic domain walls.

Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).

Abstract: A memory device with a magnetic field generator and method of operating and manufacturing the same. In the device and method, a magnetic memory may includes a magnetic tunneling junction (MTJ) cell, a transistor, and a bit line, and a magnetic field generator external to the magnetic memory to generate a global magnetic field toward the magnetic memory in a parallel direction to the bit line.

Abstract: In programming a non-volatile memory involving alternately applying a programming pulse and verifying the programming, time is saved in the program verify portion when, depending on the states of the memory cells, a portion of the verify operation is recognized to be superfluous and skipped. Preferably, in a program verify operation relative to a demarcation threshold level for demarcating between two memory states, the verify operation includes a sequence of two verify sub-cycles, the first sub-cycle performing a verify relative to a first threshold level at a predetermined margin below the demarcation threshold level and the second sub-cycle performing a verify relative to a second threshold level which is identical to the demarcation threshold level. Unlike conventional cases, the second sub-cycle is not performed until any one memory cell of the group has been verified to pass the first threshold.

Abstract: A dynamic random access memory (DRAM) device has an array of DRAM cells of rows by columns. Each DRAM cell of the array is coupled with a wordline of a corresponding row and a bitline of a corresponding column. An entry into and an exit from the self-refresh mode are detected by a mode detector and a self-refresh mode signal is provided. An oscillation circuit generates in response to the self-refresh mode signal generates a basic time period. A first frequency divider/time period multiplier changes the basic time period in accordance with a process variation factor relating to the DRAM device. A second frequency divider/time period multiplier further changes the changed time period in accordance with a temperature change factor relating to the DRAM device. In the self-refresh mode, data stored in the DRAM cells is refreshed. In accordance with the two factors, the DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.

Abstract: A semiconductor storage device has a memory cell (501, 502) storing data; bit lines (BL1, BL2) connected to the memory cell, allowing therethrough data input or output to or from the memory cell; a sense amplifier (506a) connected to said bit lines, amplifying data on the bit lines; and a switching transistor (505a) connecting or disconnecting the bit line connected to the memory cell to or from the bit line connected to the sense amplifier. The switching transistor operates differently in a first memory cell access operation and in a second memory cell access operation.

Abstract: A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further includes a word line enable device for asserting a selected one of the word lines and a column select device for asserting a selected one of the bit line pairs. A timing circuit is provided for controlling the word line enable device, the column select device, and the read, write, and refresh operations in response to a word line timing pulse. The read, write, and refresh operation are performed in the same amount of time.

Abstract: A spread polarization transmitter for transmitting at least one light signal comprises a spread-spectrum communication apparatus and a polarization modulator. The spread-spectrum communication apparatus modulates the at least one light signal according to a spread-spectrum modulation technique. The polarization modulator comprises a polarizer and a magnetic bubble waveguide. The polarizer is capable of polarizing the at least one spread-spectrum modulated light signal in a polarized direction. And the magnetic bubble waveguide, which is configured in accordance with a pseudo-random polarization code sequence such that the plurality of magnetic bubble domains assume a time varying position representative of the pseudo-random polarization code sequence, is capable of receiving at least one polarized, spread-spectrum modulated light signal.

Abstract: Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in a semiconductor memory device. In one aspect, a PASR operation is performed by (1) controlling the generation of row addresses by a row address counter during a self-refresh operation and (2) controlling a self-refresh cycle generating circuit to adjust the self-refresh cycle output therefrom. The self-refresh cycle is adjusted in a manner that provides a reduction in the current dissipation during the PASR operation. In another aspect, a PASR operation is performed by controlling one or more row addresses corresponding to a partial cell array during a self-refresh operation, whereby a reduction in a self-refresh current dissipation is achieved by blocking the activation of a non-used block of a memory bank.

Abstract: A first reference current having a first temperature characteristic is generated by a first reference current generating circuit (1) while a second reference current having a second temperature characteristic is generated by a second reference current generating circuit (2). A temperature characteristic multiplying circuit (3) amplifies the first reference current by using a current difference between the first and second reference currents to generate a reference current having a third temperature characteristic higher than the first temperature characteristic, so that a ring oscillator (X) determines a refresh period on the basis of the reference current.

Abstract: A method and apparatus for operating an integrated circuit in an electronic device by controlling the supply voltage to the integrated circuit (IC). A parameter of the IC is measured and used to adjust the supply voltage of the IC. The measured parameter is indicative of the effective channel mobility of the IC. One purpose of adjusting the voltage is to modify the effective channel mobility such that the individual channel currents are substantially constant over a predetermined operating temperature range of the IC. The modification of channel mobility is chosen to set the individual channel currents at levels that either maximizes operating speed, minimizes power consumption, extends the range of operating temperature, or increases the operational reliability of the IC.

Abstract: A Random Access Memory having a fast Clear operation includes a cell array (10) which has a plurality of memory cells arranged in rows and columns. Each of the rows is selected by word lines (12) and the data is output on column lines (14). Each of the word lines (12) is selected by a row decode circuit (20) or a Clear signal through OR gates (22). The Clear signal selects all of the word lines (12) such that each row in the cell array (10) is selected. The bit line associated with each column are pulled to ground through an N-channel transistor (36) and a bit line bar pulled high through a P-channel transistor (38). In addition, the V.sub.CC supply to the array (10) is decoupled from the memory cells by a P-channel transistor (40).

Abstract: In a certain refresh cycle, a certain address is designated as a refresh address, and a read operation for the refresh is conducted. The data thus read out is checked, and, if a correctable error is detected, the corrected data and its address are held in a corrected data register and an address register, respectively. In the succeeding refresh cycles, reading operations for the refresh are conducted for the succeeding addresses. When the same address as that held in the address register is designated again in due time as the refresh address, a writing operation for the refresh is conducted to write back the content of the corrected data register.

Abstract: A magnetic bubble information writing device capable of carrying out writing without erasing old information representing either "0" or "1" at a location, where new information is to be written, by means of only a single hairpin-like conductor loop is disclosed, in which the single hairpin-like conductor loop is disposed at a projecting portion of permalloy patterns, enclosing the portion.