Abstract: A data compression method is used for compressing data indicating a gradient of a route. The data compression method includes: acquiring a gradient table that shows gradient values in respective sections arranged between a starting point of the route and an ending point thereof, the sections including one section and an adjacent section adjacent to the one section: ranking the gradient values; and in a case where the gradient value of the one section and the gradient value of the adjacent section are in a same rank, integrating the gradient value of the one section and the gradient value of the adjacent section and generating a compressed gradient table that shows a distance and a corresponding rank of the section having the same rank.

Abstract: A computer-implemented method, according to one embodiment, includes: receiving tracking information which corresponds to an amount that at least one supplemental data storage drive of an automated data storage library was used during a period of time. The automated data storage library in turn includes: one or more primary data storage drives, and one or more robotic accessors physically configured to access each of the one or more primary data storage drives and the at least one supplemental storage drive. Accordingly, the tracking information is used to calculate a usage fee which corresponds to the amount that the at least one supplemental data storage drive was used during the period of time. Furthermore, the usage fee is sent to a user associated with the automated data storage library.

Abstract: A streaming server can receive a request from a client device to access data about a wellbore environment in a database server. The database server can be communicatively coupled to a server, which can be communicatively coupled to the streaming server. The streaming server can communicate data in a standardized format with the server using a request and response protocol. The streaming server can communicate the wellbore environment data from the database server in a streaming format with the client device.

Abstract: Techniques for configurable link interfaces for a memory device are described. In some examples, memory devices may require periodic link training to support data transfer with a host device at relatively fast rates. However, in some managed memory applications, memory dies of a memory device may have integrated controllers that do not support such link training, and accordingly may not support some clock rates or data rates. To support data transfers between a host device and a memory device at relatively fast clock rates or data rates without link training, a memory die may be fabricated with a configurable link interface that can support different mappings between components and operation according to different clock rates or data rates. In some examples, a memory die may be fabricated in a manner that supports configurable mappings between an array and a data channel interface that are operable according to different multiplexing and serialization.

Abstract: An image forming apparatus includes an execution unit, a power supply control unit, and a setting unit. In a case where the power supply control unit receives a shutdown request while the execution unit is executing first repair processing for a predetermined partition in accordance with reservation information, the setting unit changes the reservation information from the first repair processing to second repair processing that takes a shorter time than the first repair processing.

Abstract: The present disclosure describes techniques for entity classification and data enrichment of data sets. A data enrichment system is disclosed that can extract, repair, and enrich datasets, resulting in more precise entity resolution and classification for purposes of subsequent indexing and clustering. Disclosed techniques may include performing entity recognition to identify segments of interest that relate to an entity. Related data may be analyzed for classification, which can be used to transform the data for enrichment to its users.

Abstract: In at least one embodiment of the disclosure, a method includes detecting an error in a local memory shared by redundant computing modules executing in delayed lockstep. The method includes pausing execution in the redundant computing modules and handling the error of the local memory. The method includes resuming execution in delayed lockstep of the redundant computing modules in response to the handling of the error.

Abstract: A technology is provided for call failure backoff in a computing service environment. An allowable call failure rate is defined for application programming interface (API) calls sent to one or more endpoints. Each endpoint may use a token bucket containing a plurality of tokens, wherein a single token is defined as being equal to one API call failure. A number of tokens in the token bucket are determined prior to executing an API call to the one or more endpoints. A health status of the one or more endpoints is identified according to the number of tokens in the token bucket. The API calls to the one or more endpoints having the determined number of tokens in the token bucket that are equal to zero or may be delayed for a predetermined backoff time period.

Abstract: Subject matter disclosed herein relates to read and write processes of a memory device.

Abstract: An apparatus for capturing images. In one embodiment, the apparatus comprises: a coded lens array including a plurality of lenses arranged in a coded pattern and with opaque material blocking array elements that do not contain lenses; and a light-sensitive semiconductor sensor coupled to the coded lens array and positioned at a specified distance behind the coded lens array, the light-sensitive sensor configured to sense light transmitted through the lenses in the coded lens array.

Abstract: A skyrmion generation method capable of reducing power consumption in generating skyrmions is provided. In the skyrmion generation method, an electric field is applied to an insulating magnetic body having a chiral crystal structure locally using an electric field generation unit while a magnetic field is applied from a magnetic field generation unit to the magnetic body. As a result, a skyrmion is generated in the magnetic body. The magnetic body preferably has a thin film shape with a thickness in a range of 2 to 300 nm at least partially, and the magnetic field generation unit preferably applies the magnetic field to a surface of the magnetic body substantially perpendicularly.

Abstract: A memory array and an integrated circuit are disclosed. The memory array includes first and second banks of memory elements and five switches. Each memory element of the first bank of memory elements is coupled to an upper rail and to a first node, while each memory element of the second bank of memory elements is coupled to a second node and to a lower rail. The first switch is coupled between the first node and the second node; the second switch is coupled between the first node and the lower rail; and the third switch is coupled between the second node and the upper rail. A fourth switch is coupled between the first node and a voltage that is one diode drop above the lower rail, and a fifth switch is coupled between the second node and a voltage that is one diode drop below the upper rail.

Abstract: Methods, computing systems and computer program products implement embodiments of the present invention that include configuring, at a first time, a clustered storage system comprising multiple modules to store and process storage requests for respective sets of data objects. While processing the storage requests, respective subsets of the data objects having one or more data errors are identified, and at a second time subsequent to the first time, respective modules storing each of the data objects having at least one data error are identified. computing, based on the identified modules, a frequency distribution of the identified data errors in the data objects over the multiple modules. Based on the frequency distribution, a failure in a given module is identified, and the identified module is removed from the storage system. In some embodiments, prior to the second time, the data objects can be redistributed among the modules of the storage system.

Abstract: A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to the rendered fragment data being written out to memory, write out circuitry configured to write a compressed representation of the rendered fragment data for a tile in the tile buffer to memory, and processing circuitry. The processing circuitry identities, based on the writing of rendered fragment data to the tile buffer, any blocks comprising sampling positions within a tile having the same data value associated with each sampling position in the block, and to, when such a block of sampling positions is identified, trigger the write out circuitry to write a compressed representation of the block to the memory.

Abstract: A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time environment for a computing platform a temperature is obtained from a thermal sensor monitoring the memory module. The memory module is in a given memory module with thermal sensor configuration that includes the memory device. An approximation of a temperature for the memory device is made based on thermal information associated with the given configuration of the memory module and the obtained temperature. The configured thermal management control for the memory device is implemented based on the approximated temperature. Other implementations and examples are also described in this disclosure.

Abstract: Low complexity partial parallel architectures for performing a Fourier transform and an inverse Fourier transform over subfields of a finite field are described. For example, circuits to perform the Fourier transforms and the inverse Fourier transform as described herein may have architectures that have simplified multipliers and/or computational units as compared to traditional Fourier transform circuits and traditional inverse Fourier transform circuits that have partial parallel designs. In a particular embodiment, a method includes, in a data storage device including a controller and a non-volatile memory, the controller includes an inverse Fourier transform circuit having a first number of inputs coupled to multipliers, receiving elements of an input vector and providing the elements to the multipliers. The multipliers are configured to perform calculations associated with an inverse Fourier transform operation.

Abstract: A variable resistance memory according to an embodiment includes: a first wiring; a second wiring provided above the first wiring and intersecting with the first wiring; a third wiring provided above the second wiring and intersecting with the second wiring; a first variable resistance element provided in an intersection region between the first wiring and the second wiring, the first variable resistance element including a first variable resistance layer formed on the first wiring, and an ion source electrode provided on the first variable resistance layer and penetrating through the second wiring, the ion source electrode being connected to the second wiring and including metal atoms; and a second variable resistance element provided in an intersection region between the second wiring and the third wiring, the second variable resistance element including a second variable resistance layer formed on the ion source electrode.

Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.

Abstract: Systems, methods and computer storage apparatuses for synthesizing terrain elevations under overpasses are described herein. An embodiment includes identifying one or more spans across an overpass in an overpasses model, where the overpasses model includes information for one or more overpasses and respective locations and widths of the spans. The embodiment associates one or more terrain elevation values with the one or more identified spans, where the terrain elevation values can be included in an elevation model corresponding to the overpasses model. The embodiment further includes interpolating terrain elevation values for one or more points across the identified spans and updating the elevation model with the interpolated terrain elevation values.

Abstract: A semiconductor device, a confidential data control system and a confidential data control method are provided capable of safeguarding confidential data even in cases of unauthorized access. Control is performed to alternately store confidential data segments of divided confidential data and respective corresponding segment parity data in a memory. When reading the confidential data, errors in the confidential data segment are checked for with the segment parity data, corrected when an error has occurred, and read. The confidential data is not stored altogether in the memory, and so the confidential data is rendered difficult to discern even in cases in which unauthorized access (hacking) has occurred to the confidential data control system.

Abstract: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a topological state including at least one winding rotation of a magnetisation vector of the domain wall. Preferably the magnetic bubble is confined in an island of magnetic material, preferably of maximum dimension less than 1 ?m.

Abstract: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a topological state including at least one winding rotation of a magnetisation vector of the domain wall. Preferably the magnetic bubble is confined in an island of magnetic material, preferably of maximum dimension less than 1 ?m.

Abstract: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a topological state including at least one winding rotation of a magnetisation vector of the domain wall. Preferably the magnetic bubble is confined in an island of magnetic material, preferably of maximum dimension less than 1 ?m.

Abstract: Data, stored in MRAM-cells should be protected against misuse or read-out by unauthorized persons. The present invention provides an array of MRAM-cells provided with a security device for destroying data stored in the MRAM-cells when they are tampered with. This is achieved by placing a permanent magnet adjacent the MRAM-array in combination with a soft-magnetic flux-closing layer. As long as the soft-magnetic layer is present, the magnetic field lines from the permanent magnet are deviated and flow through this soft-magnetic layer. When somebody is tampering with the MRAM-array, e.g. by means of reverse engineering, and the flux-closing layer is removed, the flux is no longer deviated and affects the nearby MRAM-array, thus destroying the data stored in the MRAM-cells.

Abstract: A nonvolatile loop magnetic memory having a magnetically writeable nonvolatile magnetic memory element and a loop magnetic shunt. The loop magnetic shunt has a slot through a loop of the loop magnetic shunt, the slot forming first and second ends in the loop magnetic shunt, the first and second ends arranged to focus a magnetic field on the magnetically writeable nonvolatile magnetic memory element. The magnetically writeable nonvolatile magnetic memory element is located between the first and second ends of the loop magnetic shunt. A magnetic write coil is wrapped around the loop magnetic shunt.

Abstract: A method of storing one or more bits of information comprising: forming a magnetic bubble; and storing a said bit of information encoded in a typology of a domain wall of said magnetic bubble. Preferably a bit is encoded using a symmetric topological state of the domain wall and a topological state including at least one winding rotation of a magnetisation vector of the domain wall. Preferably the magnetic bubble is confined in an island of magnetic material, preferably of maximum dimension less than 1 ?m.

Abstract: A ferroelectric layer (104) is sandwiched between a lower electrode layer (103) and an upper electrode (105). When a predetermined voltage (DC or pulse) is applied between the lower electrode layer (103) and the upper electrode (105) to change the resistance value of the ferroelectric layer (104) to switch a stable high resistance mode and low resistance mode, a memory operation is obtained. A read can easily be done by reading a current value when a predetermined voltage is applied to the upper electrode (105).

Abstract: A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time environment for a computing platform a temperature is obtained from a thermal sensor monitoring the memory module. The memory module is in a given memory module with thermal sensor configuration that includes the memory device. An approximation of a temperature for the memory device is made based on thermal information associated with the given configuration of the memory module and the obtained temperature. The configured thermal management control for the memory device is implemented based on the approximated temperature. Other implementations and examples are also described in this disclosure.

Abstract: Systems and methods are provided for digital transport of paramagnetic particles. The systems and methods may include providing a magnetic garnet film having a plurality of magnetic domain walls, disposing a liquid solution on a surface of the magnetic garnet film, wherein the liquid solution includes a plurality of paramagnetic particles, and applying an external field to transport at least a portion of the paramagnetic particles from a first magnetic domain wall to a second magnetic domain wall of the plurality of magnetic domain walls.

Abstract: A magnetic memory device includes a recording layer, a reference layer, a first input portion and a second input portion. The recording layer has perpendicular magnetization direction and a plurality of magnetic domains, and the reference layer corresponds to a portion of the recording layer and has a pinned magnetization direction. The recording layer has a data storage cell wherein a plurality of data bit regions each including a magnetic domain are formed. The magnetic domain corresponds to an effective size of the reference layer. The first input portion inputs at least one of a writing signal and a reading signal. The second input portion is electrically connected to the recording layer and inputs a magnetic domain motion signal in order to move data stored in a data bit region of the recording layer to an adjoining data bit region.

Abstract: A magnetic memory device is provided. The magnetic memory device may include a memory track in which a plurality of magnetic domains is formed so that data bits, each of which may be a magnetic domain, are stored in an array. The memory track may be formed of an amorphous soft magnetic material.

Abstract: Data, stored in MRAM-cells (12) should be protected against misuse or read-out by unauthorised persons. The present invention provides an array (10) of MRAM-cells (12) provided with a security device (14) for destroying data stored in the MRAM-cells (12) when they are tampered with. This is achieved by placing a permanent magnet (16) adjacent the MRAM-array (10) in combination with a soft-magnetic flux-closing layer (18). As long as the soft-magnetic layer (18) is present, the magnetic field lines (20) from the permanent magnet (16) are deviated and flow through this soft-magnetic layer (18). When somebody is tampering with the MRAM-array (10), e.g. by means of reverse engineering, and the flux-closing layer (18) is removed, the flux is no longer deviated and affects the nearby MRAM-array (10), thus destroying the data stored in the MRAM-cells (12).

Abstract: Improved clock and data recovery involves transmitting one or more null frames prior to transmitting a sync frame. A receiving component detects for the sync frame to lock to a data signal sent on a signal path by a transmitting component. The one or more null frames transmitted prior to the sync frame results in a settling of the signal path prior to reception of the sync frame, thereby lessening or removing the effects of previously sent data on the sync frame.

Abstract: Electronic memory devices fabricated using nanolithography techniques enables rapid and reliable storage of data on a substrate. One such device includes a memory access head, which includes a conductive member and an insulative member. The conductive member includes a proximal conductive tip, a distal conductive tip, and a body portion. The body portion is embedded in the insulative member. The device further includes a substrate adjacent to the distal conductive tip, an electrolyte disposed between the distal conductive tip and the substrate; and a microchip in communication with the proximal conductive tip.

Abstract: A memory device driving circuit is disclosed which drives a memory device including a first electrode, a second electrode, and a memory layer interposed between the first electrode and the second electrode. The memory device driving circuit may include a main driver connected to the memory device, to drive the memory device, and a secondary driver connected between the memory device and the main driver, to control a set resistance of the memory device. The memory device driving circuit may freely adjust the set resistance of the memory device, to maintain the resistance of the memory device at a desired value. Accordingly, an improvement in the operation reliability of the memory device may be achieved.

Abstract: A non-volatile memory device that changes the programming step voltage between the source side of the array and the drain side of the array. After the initial programming pulse, a verify operation determines if the cell has been programmed. If the cell is still erased, the initial programming voltage is increased by the step voltage. The step voltage for the lowest word line near the source line is lower than the step voltage for the word line closest to the drain line.

Abstract: A semiconductor apparatus includes an internal layer where a first power supply line to provide a first power supply to transistors in a layout cell and an internal cell line to connect transistors in the layout cell are placed, an input/output line connected with an input/output terminal of the layout cell is placed, and a shield line which is placed between the internal layer and the input/output line so as to cover the internal layer and the first power supply line.

Abstract: The storage apparatus includes a plurality of storage devices for storing information, a control unit controlling the storage device, a switching unit switching a connection between the storage device and the control unit, and a network different from the connection by the switching unit and connecting the storage device and the control unit. Reading of information from the storage device and writing of information into the storage device is performed by the control unit through the switching unit, and when a fault occurs in the storage device, a fault recovery command is sent from the control unit through the network to the corresponding storage device or the switching unit.

Abstract: A method and system is disclosed for reducing proton and heavy ion SEU sensitivity of a static random access memory (SRAM) cell. A first passive delay element has been inserted in series with an active delay element in a first feedback path of the SRAM cell, and a second passive delay element has been inserted in a second feedback path of the SRAM cell. The passive delay elements reduce the proton SEU sensitivity of the SRAM cell, and the active delay element reduces the heavy ion sensitivity of the SRAM cell. The passive delay elements also protect the SRAM cell against SEUs that may occur when the SRAM cell is in dynamic mode.

Abstract: MRAM structures employ the magnetic properties of layered magnetic and non-magnetic materials to read memory storage logic states. Improvements in switching reliability may be achieved by altering the shape of the layered magnetic stack structure. Forming recessed regions with sloped interior walls in an ILD layer prior to depositing the layered magnetic stack structure produces a significant advantage over the prior art by allowing a CMP process to be used to define the magnetic bit shapes. The sloped interior walls of the recessed regions, which is singular to the present invention, provide a unique formation and shaping of the magnetic stack structure, which may reduce the magnetic coupling effect between magnetic layers of the magnetic stack structure.

Abstract: The present disclosure relates to a solid-state storage device. In one arrangement, the storage device comprises a memory device comprising one of an atomic resolution storage (ARS) device and a magnetic random access memory (MRAM) device, a controller, and an integral connector that is used to directly connect the storage device to another device.

Abstract: Methods and apparatuses to generate and to access compressed and indexed elevations of Digital Elevation Models. In one aspect of the invention, a method to store elevation data includes: compressing elevation data of a first portion of a Digital Elevation Model (DEM) to generate first compressed elevation data; storing the first compressed elevation data in a storage location pointed to by a first index; and storing the first index. In another aspect of the invention, a method to retrieve elevation data includes: locating a first compressed portion of a Digital Elevation Model (DEM) using a first index; and decompressing the first compressed portion to retrieve first elevation data for at least one sample point in the Digital Elevation Model. The Digital Elevation Model has a plurality of compressed portions which includes the first compressed portion; and the first index points to a storage location where the first compressed portion is stored.

Abstract: A process of fabricating a molecular electronic device that preserves the integrity of the active molecular layer of the electronic device during processing is described. In one aspect, a passivation layer is provided to protect a molecular layer from degradation during patterning of the top wire layer. A molecular electronic device structure and a memory system that are formed from this fabrication process are described.

Abstract: This invention relates to the embedding of a microelectronic chip into printed media, including but not limited to books and magazines. The microelectronics component is switched on by opening the printed medium or by triggering an on /off mechanism. The invention may have various embodiments that can be to project speech, music or other tonal signals upon operation.

Abstract: Supply section supplies performance data of a music piece, and a processor, coupled with a display device and the supply section, controls the display device to display a music score of the music piece using a predetermined basic display block. On the basis of the supplied performance data, the processor detects music score marks included in each of predetermined music piece sections of the music piece. Then, for each of the music piece sections, the processor sets the detected music score marks to be placed in a single basic display block or dividedly in a plurality of the basic display blocks. If any one of the music piece sections includes too many music score marks, the processor dividedly allocates the music score marks to two or more basic display blocks. Thus, for each of the music piece sections, the music score marks can be displayed using a variable number of the basic display block.

Abstract: Filtering is performed on original waveform to remove components of a predetermined frequency band from the waveform, and dividing positions of the original waveform data are determined on the basis of envelope levels of the filtered waveform. The dividing positions may be determined on the basis of differentiation of an envelope of the filtered waveform. Rise positions in the original waveform data are detected, and one rise position may be selected from among one or more rise positions detected within a predetermined range of the original waveform and extracted as a dividing position of the original waveform. Presumed beat positions in the original waveform may be detected, and rise positions of the original waveform may be detected within predetermined ranges corresponding to the presumed beat positions.

Abstract: A first substrate has a plurality of bumps and a second substrate has a plurality of openings at positions in registration with the plurality of bumps when the first and second substrates are placed one on top of the other in a confronting manner. The first and second substrates are put together by fusing a sealing wall formed on the second substrate, to hermetically seal an electronic device lying on the first substrate therein. Gas that may be generated upon fusing of the sealing wall can be effectively removed through the openings in the second substrate.

Abstract: A ferroelectric memory having a dielectric layer comprised of SiOF, and a method for fabricating the SiOF dielectric layer are provided. Degradation in the ferroelectric properties due to hydrogen atoms can be prevented by depositing a SiOF dielectric layer using SiF4, instead of depositing a SiO2 dielectric layer, which has been conventionally used. The ferroelectric memory device, and the method of making the device, provide a stabilized device having less or no degradation in the ferroelectric properties.

Abstract: A module includes a semiconductor device, a phase adjustment circuit generating a second clock so that a phase adjustment signal output from the semiconductor device and a first clock have a predetermined phase relationship, and an output circuit that is provided in the semiconductor device and generates the phase adjustment signal from the second clock.

Abstract: A dynamic random access memory device and a &mgr;BGA package for the device use multiple pads for a reference voltage. The device includes n input receivers, n data input pads, and x reference voltage pads. Each input receiver operates synchronously with a clock signal and includes a differential amplifying unit that generates an output data signal according to a voltage difference between an input data signal and a reference voltage. The n data input pads respectively connect to the n input receivers and transfer the input data signals to the input receivers. The n input receivers are divided into x groups according to their positions, and the x reference voltage input pads respectively connect to the x groups of input receivers for commonly applying the reference voltage to the input receivers in the respective groups. Each reference voltage input pad can connect to its group of input receivers through one or multiple common lines. The package includes a first ball that receives the reference voltage.