Including Magnetic Element Patents (Class 365/243.5)
  • Patent number: 8687413
    Abstract: A magnetic memory unit includes a tunneling barrier separating a free magnetic element and a reference magnetic element. A first phonon glass electron crystal layer is disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element. A second phonon glass electron crystal layer also be disposed on a side opposing the tunneling barrier of either the free magnetic element or the reference magnetic element to provide a Peltier effect on the free magnetic element and the reference magnetic element.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: April 1, 2014
    Assignee: Seagate Technology LLC
    Inventors: Yuankai Zheng, Haiwen Xi, Dimitar V. Dimitrov, Dexin Wang
  • Patent number: 8675401
    Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The method also includes comparing the first bit line read voltage with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: March 18, 2014
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Kang Yong Kim, Dimitar V. Dimitrov, Henry F. Huang
  • Patent number: 8416614
    Abstract: A method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state. The first read current is less than the second read current. Then the first bit line read voltage is compared with the second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 9, 2013
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Ran Wang, Dimitar V. Dimitrov
  • Patent number: 8411495
    Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: April 2, 2013
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Kang Yong Kim, Dimitar V. Dimitrov, Henry F. Huang
  • Patent number: 8400867
    Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
    Type: Grant
    Filed: December 12, 2011
    Date of Patent: March 19, 2013
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
  • Patent number: 8374048
    Abstract: A method and system for providing a magnetic junction usable in a magnetic device are described. The magnetic junction includes a pinned layer, a nonmagnetic spacer layer, and a free layer. The nonmagnetic spacer layer is between the pinned layer and the free layer. The free layer has a magnetic anisotropy, at least a portion of which is a biaxial anisotropy. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: February 12, 2013
    Assignee: Grandis, Inc.
    Inventor: Dmytro Apalkov
  • Patent number: 8358531
    Abstract: Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: January 22, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Gurtej Sandhu
  • Patent number: 8331139
    Abstract: Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Daniel C. Worledge
  • Patent number: 8325513
    Abstract: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: December 4, 2012
    Assignee: Seagate Technology LLC
    Inventors: Thomas William Clinton, Werner Scholz
  • Patent number: 8248840
    Abstract: A Magnetoresistive Random Access Memory (MRAM) integrated circuit includes a substrate, a magnetic tunnel junction region, a magnetic circuit element, and an integrated magnetic material. The magnetic tunnel junction region is disposed on the substrate, and includes a first magnetic layer and a second magnetic layer separated by a tunnel barrier insulating layer. The magnetic circuit element region is disposed on the substrate, and includes a plurality of interconnected metal portions. The integrated magnetic material is disposed on the substrate adjacent to the plurality of interconnected metal portions.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: August 21, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang, Xiaochun Zhu, Kangho Lee
  • Patent number: 8116124
    Abstract: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: February 14, 2012
    Assignee: Seagate Technology LLC
    Inventors: Thomas William Clinton, Werner Scholz
  • Patent number: 8116122
    Abstract: A spin-transfer torque memory apparatus and self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage, the magnetic tunnel junction data cell having a first resistance state and storing the first bit line read voltage in a first voltage storage device. Then applying a low resistance state polarized write current through the magnetic tunnel junction data cell, forming a low second resistance state magnetic tunnel junction data cell. A second read current is applied through the low second resistance state magnetic tunnel junction data cell to forming a second bit line read voltage. The second bit line read voltage is stored in a second voltage storage device.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: February 14, 2012
    Assignee: Seagate Technology LLC
    Inventors: Hai Li, Yiran Chen, Hongyue Liu, Kang Yong Kim, Dimitar V. Dimitrov, Henry F. Huang
  • Patent number: 8116123
    Abstract: A spin-transfer torque memory apparatus and non-destructive self-reference read schemes are described. One method of self-reference reading a spin-transfer torque memory unit includes applying a first read current through a magnetic tunnel junction data cell and forming a first bit line read voltage and storing the first bit line read voltage in a first voltage storage device. The magnetic tunnel junction data cell has a first resistance state. Then the method includes applying a second read current thorough the magnetic tunnel junction data cell having the first resistance state and forming a second bit line read voltage and storing the second bit line read voltage in a second voltage storage device. The first read current is less than the second read current. Then the stored first bit line read voltage is compared with the stored second bit line read voltage to determine whether the first resistance state of the magnetic tunnel junction data cell was a high resistance state or low resistance state.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: February 14, 2012
    Assignee: Seagate Technology LLC
    Inventors: Yiran Chen, Hai Li, Hongyue Liu, Ran Wang, Dimitar V. Dimitrov
  • Patent number: 8102703
    Abstract: A magnetic tunnel junction, including a reference layer having a fixed magnetization direction, a first storage layer having a magnetization direction that is adjustable relative to the magnetization direction of the reference layer by passing a write current through said magnetic tunnel junction, and an insulating layer disposed between said reference layer and first storage layer; characterized in that the magnetic tunnel junction further comprises a polarizing device to polarize the spins of the write current oriented perpendicular with the magnetization direction of the reference layer; and wherein said first storage layer has a damping constant above 0.02. A magnetic memory device formed by assembling an array of the magnetic tunnel junction can be fabricated resulting in lower power consumption.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: January 24, 2012
    Assignee: Crocus Technology
    Inventors: Jean-Pierre Nozières, Bernard Dieny
  • Patent number: 8098541
    Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: January 17, 2012
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
  • Patent number: 8081394
    Abstract: An information recording apparatus has a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled along the fine particles. Summary information may be recorded for plural information recording parts.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: December 20, 2011
    Assignees: Ricoh Company, Ltd., Tohoku University
    Inventors: Migaku Takahashi, Masakiyo Tsunoda, Shin Saito, Tomoyuki Ogawa, Itaru Fujimura, Shigeyoshi Misawa, Toshiyuki Kawasaki
  • Patent number: 8077502
    Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 13, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 8077503
    Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: December 13, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 8004881
    Abstract: In an embodiment, a device is disclosed that includes a magnetic tunnel junction (MTJ) structure. The device also includes a read path coupled to the MTJ structure and a write path coupled to the MTJ structure. The write path is separate from the read path.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 23, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Xiaochun Zhu, Shiqun Gu, Xia Li, Seung H. Kang
  • Patent number: 7995383
    Abstract: A particular magnetic tunnel junction (MTJ) cell includes a side wall defining a first magnetic domain adapted to store a first digital value. The MTJ cell also includes a bottom wall coupled to the side wall and defining a second magnetic domain adapted to store a second digital value.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Seung H. Kang, Xiaochun Zhu
  • Patent number: 7995378
    Abstract: In a particular embodiment, a memory device includes a first memory cell and a second memory cell. The memory device also includes a first bit line associated with the first memory cell and a second bit line associated with the second memory cell. The memory device also includes a source line coupled to the first memory cell and coupled to the second memory cell.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Sei Seung Yoon, Cheng Zhong, Dongkyu Park, Mohamed H. Abu-Rahma
  • Patent number: 7961491
    Abstract: Provided are a data storage device using a magnetic domain wall movement and a method of operating the data storage device. The data storage device includes a magnetic layer which has a plurality of magnetic domains, a current applying unit which applies current for a magnetic domain wall movement to the magnetic layer, and a head for reading and writing, wherein the magnetic layer comprises a plurality of perpendicular magnetic layers formed on a substrate in a plurality of rows and columns, and a horizontal magnetic layer formed on the perpendicular magnetic layers to connect the perpendicular magnetic layers.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: June 14, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-chul Lee, Sung-hoon Choa, Eun-sik Kim
  • Patent number: 7957181
    Abstract: This magnetic memory with a thermally-assisted write, every storage cell of which consists of at least one magnetic tunnel junction, said tunnel junction comprising at least: one magnetic reference layer, the magnetization of which is always oriented in the same direction at the time of the read of the storage cell; one so-called “free” magnetic storage layer, the magnetization direction of which is variable; one insulating layer sandwiched between the reference layer and the storage layer. The magnetization direction of the reference layer is polarized in a direction that is substantially always the same at the time of a read due to magnetostatic interaction with another fixed-magnetization layer called the “polarizing layer”.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: June 7, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Jean-Pierre Nozieres, Ricardo Sousa, Bernard Dieny, Olivier Redon, Ioan Lucian Prejbeanu
  • Patent number: 7952918
    Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-yeong Cho, Yun-seung Shin
  • Patent number: 7940600
    Abstract: A method and apparatus for stray magnetic field compensation in a non-volatile memory cell, such as a spin-torque transfer random access memory (STRAM). In some embodiments, a first tunneling barrier is coupled to a reference structure that has a perpendicular anisotropy and a first magnetization direction. A recording structure that has a perpendicular anisotropy is coupled to the first tunneling barrier and a nonmagnetic spacer layer. A compensation layer that has a perpendicular anisotropy and a second magnetization direction in substantial opposition to the first magnetization direction is coupled to the nonmagnetic spacer layer. Further, the memory cell is programmable to a selected resistance state with application of a current to the recording structure.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 10, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar Dimitrov, Olle Gunnar Heinonen, Dexin Wang, Haiwen Xi
  • Patent number: 7936597
    Abstract: The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits.
    Type: Grant
    Filed: March 25, 2008
    Date of Patent: May 3, 2011
    Assignee: Seagate Technology LLC
    Inventors: Thomas W. Clinton, Michael A. Seigler, Mark W. Convington, Werner Scholz
  • Patent number: 7933146
    Abstract: Electronic devices that include (i) a magnetization controlling structure; (ii) a tunnel barrier structure; and (iii) a magnetization controllable structure including: a first polarizing layer; and a first stabilizing layer, wherein the tunnel barrier structure is between the magnetization controlling structure and the magnetization controlling structure and the first polarizing layer is between the first stabilizing layer and the tunnel barrier structure, wherein the electronic device has two stable overall magnetic configurations, and wherein a first unipolar current applied to the electronic device will cause the orientation of the magnetization controlling structure to reverse its orientation and a second unipolar current applied to the electronic device will cause the magnetization controllable structure to switch its magnetization in order to obtain one of the two stable overall magnetic configurations, wherein the second unipolar current has an amplitude that is less than the first unipolar current.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 26, 2011
    Assignee: Seagate Technology LLC
    Inventors: Dimitar V. Dimitrov, Olle Gunnar Heinonen, Yiran Chen, Haiwen Xi, Xiaohua Lou
  • Patent number: 7920416
    Abstract: Magnetic random access memory (MRAM) devices and techniques for use thereof are provided. In one aspect, a magnetic memory cell is provided. The magnetic memory cell comprises at least one fixed magnetic layer; at least one first free magnetic layer separated from the fixed magnetic layer by at least one barrier layer; at least one second free magnetic layer separated from the first free magnetic layer by at least one spacer layer; and at least one capping layer over a side of the second free magnetic layer opposite the spacer layer. One or more of the first free magnetic layer and the second free magnetic layer comprise at least one rare earth element, such that the at least one rare earth element makes up between about one percent and about 10 percent of one or more of the first free magnetic layer and the second free magnetic layer.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: April 5, 2011
    Assignee: International Business Machines Corporation
    Inventors: William J. Gallagher, Daniel C. Worledge
  • Patent number: 7916520
    Abstract: A memory cell is used which includes a plurality of magneto-resistive elements and a plurality of laminated ferrimagnetic structure substances. The plurality of the magneto-resistive elements are placed corresponding to respective positions where a plurality of first wirings extended in a first direction intersects with a plurality of second wirings extended in a second direction which is substantially perpendicular to the first direction. The plurality of the laminated ferrimagnetic structure substances corresponds to the plurality of the magneto-resistive elements, respectively, is placed to have a distance of a predetermined range from the respective plurality of the magneto-resistive elements, and has a laminated ferrimagnetic structure. The magneto-resistive element includes a free layer having a laminated ferrimagnetic structure, a fixed layer, and a nonmagnetic layer interposed between the free layer and the fixed layer.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 29, 2011
    Assignee: NEC Corporation
    Inventors: Tadahiko Sugibayashi, Takeshi Honda, Noboru Sakimura, Tetsuhiro Suzuki
  • Patent number: 7898849
    Abstract: A compound magnetic data storage cell, applicable to spin-torque random access memory (ST-RAM), is disclosed. A magnetic data storage cell includes a magnetic storage element and two terminals communicatively connected to the magnetic storage element. The magnetic storage element is configured to yield any of at least three distinct magnetoresistance output levels, corresponding to stable magnetic configurations, in response to spin-momentum transfer inputs via the terminals.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: March 1, 2011
    Assignee: Seagate Technology, LLC
    Inventors: Thomas William Clinton, Werner Scholz
  • Patent number: 7869265
    Abstract: A magnetic random access memory includes a first interconnection extending to a first direction, a second interconnection extending to a second direction perpendicular to the first direction, a magnetoresistive effect element formed between the first and second interconnections, having one terminal connected to the first interconnection, includes a fixed layer, a recording layer and a nonmagnetic layer, a film thickness of the fixed layer being larger than that of the recording layer, and a width of the fixed layer being larger than that of the recording layer, and configured to reverse a magnetization direction in the recording layer by supplying a first electric current between the fixed layer and the recording layer, and a diode having one terminal connected to the other terminal of the magnetoresistive effect element, and the other terminal connected to the second interconnection, and configured to supply the first electric current in only one direction.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: January 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuui Shimizu, Tatsuya Kishi
  • Patent number: 7859881
    Abstract: A magnetic memory device includes a first magnetic line which has a plurality of cells made of magnetic domains partitioned by domain walls, and in which information is recorded in each cell, a first write element formed at one end portion of the first magnetic line, and a first read element formed at the other end portion of the first magnetic line.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: December 28, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Katsuyuki Fujita, Yuui Shimizu
  • Patent number: 7852662
    Abstract: A spin-torque MRAM array has MRAM cells arranged in rows and columns. Bit lines are connected to each of the MRAM cells on each column. Source select lines are connected to each MRAM cell of a pair of rows and are oriented orthogonally to the bit lines. Write lines are connected to the gate of the gating MOS transistor of each MRAM cell of the rows. The MRAM cells are written in a two step process with selected MRAM cells written to a first logic level (0) in a first step and selected MRAM cells written to a second logic level (1) in a second step. A second embodiment of the spin-torque MRAM array has the bit lines commonly connected together to receive the data and the source select lines commonly connected together to receive an inverse of the data for writing.
    Type: Grant
    Filed: April 24, 2007
    Date of Patent: December 14, 2010
    Assignee: MagIC Technologies, Inc.
    Inventors: Hsu Kai Yang, Po-Kang Wang
  • Patent number: 7826174
    Abstract: An information recording apparatus comprises a plurality of fine particles forming an array on a plane in close proximity of each other, each of the plural particles including a ferromagnetic metal, a light-emitting device for exciting a near-field light, and a photo-electric conversion element for detecting a near-field light traveled along the fine particles.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: November 2, 2010
    Assignees: Ricoh Company, Ltd., Tohoku University
    Inventors: Migaku Takahashi, Masakiyo Tsunoda, Shin Saito, Tomoyuki Ogawa, Itaru Fujimura, Shigeyoshi Misawa, Toshiyuki Kawasaki
  • Patent number: 7791929
    Abstract: A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: September 7, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-yeong Cho, Yun-seung Shin
  • Patent number: 7787289
    Abstract: Embodiments of the present invention disclose an MRAM device having a plurality of magnetic memory cells grouped into words, and write conductors for carrying write currents to write to the memory cells, wherein at least some of the write conductors have a reduced cross-sectional area in the vicinity of a group of memory cells.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: August 31, 2010
    Assignee: Magsil Corporation
    Inventors: Krishnakumar Mani, Jannier Maximo Roiz Wilson, Anil Gupta, Kimihiro Satoh
  • Patent number: 7782663
    Abstract: A data storage device includes a magnetic layer having a plurality of magnetic domains, a write head provided at an end portion of the magnetic layer, a read head to read data written to the magnetic layer, and a current controller connected to the write head and the read head. A method of operating the data storage device includes reading data of an end portion of the magnetic layer using a read head provided at the end portion of the magnetic layer in which a write head is provided at the other end portion thereof, moving a magnetic domain wall of the magnetic layer by a distance corresponding to the length of one magnetic domain toward the end portion, and writing the read data to the other end portion of the magnetic layer using the write head and a current controller provided between the write head and the read head.
    Type: Grant
    Filed: April 2, 2007
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yong-su Kim
  • Patent number: 7764539
    Abstract: A spin-transfer MRAM is described that has two sub-cells each having a conductive spacer between an upper CPP cell and a lower MTJ cell. The two conductive spacers in each bit cell are linked by a transistor which is controlled by a write word line. The two CPP cells in each bit cell have different resistance states and the MTJ cell and CPP cell in each sub-cell have different resistance states. The MTJ free layer rotates in response to switching in the CPP free layer because of a large demagnetization field exerted by the CPP free layer. An improved circuit design is disclosed that enables a faster and more reliable read process since the reference is a second MTJ within the same bit cell. When RMTJ1>RMTJ2, the bit cell has a “0” state, and when RMTJ1<RMTJ2, the bit cell has a “1” state.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: July 27, 2010
    Assignee: MagIC Technologies, Inc.
    Inventors: Yimin Guo, Jeff Chien
  • Patent number: 7751235
    Abstract: A semiconductor memory device includes first to fourth resistance change elements sequentially arranged apart from each other in a first direction, a first electrode which connects one terminals of the first and second resistance change elements, a second electrode which connects one terminals of the third and fourth resistance change elements, a bit line which connects the other terminals of the second and third resistance change elements, first to fourth word lines respectively paired with the first to fourth resistance change elements, arranged apart from the first and second electrodes, and running in a second direction, a first current source which supplies a first electric current to a chain structure, when writing data in a selected element, and a second current source which supplies a second electric current to a selected word line which corresponds to the selected element, when writing the data in the selected element.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Yoshiaki Asao
  • Patent number: 7668005
    Abstract: A magnetic memory includes a plurality of magnetoresistive elements which include a fixed layer in which a magnetization direction is fixed, a free layer in which a magnetization direction changes, and a nonmagnetic layer formed between the fixed layer and the free layer, and a word line electrically connected to the magnetoresistive elements. Data erase is performed by setting the magnetization direction of the free layer in a first direction by a magnetic field induced by a current flowing through the word line, and data of the magnetoresistive elements are erased by one time data erase. Data write is performed by setting the magnetization direction of the free layer in a second direction by spin-transfer magnetization reversal by supplying a current in one direction to the magnetoresistive elements.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: February 23, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ueda
  • Patent number: 7626857
    Abstract: Provided is a current induced switching magnetoresistance device comprising a magnetic multilayer composed of a first ferromagnetic layer, a nonferromagnetic layer, and a second ferromagnetic layer, wherein the first ferromagnetic layer has an upper electrode, the second ferromagnetic layer pinned by an antiferromagnet, wherein the antiferromagnet contains a lower electrode at its lower part, and the second ferromagnetic layer is embedded with a nano oxide layer. It is preferable to have at least a part of the lower electrode in contact with the second ferromagnetic layer. The magnetoresistance device provides a lower critical current (Ic) for the magnetization reversal and has an increased resistance.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: December 1, 2009
    Assignee: Korea Institute of Science and Technology
    Inventors: Kyung-Ho Shin, Nguyen Thi Hoang Yen, Hyun-Jung Yi
  • Patent number: 7613035
    Abstract: A magnetic memory device includes a memory cell including magnetoresistance effect elements MTJ1, MTJ2 and a select transistor connected to the connection node of the magnetoresistance effect elements MTJ1, MTJ2, a first signal line extended in a first direction and connected to the magnetoresistance effect element MTJ1, a second signal line extended in the first direction and connected to the magnetoresistance effect element MTJ2, and a third signal line extended in a second direction and crossing the first signal line in a region where the magnetoresistance effect element MTJ1 is formed and crossing the second signal line in a region where the magnetoresistance effect element MTJ2 is formed. When memory information is written into the memory cell, the memory information to be memorized is switched by directions of write currents to be flowed to the first and the second signal lines.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: November 3, 2009
    Assignee: Fujitsu Limited
    Inventor: Masaki Aoki
  • Patent number: 7525862
    Abstract: A method for resetting a spin-transfer based random access memory system, the method comprising, inducing a first current through a first conductor, wherein the first current is operative to propagate a magnetic domain wall in a ferromagnetic film layer and the propagation of the magnetic domain wall is further operative to change the direction of a magnetic state of a first free layer magnet, and inducing a second current only through a second conductor, wherein the second current is operative to further propagate the magnetic domain wall in the ferromagnetic film layer and the propagation of the magnetic domain wall is further operative to change the direction of a magnetic state of a second free layer magnet.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: April 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Jonathan Z. Sun, Rudolf M. Tromp
  • Patent number: 7372757
    Abstract: A magnetic memory device includes a plurality of first metal lines arranged in parallel on a substrate and including a plurality of magnetic domains with variable magnetization directions. A plurality of second metal lines is arranged on the substrate perpendicular to the first metal lines. The plurality of second metal lines each has a tunnel through which the plurality of first metal lines pass. First input units are connected to the plurality of first metal lines and supply a current to drag or move the plurality of magnetic domains. Second input units are connected to the plurality of second metal lines to supply a current for switching the magnetization directions of magnetic domains inside the tunnels. Sensing units are connected to the plurality of second metal lines for sensing an electromotive force caused by magnetic domain walls passing through the tunnels.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: May 13, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Min Shin, Yong-Su Kim, Yoon-Dong Park
  • Patent number: 7209382
    Abstract: In a magnetic random access memory (MRAM), setting data which determines the supply/cutoff timing, magnitude, and temporal change (current waveform) of a write word/bit line current is registered in a setting circuit. A write current waveform control circuit generates a write word line drive signal, write word line sink signal, write bit line drive signal, and write bit line sink signal on the basis of the setting data. The current waveform of the write word/bit line current is controlled for each chip or memory cell array.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Kentaro Nakajima
  • Patent number: 7145796
    Abstract: A semiconductor integrated circuit device includes a magneto-resistive effect element and a plug. The magneto-resistive effect element includes a first magnetic layer whose magnetization direction is fixed and a second magnetic layer whose magnetization direction can be changed. The plug is formed to penetrate through the second magnetic layer in the film thickness direction of the second magnetic layer and used to apply a write magnetic field to the second magnetic layer.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: December 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Fukuzumi, Hiroaki Yoda
  • Patent number: 7068530
    Abstract: One block SB serving as a fundamental unit constituting a data reading circuit is constituted by four memory cells MS1 to MS4 connected electrically in series, four FETs S1 to S4 connected in parallel with the memory cells MS1 to MS4 in one-to-one correspondence, and an FET S0 connected to one of series connection ends of the memory cells MS1 to MS4. Each memory cell MS1-MS4 is formed out of a TMR element having two TMR element portions connected electrically in series. The two TMR element portions are connected in series to thereby form a series connection body. A sensing current flows in only through one end of the series connection body of the two TMR element portions, passes through the TMR element portions in turn, and then flows out only through the other end of the series connection body. Further, the TMR element 11 has two TMR element portions 11A and 11B. The TMR element portions 11A and 11B are disposed in a direction parallel with their laminated surfaces with respect to each other.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: June 27, 2006
    Assignee: TDK Corporation
    Inventor: Katsuhiko Hayashi
  • Patent number: 7054185
    Abstract: A word current source (445) for a magnetoresistive random access memory circuit (420) includes an n-channel transistor (430) including a gate, a source and a drain, where the source is coupled to a supply ground, and the drain is coupled to the magnetoresistive random access memory circuit. A positive supply voltage is coupled to the magnetoresistive random access memory circuit (420) so as to allow current to flow through the magnetoresistive random access memory circuit (420) when an activation signal is applied to the gate by the control circuit.
    Type: Grant
    Filed: November 30, 2003
    Date of Patent: May 30, 2006
    Assignee: Union Semiconductor Technology Corporation
    Inventor: Wayne Theel
  • Patent number: 6826321
    Abstract: Excitation of a triad artificial photosynthetic reaction center consisting of a porphyrin (P) convalently linked to a fullerene electron acceptor (C60) and a carotenoid secondary donor (C) leads to the formation of a long-lived C+-P-C60− charge-separated state via photoinduced electron transfer. This reaction occurs in a frozen organic glass down to at least 8 K. At 77 K, charge recombination of C*+-P-C60− occurs on the &mgr;s time scale, and yields solely the carotenoid triplet state. In the presence of a small (20 mT) static magnetic field, the lifetime of the charge-separated state is increased by 50%. This is ascribed to the effect of the magnetic field on interconversion of the singlet and triplet biradicals. At zero field, the initially formed singlet biradical state is in equilibrium with the three triplet biradical sublevels, and all four states have comparable populations. Decay to the carotenoid triplet only occurs from the three triplet sublevels.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 30, 2004
    Assignee: Arizona Board of Regents
    Inventors: John D. Gust, Jr., Ana L. Moore, Thomas A. Moore
  • Patent number: RE41693
    Abstract: Excitation of a triad artificial photosynthetic reaction center consisting of a porphyrin (P) convalently linked to a fullerene electron acceptor (C60) and a carotenoid secondary donor (C) leads to the formation of a long-lived C+-P-C60? charge-separated state via photoinduced electron transfer. This reaction occurs in a frozen organic glass down to at least 8 K. At 77 K, charge recombination of C*+-P-C60? occurs on the ?s time scale, and yields solely the carotenoid triplet state. In the presence of a small (20 mT) static magnetic field, the lifetime of the charge-separated state is increased by 50%. This is ascribed to the effect of the magnetic field on interconversion of the singlet and triplet biradicals. At zero field, the initially formed singlet biradical state is in equilibrium with the three triplet biradical sublevels, and all four states have comparable populations. Decay to the carotenoid triplet only occurs from the three triplet sublevels.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: September 14, 2010
    Assignee: Arizona Board of Regents, Acting for and on Behalf of, Arizona State University
    Inventors: John D. Gust, Jr., Ana L. Moore, Thomas Moore