Abstract: Exemplar embodiments are disclosed which allow errors in a magnetoresistive solid-state storage device, such as a magnetic random access memory (MRAM) device, to be minimized. An illustrative method includes the steps of identifying cells in the device which have a failure mode characterized by a propensity to remain in a particular orientation of magnetization, mapping the location of the identified cells, and compensating for the failure mode of a cell at a mapped location. Systems and computer readable media are also provided.

Abstract: A program unit includes two program cells having an electric resistance varying according to a magnetization direction thereof. These program cells are magnetized in the same direction in initial state, that is, non-program state. In program state, the magnetization direction of one of the program cells selected according to program data is changed from the initial state. One-bit program data and information of whether the program unit stores program data or not can be read based on two program signals generated according to the electric resistances of the two program cells.

Abstract: A magnetic random access memory (MRAM) having a vertical structure transistor has the characteristics of faster access time than SRAM, high density as with DRAM, and non-volatility like a flash memory device. The MRAM has a vertical structure transistor, a first word line including the transistor, a contact line connected to the transistor, a magnetic tunnel junction (MTJ) cell deposited on the contact line, a bit line deposited on the MTJ cell, and a second word line deposited on the bit line at the position of MTJ cell. With the disclosed structure, it is possible to improve the integration density of a semiconductor device, to increase the short channel effect, and to improve the control rate of the resistance, while using a simplified manufacturing process.

Abstract: A magnetic memory includes a memory cell and a conductor wherein the memory cell is crossed by the conductor. A write pulse generator is coupled to the conductor and is configured to provide a discharge current to the conductor during a write operation of the memory cell.