Abstract: A storage apparatus includes a plurality of first wiring layers extending in one direction, a plurality of second wiring layers extending in another direction, and a plurality of memory cells provided in respective opposing regions in which the plurality of first wiring layers and the plurality of second wiring layers are opposed to each other. The plurality of memory cells each includes a selector element layer, a storage element layer, and an intermediate electrode layer provided between the selector element layer and the storage element layer. One or more of the selector element layer, the storage element layer, and the intermediate electrode layer is a common layer that is common between the plurality of memory cells, in which the plurality of memory cells is adjacent to each other and extends in the one direction or the other direction. The intermediate electrode layer includes a nonlinear resistive material.

Abstract: A method of programming a non-volatile memory device includes providing a resistive switching device, the resistive switching device being in a first state and characterized by at least a first resistance, applying a first voltage to the resistive switching device in the first state to cause the resistive switching device to change to a second state wherein the second state is characterized by at least a second resistance, wherein the second resistance is greater than the first resistance, and applying a second voltage to the resistive switching device in the second state to cause the resistive switching device to change to a third state, wherein the third state is characterized by at least a third resistance, wherein the second voltage has a magnitude higher than a magnitude of the second voltage, and wherein the third resistance is greater than the second resistance.

Abstract: A re-writable memory that uses resistive memory cell elements with non-linear IV characteristics is disclosed. Non-linearity is important in certain memory arrays to prevent unselected cells from being disturbed and to reduce the required current. Non-linearity refers to the ability of the element to block the majority of current up to a certain level, but then, once that level is reached, the element allows the majority of the current over and above that level to flow.

Abstract: A ferromagnetic pinned layer (1) kept at a fixed magnetic orientation by a pinning layer (4) is separated from a ferromagnetic free layer (3) by a Mott insulator coupling layer (2). A controllable voltage source (5) is connected between the pinned layer (1) and the free layer (3). A sublayer of the coupling layer (2) whose width (d) increases with the voltage is converted to an electrically conducting and magnetically coupling metallic state. The magnetic exchange field acting on the free layer (3) which is controlled by the applied voltage via the width (d) of the electrically conducting sublayer of the coupling layer (2) can be used to switch the free layer (3) between states of parallel and antiparallel orientations with respect to the magnetic orientation of the pinned layer (1). This is used in memory cells and in a write head.

Abstract: A method and apparatus for hot-plugging circuit boards having lower voltage logic devices into a higher voltage backplane in a manner that minimizes overvoltage stress during system power-up, or during a lower voltage power failure. The method and apparatus ensures that the lower voltage device(s') power input reaches at least a nominal input level before any other inputs of the device are driven to a level greater than or equal to an expected input level. Dedicated output pins on lower voltage logic device(s) are configured to issue a control output signal for enabling higher voltage devices. Output enable terminals for the higher voltage parts, which are connected to respective control outputs from a lower voltage device, are normally in a disabled state as a function of pull-up or pull-down circuitry.

Abstract: Switching distortion in a digitally controlled attenuator is effectively suppressed and soft-switching in passgate arrays, present at a certain point of a logic signal path, is implemented with a minimum number of additional components. The soft switching in passgate arrays is implemented by driving the control nodes of each passgate by an inverter, at least a current terminal of which is made switchable from the respective supply node to a node onto which an appropriate ramp signal toward the potential of the respective supply potential is produced by a suitable controlled ramp generator. The passgates for switching the current terminals of the inverters are controlled by the logic signal that preexisted the intervening switching on the respective signal line of the passgate, and by its inverse. The preexistent logic value is momentarily stored in a latch that is updated at the end of any new switching process.

Abstract: A magnetic bubble device has minor loops formed through ion implantation and used for storing information. As the density becomes higher, inside turn corner portions are formed on the minor loops. Dummy patterns having circular, triangular or other shapes are disposed in the vicinity of the corner portion. It is desirable that the minimum distance X between the dummy pattern and the propagation track satisfy the relation of 1.5 D.ltoreq.X.ltoreq.3.5 D, where D represents the diameter of a bubble.

Abstract: A magnetic bubble Y-bar corner for use at the end of a minor loop. The Y-bar corner includes a Y-bar corner element and a canted I-bar positioned between the Y-bar corner element and each of the two adjacent storage elements in the minor loop. The ends of the arm of the Y-bar corner element are positioned adjacent the apex portions of the canted I-bars. The distance between the ends of the arms of the Y-bar is larger than the distance between the opposing ends of the two canted I-bars. With this corner a bubble propagates in either direction along a path from a minor loop storage element to the end of the canted I-bar and then to the apex portion of the canted I-bar and from there across to the end of the arm of the Y-bar.

Abstract: A magnetic bubble storage device is formed with a major-minor loop organization wherein the bit pitch in at least a part of a first region of the major loop other than a second region where the major loop and the minor loops are connected is larger than the bit pitch in the second region. This permits the realization of a pattern arrangement with a broader operating margin and also facilitates the addition of redundant minor loops.

Abstract: A magnetic bubble memory structure having an enhanced storage density is made possible by reducing the circuit period, that is the distance between bubbles, in the storage section of the device. This reduction of the circuit period is made possible by using a gap tolerant propagation element, e.g. asymmetrical chevrons. The bubble storage sections are structured such that the areas closest to the transfer gates have a larger circuit period than the remainder of the storage section. The bubble chip architecture utilizing this means of enhancing the storage density may be of the major-minor loop configuration or the block-replicate configuration. Bubble storage sections in the form of loop structures may have a folded loop or an h loop configuration as well as a closed loop configuration. The reduction in circuit period accomplishes enhancement of the storage density without reducing the bubble diameter and other minimum circuit features to achieve this goal.

Abstract: Composite mutually exclusive field-accessed circuit elements common to a plurality of bubble paths. A channel composed of mutually exclusive circuit elements is linked to an adjacent parallel channel of mutually exclusive circuit elements by means of circuit element portions common to both channels. The interconnected channels are operated mutually exclusively by means of corresponding pulsed field sequences. Transfer between the linked channels is via the common circuit element portion. Several new types of propagation circuits are also discussed along with organizations for mutually exclusive major and minor closed loops featuring controlled transfer via common circuit element portions.