Abstract: A decoder may perform node data reordering for bit node processing and node data reordering for bit node to check node interconnections. The decoder may also utilize a single barrel shifting operation on data read from an edge memory for bit node processing or check node processing during a memory read operation. The decoder may also utilize a single format conversion on data read from an edge memory for bit node processing or check node processing. The decoder may also utilize a simplified check node process for check node processing.

Abstract: An optical waveguide for a touch panel which obviates a need for positioning a light receiving optical waveguide portion. The touch panel optical waveguide A1 which is to be fitted around a periphery of a display screen of a display of a touch panel, the optical waveguide comprising light emitting cores 3 each having an end face provided on one of opposed portions disposed in opposed relation on opposite sides of the display screen of the display, and light receiving cores 3 each having an end face provided on the other of the opposed portions, wherein the cores 3 are provided on a surface of a planar frame-shaped under-cladding layer (frame) 2 having a shape conformable to the periphery of the display screen of the display.

Abstract: A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst counter starting from an externally applied starting address. The count direction of the counter is controlled by a counter control circuit that receives the LSB the next to least significant bit (“NLSB”) of the starting column address, as well as a signal indicative of the operating mode of the DRAM. In a serial operating mode, the counter control circuit causes the burst counter to increment when the LSB of the starting column address is “0” and to decrement when the LSB of the starting column address is “1”. In an interleave operating mode, the counter control circuit causes the burst counter to increment when the NLSB of the starting column address is “0” and to decrement when the NLSB of the starting column address is “1”.

Abstract: In one illustrative embodiment, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate.

Abstract: Control circuitry for applying voltages to a memory circuit. In accordance with this invention, row circuitry applies either a high voltage or a low voltage to a memory cell based on the operation to be performed and column circuitry applies a high or a low voltage to the memory cell based on the operation to be performed.

Abstract: In the disclosed distance measuring arrangement, a light projector turns on and off to illuminate an object over the ambient light during projection periods when light is projected and during space periods when light is not projected. The reflected light is detected as a function of distance by integrating projection signals representing light reflected during projection periods, integrating space signals representing light during reflected space periods, subtracting the integration space signals from the projection signals, and extracting measurements based on the subtractions. Compensation for change in ambient light between periods is obtained by changing the timing of the integrations and extractions from concidence with the projections and space periods.

Abstract: An on-chip magnetic bubble decoder comprising a plurality of sequentially operated gates oriented to be responsive to different phases of the rotating in-plane magnetic field and connected to a conductor which is pulsed at the selected phase of the cycle to transfer bubbles from one track onto different tracks to be propagated therefrom. In its simplest form, one gate oriented to be operated during the phase 2 time of the cycle and a second gate oriented to be responsive to the phase 1 time of the cycle, all operable by a single conductor, thus form a four output decoder with two gates and a single conductor. A second conductor controls a third gate which modulates the bubble stream to control the data being decoded.Further embodiments of the invention include 8 output decoder (2 data bits decoded into 1 of 4 paths) with only two conductors for activating the gates and a 1 of 16 output decoder with 2 conductors for decoding and a third for data control.

Abstract: There is shown and described a magnetic bubble domain decoder organization which is especially adaptable to a single port configuration. A plurality of separate storage loops are utilized to store data in the form of magnetic bubble domains. An input/output section is provided for supplying data to the storage loops. A crossover junction circuit permits information to be propagated along a single input/output loop into and out of the storage loops. Input and output decoder circuits are provided in each storage loop to control the data which is stored therein. Control circuits such as tranfer switches, universal switches, retarding networks and the like are arranged to control the movement of magnetic bubble domains in the storage loops. By operation of the various control circuits, interwoven data in the storage loops can be selectively separated and retrieved at the input/output section.

Abstract: A random access bubble memory directs a plurality of continuous streams of bubbles toward a plurality of storage loops. A write decoder selects one continuous stream of bubbles. An annihilator then transforms this one continuous stream of bubbles into the desired data pattern which is then stored in a selected loop. While the data pattern is being formed, a read decoder directs the data which had been stored in the selected loop to a bubble detector. This memory has a unified read/write cycle which permits intermixed read and write, read/modify/write, and swap operations. This bubble memory allows a user to remove power abruptly during a read/write cycle without returning a partially processed block to its storage loop and without saving the identity of the block. In a preferred embodiment, the read and write decoders are operated simultaneously by identical control currents.

Abstract: A display system for providing a real-time, dynamic presentation of an analog signal waveform is disclosed. The system includes an A-D converter that, in turn, drives a serial string of binary weighted bubble domain generators. The bubble domain generators generate moving columns of bubble domains, the total amplitude of light that is provided by each column representing the amplitude of the analog signal waveform at each of an associated sample time. The bubble domain memory plane is of a construction to permit the columns of moving bubbles to appear as moving columns of bright spots when seen by an observer using a plane polarized light beam and an analyzer.

Abstract: An associative bubble memory apparatus utilizing a plurality of registers therein to provide a high total memory capacity and to provide data retrieval or correlation based upon content rather than the address of the data of interest.

Abstract: The disclosed chip design is directed to a multiplexed decoder chip with M.gtoreq.2. With this arrangement magnetic bubble domains are propagating at one data bit every M cycles (for M = 2 this is every other cycle). Therefore, a unique decoder network using an existing retarding switch can be realized to offer a lower power, highly efficient multiplexed decoder chip with complete selective read-write capability.

Abstract: In a Teletext transmission system, data is transmitted in digital form during lines in the field blanking period of a composite video signal of a television transmission. On reception, the information is decoded and utilized to provide a display comprising a page having a predetermined number of rows of information in alphanumeric or graphics form. The data is received in blocks comprising information digits and each block has an associated group of address digits so that each block can be directed to an appropriate storage location in a first store, regardless of the order in which the data blocks are transmitted. The contents of the first store can then be transferred in address order into a larger capacity serial store ready for use in generating the display. Thus it is possible for a number of pages of information data to be correctly assembled in serial row order, ready for display generation, in a manner accommodating non-transmitted blank rows.

Abstract: An on-chip bubble domain circuit organization utilizing a multi-chip concept is provided. One or more storage registers are separately connected to each of a plurality of propagation channels whereby data in the form of magnetic bubble domains (bubbles) may be transferred into and out of the storage registers. Each of the propagation channels includes a generator for producing the initial bubbles which are supplied to a multiple output replicator via an input propagation path. The initial bubbles are replicated into any desired number of new bubbles by a multiple output replicator. The input propagation paths for the several channels have different lengths of propagation times between the generator and the replicator. Input decoders are utilized to determine to which storage register the bubbles from the replicators will be directed along the propagation channel. Those bubbles not selected are, typically, annihilated.

Abstract: A block oriented random access memory (BORAM) magnetic bubble domain system which provides increased throughput of information and reduced access or read time for the same information as compared to existing major-minor or decoder accessed chip organizations which it is designed to replace.