Abstract: In certain aspects, a circuit for multi-mode calibration can include a resistor input. The circuit can also include a first comparator connected to the resistor input and to a first plurality of voltage sources. The circuit can also include a first pull-up driver. The circuit can further include a logic pull-up code generator to calibrate the first pull-up driver. The circuit can additionally include a replica of the first pull-up driver. The circuit can also include a first pull-down driver and a second comparator connected to the replica, the first pull-down driver, and a second plurality of voltage sources. The second comparator can compare a voltage of a middle point between the first pull-down driver and the second pull-up driver to one of the second plurality of voltage sources. The circuit can further include a logic pull-down code generator.

Abstract: Such a device is disclosed that includes a first chip outputting a bank address signal and an active signal, and a plurality of second chips stacked on the first chip. Each of the second chips includes a plurality of memory banks each selected based on the bank address signal. Selected one or ones of the memory banks is brought into an active state in response to the active signal. Each of the second chips activates a local bank active signal when at least one of the memory banks included therein is in the active state. The first chip activates a bank active signal when at least one of the local bank active signals is activated.

Abstract: An LED chip package structure includes a conductive unit, a first package unit, an ESD unit, a second package unit, a light-emitting unit and a second package unit. The conductive unit has two conductive pins adjacent to each other which form a concave space between each other. The first package unit encloses one part of each conductive pin in order to form a receiving space communicating with the concave space and to expose an end side of each conductive pin. The ESD unit is received in the concave space and electrically connected between the two conductive pins. The second package unit is received in the concave space in order to cover the ESD unit. The light-emitting unit is received in the receiving space and electrically connected between the two conductive pins. The third package unit is received in the receiving space in order to cover the light-emitting unit.

Abstract: A method and system for providing a magnetic element are disclosed. The method and system include providing a pinned layer, providing a spacer layer, and providing a free layer. The free layer is ferrimagnetic and includes at least one of a conductive ferrite, a garnet, a ferrimagnetic alloy excluding a rare earth, a heavy rare-earth-transition metal alloy, a half-metallic ferrimagnetic, and a bilayer. The bilayer includes a rare earth-transition metal alloy layer and a spin current enhancement layer. The magnetic element is configured to allow the free layer to be switched due to spin transfer when a write current is passed through the magnetic element.

Abstract: A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a word line such that when activated, the respective data node and data line are coupled. The CAM cell further includes a match circuit coupled to one of the complementary data nodes of the latch. The match circuit discharges a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching. Two of the CAM cells can be used to implement a full ternary CAM cell.

Abstract: A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a word line such that when activated, the respective data node and data line are coupled. The CAM cell further includes a match circuit coupled to one of the complementary data nodes of the latch. The match circuit discharges a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching. Two of the CAM cells can be used to implement a full ternary CAM cell.

Abstract: An MRAM cell and a method of forming the an MRAM cell minimizes the occurrence of electrical shorts along the side walls of the stacked cell structure during fabrication. Specifically, a first conductor is provided in a trench in an insulating layer, and then an upper surface of the insulating layer and the first conductor are planarized. Next, as the layers forming the stacks of the MRAM cells are deposited on the planarized insulating layer and first conductor, the critical layers are physically separated from adjacent layers at regions surrounding an interior region of the stacked layers. The stacked layers at the interior region form an MRAM cell, while the separated edges prevent conductive layers from being formed along the sidewalls of the MRAM cell due to sputtering during the etching process(es) performed to define the cell.

Abstract: A single event upset (SEU) resistant semiconductor circuit element and a method of making are provided by the invention. The single event upset resistant semiconductor circuit element includes a plurality of parallel-connected semiconductor cell elements. Each semiconductor cell element of the plurality of parallel-connected semiconductor cell elements is physically separated from the other cell elements. Moreover, the semiconductor cell elements may be physically separated by at least one intervening semiconductor cell element of another circuit element.

Abstract: A data storage device includes a group of memory cells. Write-once operations may be performed by damaging the thin-film barriers of at least some of the memory cells. The data storage device may be a Magnetic Random Access Memory (“MRAM”) device.

Abstract: A magnetic tape pancake package includes a plurality of pancakes respectively comprising a hub having a width slightly larger than the width of a magnetic tape, and the magnetic tape wound around the hub. A plurality of spacers are stacked together with the pancakes between the stacked pancakes and at the top and the bottom of the stack of the pancakes. Each spacer is formed into a disk-like shape having a diameter larger than the diameters of the pancakes and provided with a recess at a section contacting the hub for engagement with a hub end face section protruding from the magnetic tape wound around the hub. The pancakes and the spacers are wrapped in a lump with an expansible and/or contractible film.

Abstract: A protection circuit for inner elements such as metal insulator semiconductor (MIS) field effect transistors in a semiconductor device of high packing density has been improved. The protection circuit comprises protective elements of two types. One type has a deep diffusion region providing the element with high surge capacity, that is an ability to withstand the energy of an incoming surge, and the other type has a shallow diffusion region providing a low breakdown voltage. With a combination of these two types of protective element, the protection circuit can withstand high energy of an input surge and, at the same time, provide a low protection voltage suitable to protect the inner elements from breakdown.

Abstract: A magnetic shielding device, adapted to protect a magnetic recording member against external magnetic fields, includes a plurality of spaced apart sheets of ferromagnetic material and the total thickness of the spacings between adjacent sheets of ferromagnetic material is selected to be larger than 0.5 mm. In a modification, the spaced sheets are covered with covers and the peripheral portions thereof are welded together. In another modification a sheet of insulating material having a surface area larger than those of the sheets of ferromagnetic material is interposed therebetween.