Abstract: Embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data writing method thereof. The storage system is configured to: enter a write data copy mode in response to a write-copy enable signal; if at least two groups of data in multiple groups of data exported from multiple data ports are a same in the write data copy mode, define the at least two groups of data as a category; generate an identification signal that is used to indicate a data copy; transmit one group of data in the category to an interface of a memory array; and disconnect a transmission path between a data port corresponding to another group of data in the category and another interface of the memory array, wherein the memory array, in response to the write-copy enable signal and the identification signal.

Abstract: The embodiments of the present disclosure relate to the technical field of semiconductors and provide a storage system and a data reading method thereof. The storage system is configured to: enter a read data copy mode in response to a read-copy enable signal; if at least two groups of data in multiple groups of data exported from a memory array are a same in the read data copy mode, define the at least two groups of data as a category; export an identification signal that is used to indicate a data copy; transmit one group of data in the category to a corresponding data port; and disconnect a transmission path that is used to transmit another group of data in the category to a corresponding data port.

Abstract: A storage circuit (11) includes memory cells (MCij), each of which includes an MTJ element, and reference cells (RCi), each of which includes a series circuit of an MTJ element set to a low-resistance state and a linear resistor (FR). A RW circuit (23j) that includes a sense amplifier is provided in each column of a memory cell array (21), and compares a data voltage on a corresponding bit line (BLj) with a reference voltage. The sense amplifier includes a pair of PMOS transistors to which the data voltage and the reference voltage are applied, a CMOS sense latch that is connected to a current path of the PMOS transistors.

Abstract: Various implementations described herein are related to a device with a backside power network. The backside power network may have a buried power rail that is coupled to ground. The device may have a read-only memory (ROM) cell that is coupled between at least one bitline and the buried power rail, and the ROM cell may be coupled to ground by way of the buried power rail.

Abstract: Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

Abstract: The present invention discloses an electronic device including a carrier module, a first storage module and a second storage module. The carrier module includes a first slot and a second slot. The first slot has a first shape feature, and the second slot has a second shape feature, wherein the first shape feature is different from the second shape feature. The first storage module is detachably disposed in the first slot, and has a third shape feature corresponding to the first shape feature. The second storage module is detachably disposed in the second slot, and has a fourth shape feature corresponding to the second shape feature. The third shape feature is different from the fourth shape feature.

Abstract: An X16 nonvolatile memory has 16 input/output (I/O) ports, identified as I/O ports [15:0], and adopts a conversion method, which allows the memory to operate in an X16 mode or in an X8 mode. The method includes receiving a first user command that is sent by an upper computer and belongs to a user mode; determining a disabling command for a module path of the high-bit I/O ports [15:8] according to the first user command; and executing the disabling command and disabling the module path for controlling the high-bit I/O ports [15:8] of the memory so as to operate in an X8 mode.

Abstract: A smart credential is programmed to show personal information regarding a user on a display when such information is desired or required, and to conceal some or all of the personal information of the user at other times. The information displayed by the credential may pertain to a location of the credential, a level of authorization of the user, or a task or function to be performed by the user. When the credential executes a handshake with a beacon at a secure facility, relevant information regarding the location, the level of authorization, the task or the function is displayed on the credential, and irrelevant information is not displayed. Additionally, a signature of motion by a bearer of a credential may be compared to a signature of motion of an authorized user of the credential in order to determine whether the bearer of the credential is the authorized user.

Abstract: Disclosed in an embodiment of the present invention are a hardware-based flash FTL function realization method and data storage device thereof, wherein the method comprises: when the data storage device is powered on, a state machine identifies the flash chip to acquire the chip information of the flash chip; the state machine establishes a target table according to the chip information; and the state machine realizes the FTL function of the flash controller according to the target table, wherein the FTL function comprises an address mapping function, a bad block management function and a garbage collection function.

Abstract: A method includes retrieving a registered response obtained in a registration process, the registered response being a physically unclonable function (PUF)-based response associated with a device; retrieving a registered helper data obtained in the registration process, the registered helper data corresponding to the registered response; generating a cipher text by encrypting a message with the registered response; and sending to the device over a public channel the cipher text with the registered helper data.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

Abstract: A method comprising: recording test code defined in a high-level test specification language; and automated analysis of the test code defined in the high-level test specification language before a conversion of the high-level test specification language to a low-level test implementation language configured to enable testing of a target by a test module.

Abstract: An apparatus comprises field-effect transistor (FET) structures stacked horizontally and vertically in a three-dimensional memory array architecture, gates extending vertically and spaced horizontally between the plurality of FET structures, and a ferroelectric material separating the FET structures and the gates. Individual ferroelectric FETs (FeFETs) are formed at intersections of the FET structures, the gates, and the ferroelectric material. Another apparatus comprises a plurality of bit lines and word lines. Each bit line has at least two sides that are coupled with a ferroelectric material such that each bit line is shared by neighboring gates to form a plurality of FeFETs. A method of operating a memory array comprises applying a combination of voltages to a plurality of word lines and digit lines for a desired operation for a plurality of FeFET memory cells, at least one digit line having the plurality of FeFET memory cells accessible by neighboring gates.

Abstract: Systems and methods for content management server systems configured to manage and publish managed content in accordance with embodiments of the invention are disclosed. In one embodiment, a versioned content management server system, includes a processor, a versioned content management application, managed content, wherein managed content includes content and content version metadata, wherein the versioned content management application configures the processor to receive updated content, locate managed content based on the received updated content, determine version data based on a portion of the located managed content, the received updated content, update the content version metadata data, associate the updated version content data with the managed content, receive a request for content, identify a portion of the managed content that corresponds to the requested content, retrieve the identified portion of the managed content, and transmit the retrieved portion of the managed content.

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

Abstract: A receiver includes a first interface to receive content, a second interface to be coupled to a device, and a processor to determine whether the device is a compliant device and to prevent decryption of at least a portion of the content received through the first interface when the device is determined to be a non-compliant device.

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A portion of charge of a memory cell may be captured and, for example, stored using a capacitor or intrinsic capacitance of the memory array that includes the memory cell. The memory cell may be recharged (e.g., re-written). The memory cell may then be read, and a voltage of the memory cell may be compared to a voltage resulting from the captured charge. A logic state of the memory cell may be determined based at least in part on the voltage comparison.

Abstract: The invention relates to a method for a first communication device to perform authenticated distance measurement between the first communication device and a second communication device, wherein the first and the second communication device share a common secret and the common secret is used for performing the distance measurement between the first and the second communication device. The invention also relates to a method of determining whether data stored on a first communication device are to be accessed by a second communication device. Moreover, the invention relates to a communication device for performing authenticated distance measurement to a second communication device. The invention also relates to an apparatus for playing back multimedia content comprising a communication device.

Abstract: A determining method for determining whether or not the tension of an adhesive tape constituting a frame unit is proper, in which a plate-shaped workpiece and an annular frame are attached to the adhesive tape to form the frame unit, is provided. The adhesive tape is composed of a base layer and an adhesive layer formed on the base layer. The determining method includes a supporting step, a downward amount measuring step, and a determining step.

Abstract: Techniques described herein generally include methods and systems related to the use of processors that include graphene-containing computing elements while minimizing or otherwise reducing the effects of high leakage energy associated with graphene computing elements. Furthermore, embodiments of the present disclosure provide systems and methods for scheduling instructions for processing by a chip multiprocessor that includes graphene-containing computing elements arranged in multiple processor groups.

Abstract: Systems and method to provide secure storage are disclosed. An example method includes establishing a secure tunnel between a storage device and an agent, provide a command from the agent to the storage device via the secure tunnel, access first data at the storage device in response to the command, and identify a modification to data stored on the storage device by comparing the first data to second data, wherein the comparison is done using the storage device.

Abstract: An improved way of communicating data operation commands within a non-volatile storage controller is presented. The non-volatile storage controller includes an internal processing unit that is communicatively coupled with an associated host system, a master controller, and a plurality of local controllers that are communicatively coupled with a non-volatile memory. Upon receiving a series of data operations commands from the host system, the internal processing unit is configured to apply address shadowing when communicating the series of commands to the master controller such that the internal processing unit does not need to repetitively send the same set memory addresses to the master controller when issuing the series of commands.

Abstract: Systems and methods are disclosed for managing and protecting electronic content and applications. Applications, content, and/or users can be given credentials by one or more credentialing authorities upon satisfaction of a set of requirements. Rights management software/hardware is used to attach and detect these credentials, and to enforce rules that indicate how content and applications may be used if certain credentials are present or absent. In one embodiment an application may condition access to a piece of electronic content upon the content's possession of a credential from a first entity, while the content may condition access upon the application's possession of a credential from a second entity and/or the user's possession of a credential from a third entity. Use of credentials in this manner enables a wide variety of relatively complex and flexible control arrangements to be put in place and enforced with relatively simple rights management technology.

Abstract: The disclosure relates to a tamper protection device for protecting a field device against tampering. The tamper protection device includes a carrier and at least one electronic memory, wherein the at least one electronic memory is disposed in at least one partial area on the carrier, and the at least one electronic memory stores at least one predefinable security information item. The at least one electronic memory is configured to modify the predefinable security information item in the event of at least partial damage to the tamper protection device. The disclosure further relates to a method for producing a field device having a tamper protection device, to a field device comprising a tamper protection device, to a tamper protection system, and to the use of a tamper protection device.

Abstract: Content on a device is encrypted and protected based on a data protection key corresponding to a particular identity of the user of the device. The protected content can then be stored to cloud storage, and from the cloud storage the protected content can be transferred to various other ones of the user's devices. A data protection key that is used to retrieve the plaintext content from the protected content is maintained by the user's device. This data protection key can be securely transferred to other of the user's devices, allowing any of the user's devices to access the protected content.

Abstract: A memory module includes a first printed circuit board (PCB) which includes a first surface, a second surface, first taps formed on the first surface, and second taps formed on the second surface, a first buffer attached to the first PCB, and first memory devices attached to the first PCB, in which the first buffer is configured to transmit signals input through the first taps and the second taps to the first memory devices, and signals re-driven by the first buffer among the signals are transmitted to a second module through the second taps.

Abstract: An apparatus, a method, and a system are presented in which the apparatus may include a security circuit, a processor, and an interface controller. The security circuit may be configured to generate a keyword. The processor may be configured to determine one or more policies to be applied to usage of the keyword, and to generate a policy value. The policy value may include one or more data bits indicative of the determined one or more policies. The interface controller may be configured to generate a message including the keyword and the policy value. The interface controller may also be configured to send the message.

Abstract: In one embodiment, a memory system is provided comprising at least one memory die, a sensor configured to sense an average amount of power consumed by the memory system over a time period, and a controller. The controller is configured to maintain a token bucket that indicates an amount of power currently available for memory operations in the at least one memory die and is further configured to reduce a number of tokens in the token bucket by an amount of power consumed over the time period as indicated by the average amount of power sensed by the sensor over the time period.

Abstract: A multi-media device interface (18) couples a multi-media device (16) to a portable electronic device (10). Multi-media and other information can be loaded into the portable electronic device (10) from the multi-media device (16) or stored in the multi-media device (16) from the portable electronic device (10). The multi-media device interface (18) queues commands to the multi-media device (16) from the portable electronic device (10) while the multi-media device (16) completes a previously-issued command.

Abstract: A multi-media device interface (18) couples a multi-media device (16) to a portable electronic device (10). Multi-media and other information can be loaded into the portable electronic device (10) from the multi-media device (16) or stored in the multi-media device (16) from the portable electronic device (10). The multi-media device interface (18) queues commands to the multi-media device (16) from the portable electronic device (10) while the multi-media device (16) completes a previously-issued command.

Abstract: A regulator circuit that makes it possible to supply a voltage which enables a load circuit to operate normally, even if an external power supply voltage is momentarily interrupted or dropped, includes a ZD/R parallel circuit (a backflow prevention diode and in parallel with a resistor) that is connected between an external power supply voltage terminal and the drain of a MOSFET.

Abstract: A system includes memory chips mounted on a memory module each having an alert terminal that notifies that the memory chip has detected a predetermined error. The memory module has a first transmission line connected to alert terminals of memory chips, output terminal being connected to one end of the first transmission line, and a first termination resistor having an end connected to another end of the first transmission line. The system further includes a second transmission line having an end connected to the alert terminal and another end connected to a controller and a third transmission line having an end connected to a first input terminal on the memory module and a second end line and a second end having a voltage different from a voltage of another end of the first termination resistor.

Abstract: A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.

Abstract: An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

Abstract: A method for making an electrical circuit comprises the steps of: forming a rigid printed circuit board having a plurality of electrical contacts on at least one surface; forming a multilayer flexible circuit board having a plurality of electrical components on at least one surface, and further having a bifurcated area along one edge; forming electrode pads on the inner surfaces of the bifurcated area of the flexible circuit board that are alignable respectively with the electrical contacts on the rigid circuit board when the bifurcated area is spread apart by about 180°; spreading the bifurcated area apart and aligning the electrode pads respectively with the electrical contacts; and forming an electrical connection between the electrode pads and the electrical contacts.

Abstract: A processing system includes a processor core, a peripheral component, and a flip-flop unit in at least one of the processor core and the peripheral component. The flip-flop unit can include a master latch, and two slave latches coupled to an output of the master latch. The first slave latch is formed over a first doped well region of a semiconductor substrate. The second slave latch is formed over a second doped well region of the semiconductor substrate. A comparator is coupled to an output of the first slave latch and to an output of the second slave latch. An output of the comparator indicates whether a state stored in the first slave latch is the same as a state stored in the second slave latch.

Abstract: A memory channel can be divided into two or more memory sub-channels, wherein each one of the memory sub-channels includes two or more memory components configured to store data made accessible on that memory sub-channel, and wherein the two or more memory components in each one of the memory sub-channels are respectively connected via at least one transmission line and can be individually accessed (addressed) on their associated sub-channel.

Abstract: Disclosed herein are integrated circuit devices having stacked power supplies and methods of making such integrated circuit devices. In one example, the device includes a first power supply structure, a second power supply structure electrically isolated from the first power supply structure, wherein at least a portion of the second power supply structure is positioned vertically below at least a portion of the first power supply structure, wherein the first power supply structure is one of an interruptible or an uninterruptible power supply structure, while the second power supply structure is the other of the interruptible or the uninterruptible power supply structure, a plurality of constant-power circuits conductively coupled to whichever of the first or second power supply structure that is the uninterruptible power supply and a plurality of interruptible-power circuits conductively coupled to whichever of the first or second power supply structure that is the interruptible power supply.

Abstract: Disclosed is a rotary USB interface device, which includes: a USB module (110), a PCB, a rotary shaft (130) connecting the USB module and the PCB, a conductive layer (140) connected with the rotary shaft, and an insulation layer (150) provided between a grounding layer (160) on the PCB and the conductive layer. The USB module contains a first ground wire, which forms a first grounding path of the USB module, together with the rotary shaft and the conductive layer. The grounding layer on the PCB forms a second grounding path. The first grounding path is separated from the second grounding path by virtue of the insulation layer, i.e. the grounding path of the PCB is separated from the grounding path of the USB module. Thus, an open circuit voltage is formed, the voltage difference is maintained stable, the overall device obtains a stable grounding signal, the grounding performance is enhanced and the transmitting/receiving performance of the device is improved.

Abstract: A memory device structure and method of fabricating the memory device structure is described. The memory device structure has a memory array disposed in a array level and peripheral circuitry, including decoders and other peripheral circuitry, disposed in a device level. The array of memory cells has a perimeter that defines a cylinder that extends above and beneath the array of memory cells. The decoders and the other peripheral circuitry or at least part of the decoders and the other peripheral circuitry are disposed within the cylinder in the device level. The memory device structure also includes a plurality of pads in a pad level. A first plurality of inter-level conductive lines electrically couples the decoders to the bit lines and word lines in the array of memory cells.

Abstract: A device is provided for protecting an electronic printed circuit board. The device includes at least one zone of conductive contact between the printed circuit board and an element for securing the printed circuit board. The device also includes at least one elevating pad for elevating the at least one zone of conductive contact. The element for securing comes into contact with the zone of conductive contact of the printed circuit board by means of a zone of conductive contact of the elevating pad.

Abstract: According to some embodiments, an electronic circuit comprises a digital output which is held to a logic one after the power supply was removed, for a time duration in a narrow range. The electronic circuit comprises a first array of elements comprising capacitors and discharging devices (diodes or transistors). A time constant detector detects which elements has the discharging time closest to the target. A second array of elements also comprises capacitors and discharging devices, with discharging durations proportional to the discharging durations of the first array. A decoder charges the appropriate element from the second array. After the power is removed, this charged element starts to discharge. During the discharge duration, a comparator outputs a logic one, and a logic zero after the discharge is completed.

Abstract: A semiconductor apparatus includes a test unit including: a data determination unit configured to receive a plurality of data, determine whether the plurality of data are identical or not, and output the determination result as a compression signal; and an output control unit configured to output the compression signal as a test result in response to a test mode signal and a die activation signal.

Abstract: Memory die, stacks of memory dies, memory devices and methods, such as those to construct and operate such die, stacks and/or memory devices are provided. One such memory die includes an identification configured to be selectively coupled to an external select connection node depending on how the die is arranged in a stack. The identification circuit can determine an identification of its respective memory die responsive to how, if coupled, the identification circuit is coupled to the external select connection node.

Abstract: When a measured current of a resistor is less than a preset current value after a device is inserted into a memory slot, a control chip and a storage chip does not receive voltages. When the measured current is not less than the preset current value and a count time reaches a preset time value, the control chip and the storage chip receive voltages, to read or write data. When measured current of the resistor is not less than the preset current value after the device is removed from the memory slot, the control chip and the storage chip receive voltages, to backup data. When the measured current is less than the preset current value and the count time reaches the preset time value, the control chip and the storage chip do not receive voltages.

Abstract: A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.

Abstract: A sense amplifier circuit for a nonvolatile memory that includes a first amplifier to perform a switching operation to output a first signal on a sense amplifier based logic (SABL) node depending on the state of a sensing enable signal, a second amplifier to perform a switching operation to output a second signal on the SABL node depending on the state of the sensing enable signal, a current mirror that sinks current on the SABL node depending on the sensing enable signal and a bit line signal, and an inverter arranged to output the signal on the SABL node as a data signal.

Abstract: A solid state drive is disclosed. The solid state drive includes a circuit board having opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the circuit board of the solid state drive, and the plurality of semiconductor chips of the solid state drive include at least one memory chip that is at least substantially encapsulated in a resin. An in-line memory module-type form factor circuit board is also disclosed. The in-line memory module-type form factor circuit board has opposing first and second surfaces. A plurality of semiconductor chips are attached to the first surface of the in-line memory module-type form factor circuit board, and these semiconductor chips include at least one memory chip that is at least substantially encapsulated in a resin.

Abstract: Memory device and method for fabricating a memory device on two layers of a semiconductor wafer. An example device includes bit lines and word lines fabricated at one layer of a semiconductor wafer and re-writable nonvolatile memory cells that include a two-terminal access device with a bidirectional voltage-current characteristics for positive and negative voltages applied at the terminals. Additionally, a drive circuit electrically coupled to the memory cells and configured to program the memory cells is fabricated at another layer of the semiconductor wafer. Another example embodiment includes a memory device where a plurality of memory arrays are fabricated at one layer of a semiconductor wafer and a plurality of drive circuits electrically coupled to the memory cells and configured to read the memory cells are fabricated at a second layer of the semiconductor wafer.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.