Abstract: Featured is a magnetic ring structure including at least a vortex magnetic state such as symmetrically and asymmetrically shaped nanorings (FIG. 7C), having small diameters (e.g., on the order of 100 nm). In particular embodiments, the width and thickness of the maxima and minima thereof are located on opposite sides of the nanoring. Also featured are methods for fabricating such symmetrically and asymmetrically shaped nanorings (FIG. 1). Also featured are methods for controlling the reversal process so as to thereby create vortex states in such asymmetric nanorings by controlling the field angle (FIG. 9).
Abstract: Featured is a magnetic ring structure including at least a vortex magnetic state such as symmetrically and asymmetrically shaped nanorings (FIG. 7C), having small diameters (e.g., on the order of 100 run). In particular embodiments, the width and thickness of the maxima and minima thereof are located on opposite sides of the nanoring. Also featured are methods for fabricating such symmetrically and asymmetrically shaped nanorings (FIG. 1). Also featured are methods for controlling the reversal process so as to thereby create vortex states in such asymmetric nanorings by controlling the field angle (FIG. 9).
Abstract: A magnetic logic device can comprise a generally planar first substrate for an electrical circuit and a plurality of generally planar second substrates for a magnetic circuit, formed in a stacked arrangement over the first substrate. Each said second substrate can have formed thereon a magnetic circuit and each magnetic circuit can have a plurality of logic elements, a data writing element and a data reading element. The data writing element of each magnetic circuit can correspond in planar positioning to a respective magneto-electrical writing element of the first substrate and the data reading element of each magnetic circuit can correspond in planar positioning to a respective magneto-electrical reading element of the first substrate.
Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.
Abstract: Eccentricity of a optical fiber installed in a passageway of a ferrule is minimized by imposing a force on the end of the optical fiber projecting from the passageway at the ferrule end face to push the optical fiber to a desired position in the passageway, prior to curing an adhesive used for fixing the optical fiber in the passageway, so as to compensate for eccentricity of the passageway. In one embodiment, the force is imposed on the optical fiber by hanging a weight on the optical fiber. In another embodiment, the force is imposed on the optical fiber by using a pressurized jet of fluid. The point of application of the force, the magnitude of the force, and the viscosity of the adhesive are selected such that minimal optical fiber bending occurs, thereby assuring that the optical fiber is positioned at the desired position in the passageway for an appreciable distance from the ferrule end face along the passageway.
Type:
Grant
Filed:
August 11, 2003
Date of Patent:
April 24, 2007
Assignee:
Corning Cable Systems LLC
Inventors:
Brian J. Gimbel, James P. Luther, Thomas Theuerkorn, Hieu V. Tran, Darrell Childers, Dennis M. Knecht