Abstract: An apparatus comprising one or more memory blocks in a programmable logic device. The memory blocks may be configured as content-addressable memory having arbitrarily adjustable tag and data widths.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: A one-shot system for loading a bitline shift register with a typical test pattern is described. Each bitline latch within the bitline shift register is augmented with a one-shot circuit that may pull-up or pull-down the value stored in the bitline latch. The choice of a particular memory test pattern dictates the control of the one-shot circuit.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: Compression and encoding sections (311 (1), 311 (2) and 311 (3) compress and encode input signals VS, AS and SS separately to generate compressed data. A SCSI interface (32) outputs the compressed data to a DSM (50). Output buffers (312 (1), 312 (2) and 312 (3)), a stream interface (34) and an input buffer (33) transfer the compressed data generated at the compression and encoding sections (311 (1), 311 (2) and 311 (3)) to the SCSI interface (32) through data transfer buses (38(1), 38 (2), 38 (3), 39 and 40). A CPU (35), a RAM (36) and a ROM (37) control data transfer through a CPU bus (42).

Abstract: M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.

Abstract: M parallel datastreams are interleaved into a serial bitstream and shifted into a staging register, so that bit zeros of all datastreams shift in first and bit (X-1)s last. All bits of the Mth datastream occupy uniformly spaced non-adjacent memory elements interconnected with a target memory device having M memory registers each of width X. The Mth memory register of the memory device is addressed, simultaneously writing all interconnected bits to the Mth memory register within a single clock period. The bitstream is then shifted by one memory element, such that bits of the (M-1)th parallel datastream occupy the interconnected memory elements, the register address decrements, and the interconnected bits are simultaneously written to the (M-1)th register. This process iterates until M registers are written within an elapsed time of M clock periods. Reading occurs essentially in a reverse sequence.

Abstract: A FIFO is operated so no changes occur on an output thereof in response to (1) only one stage of the FIFO having a signal stored therein when a read command is supplied to the FIFO exclusively of a write command and/or (2) the FIFO being flushed, i.e., erased. Result (1) is achieved by decrementing a write pointer by one without changing a read pointer or by loading the write pointer with the contents of the read pointer. Result (2) is achieved by loading the write pointer with the contents of the read pointer.

Abstract: The semiconductor integrated circuit comprises a parallel-serial converter for converting parallel data read from memory cells into serial data and a switch control circuit for receiving a control signal and controlling the parallel-serial converter. The parallel-serial converter has a plurality of switches connected in a predetermined order. The switch control circuit controls the order of connecting the switches in accordance with the control signal so that parallel data are converted into serial data in a predetermined bit order. This minimizes delay elements formed on the transmission paths of parallel data. Specifically, for example, it eliminates the need for a conversion circuit for changing the bit order of parallel data. This results in faster data read operations from memory cells. Each of the switches in the parallel-serial converter operates in synchronization with a clock signal supplied from the exterior.

Abstract: An architecture for registers and/or memory may provide a selectively disable payload portion. The architecture induced energy conservation. The architecture may include two or more payload portions for storage of payload data and a portion for storage of administrative data. Based on the contacts of the administrative data, certain payload portions may be enabled or disabled.

Abstract: An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock (mclk), for transferring data between the first and second circuitry and achieving a fast turn-around time between a data request from the mclk domain circuitry and a bus request in the sclk domain. A first FIFO buffer for transferring data from the first circuitry to the second circuitry is provided. Logic associated with the first FIFO to synchronize reads and writes to the first FIFO is also provided. A read Bus Request Enable Generator provides a read bus request enable signal to the first circuitry, and an At_least_x_words_filled Flag Generator provides a plurality of flags, which indicate degrees of fullness of the first FIFO buffer to the second circuitry. A second FIFO buffer transfers data from the second circuitry to the first circuitry. Associated logic for synchronizing reads and writes to the second FIFO buffer is provided.

Abstract: Disclosed is a data storage device capable of storing plural bits of data using one storage circuit which can hold two signal levels.

Abstract: It is disclosed a semiconductor memory device and data output buffer thereof in which an area of a layout can be optimized.

Abstract: Apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces. Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. In one embodiment, a hierarchical one of the plural primary nodes includes plural secondary registers, each of the plural secondary registers individually selectable according to a secondary address presented on the serial data line. In another embodiment, a hierarchical one of the plural primary nodes includes plural secondary nodes, each of the plural secondary nodes individually selectable according to a secondary address presented on the serial data line. At least one of the plural secondary nodes includes plural tertiary registers, each of the plural tertiary registers individually selectable according to a tertiary address presented on the serial data line.

Abstract: A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a plurality of output data retaining blocks corresponding to the multiple memory blocks, and a burst counter unit. The output registers alternately receive data transferred from the memory cell array. In accordance with the result of counting by the burst counter unit, the data retained in the output registers is output alternately in bursts, whereby the speed of data read operation in the memory is boosted regardless of the operating speed of the memory cell array therein.

Abstract: An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N.

Abstract: A field memory having a distributed architecture is disclosed and in particular a memory arranged in block, wherein each block stores a bit or bits of said word, said bits having a predetermined position within said word. The distributed architecture improves the transfer of data between the input/output buffers and the internal registers of the memory. A data cache and an improved input erasable realisation are also disclosed.

Abstract: A command buffer for use in packetized DRAM includes a two stage shift register for shifting for sequentially storing two of the four 10-bit command words in each packet. After the first two words of each packet have been shifted into the shift register, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device.

Abstract: A data processing system includes a data processor and a random access memory arranged with plural memory planes. Each memory plane includes N memory arrays; N serial registers, each serial register coupled to a memory array; N block write control circuits; a row address decoder; and a column address decoder arranged for both block decoding and individual column decoding. An address bus and a data bus connect the data processor with all of the memory arrays. Random access for writing data into the N memory arrays may be by individual bits or by blocks of bits. The plural memory planes, the address bus, and the data bus are all fabricated on a single semiconductor substrate. A Z-buffer memory with plural Z-buffer planes may also be included. Each Z-buffer plane includes N Z-buffer arrays; N Z-buffer block write control circuits; a Z-buffer row address decoder; and a Z-buffer column address decoder arranged for both block decoding and individual column decoding.

Abstract: Each of a plurality of FIFO has (1) a low region indicating a minimum number of words for FIFO storage, (2) a burst count indicating the number of words involved in each transfer to such FIFO and (3) a high region where a word count transfer into the FIFO is not initiated. However, a burst count transfer initiated before the beginning of a FIFO high region may be completed in the FIFO high region. Each FIFO is initially filled from a memory by a memory controller to the low FIFO region. Upon word transfer from each FIFO, the memory controller establishes a priority to provide an additional burst count to the FIFO low region. When the memory controller is otherwise idle and the number of words in such FIFO is in a region intermediate the FIFO low and high regions, a burst count for each FIFO may be transferred into the intermediate FIFO region. The memory controller and each FIFO respectively remember the number of words transferred into and from such FIFO.

Abstract: A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Abstract: A semiconductor integrated circuit device including a logic area for executing logical operation and a history holding circuit for managing discrete information concerning respective device, the history holding circuit further comprising an EEPROM for holding discrete information, an input terminal for writing external information into the EEPROM and an output terminal for reading out information held in the EEPROM.

Abstract: A space saving method and floor plan for fabricating an integrated circuit comprising a high density buffer memory. The method and floor plan allow for a significant reduction in the physical area required for a buffer memory of any given size that is fabricated on integrated circuit. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage call be fabricated using much less chip area per bit than the first and third memory stages.

Abstract: According to one aspect of the invention, a serial access memory has multiple shift registers that are clocked simultaneously for designating column addresses. Each shift register shifts an enabling signal that enables access to a certain number of bits at a time. By operating together, the shift registers enable simultaneous access to a multiple of that number of bits. This multiple can be varied to design serial access memories with different word widths. According to another aspect of the invention, there need be only one shift register, but its stages are interleaved. The enabling signal is shifted from a first end of the shift register to a second end, skipping every other stage, then shifted back from the second end to the first end through the stages that were skipped. This operation is repeated cyclically.

Abstract: A reading circuit for a multibit register has a differential stage that is configured as an output latch by one of two control phases required by the circuit after the discrimination phase of a reading cycle a single NOR gate, the output of which is provided with anti-overshoot means, enables the performance of a reading cycle. An input of the differential stage, is connectable to a common sensing line to which all the cells of the register are coupled in an OR configuration, while the other input is connectable to a reference current generator.

Abstract: A serial access memory device is disclosed in which order of access to writing and reading memory cell columns can be controlled. A writing column selecting circuit and a reading column selecting circuit are each comprised of ring pointers with a controllable number of stages. The number of stages of the ring pointers is controlled in response to control signals stored in a serial interface circuit. As a result, two ring pointers each having two stages are formed in the writing column selecting circuit while one ring pointer having four stages is formed in the reading column selecting circuit. After two data signals are written in selected two memory cell columns in parallel, written data signals are read out from serially selected four memory cell columns at a speed twice that in the writing. This serial access memory device is applied to a progressive scan conversion circuit for video signal processing.

Abstract: A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage can be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.

Abstract: A digital video memory circuit. The circuit includes a DRAM for storing thereto and reading data therefrom, a register group having registers for holding data to be written to and read from the DRAM, a selector having switching transistors connecting registers in the register group to an I/O data bus, respectively, for storing data on the I/O data bus to the DRAM and for transferring data from the DRAM to the I/O data bus. The register group includes a first register set and a second register set connected serially between the DRAM and the selector, the second register set transferring data on the I/O data bus to the first register set, and the first register set transferring data from the second register set to the DRAM. The second register set can receive data on the I/O data bus while the first register set writes previously received data to the DRAM.

Abstract: A high performance fault tolerant orthogonal shuffle memory comprising a plurality of memory cells arranged to form a two-dimensional array of rows and columns. Each memory cell includes a data store element for storing data and a multi-state data transmission element to provide access to the data stored in the data store element. Each memory cell has the dual function of storing and transmitting (i.e. shifting) data. The memory cell array is coupled to first and second registers and a shuffle signal generator. In operation, data is shuffled column by column through the array, such that only two columns of memory cells are activated at any time. The shuffle memory herein disclosed may form subarrays of each of a data storage array and a redundancy storage array that are coupled to an improved error detector and corrector to form a high performance fault tolerant orthogonal memory system.

Abstract: A buffer memory architecture, method, and chip floor plan allows for significant reduction in the physical area required for a buffer memory of any given size in a microelectronic device. Buffer applications wherein random access to the buffered data is not required use a CMOS dynamic serial memory with p-channel devices supplied with a voltage less positive than the voltage supplied to their respective n-wells. In a particular embodiment, three memory stages are used in a cascaded fashion. The first and third memory stages store data on a parallel basis, while the second memory stage stores data on a serial basis. The second memory stage can be fabricated using much less chip area per bit than the first and third memory stages. Significant area reduction is achieved because the second memory stage eliminates addressing overhead associated with conventional high-density memory schemes, and low voltage power supplies permit relaxation of latch-up prevention layout rules.

Abstract: A two-cycle asynchronous first-in/first-out (FIFO) device has a plurality of queue registers for holding data, and control cells coupled to the queue registers for controlling data transfer into and out of the registers. Each control cell includes interconnected first and second latches. The first latch receives a request-in signal from a previous control cell and in response produces an intermediate signal. The second latch receives the intermediate signal and in response supplies a request-out signal to a subsequent control cell. The control cell also has a logic circuit coupled to the queue register and first and second latches. In response to input signals, the logic circuit produces load and hold control signals to the queue register and first and second latches. The device includes two-to-four and four-to-two cycle converters that allow the two-cycle FIFO device to be used in either a two-cycle or a four-cycle environment.

Abstract: The present invention reduces the overhead commonly associated with computer queues by not requiring direct addressing of each location in the queue and by not requiring specialized underflow logic. Furthermore, reads and writes to the computer queue of the present invention can be asynchronous. Lastly, the computer queue of the present invention requires less circuitry and is thus physically smaller, requires less power to operate and can operate more quickly than can queues of the prior art.

Abstract: A memory device for storing analog or multilevel data which is easy to produce and of a small scale. The memory device according to the present invention circulates data between a plurality of linear CCD arrays which store data as electrical charges, allows high speed memory access by reading and writing data through cache memory which stores row addresses corresponding to CCD arrays, and includes an address register for registering the address of cache memory data.

Abstract: A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A first pair of circular shift registers are used to control writing data to and reading data from the FIFO. The outputs of each register in each shift register are coupled to enable individual read and write lines of a FIFO memory device. A single logical one value circulates through the shift registers to indicate a FIFO location where data may be written to or from. Toggle latches are coupled to each shift register. The values in the toggle registers change responsive to a read or write operation. By comparing the logical one values in the corresponding positions in the shift registers, and considering the values from the toggle latches, EMPTY and FULL conditions are detected.

Abstract: A FIFO buffer system has an error detection and resetting unit for resetting the FIFO buffer system at the occurrence of errors therein. The system comprises M number of data storage circuits arranged in parallel for temporarily storing the N-bit input digital data and producing the N-bit output digital data in synchronization, each of said data storage circuits synchronously storing (N/M)-bit input digital data and generating storage state signals including a full flag and an empty flag signals representative of the full and the empty states thereof, respectively; and error detection and resetting unit, responsive to the storage state signals generated by said M number of data storage circuits, for generating a reset signal for resetting the FIFO buffer system when there exists a discrepancy among the full flag signal or the empty flag signals.

Abstract: A FIFO memory device using a serial pointer consists of first second memory cell arrays, a row decoder for selecting a word line first and second write registers for storing data, each write register consisting of registers, and a serial write pointer for serially selecting each register. The serial write pointer consists of pointers corresponding to the first and second write registers. The row decoder is located between the first memory cell array and the second memory cell array. In the device, in adjacent registers in each write register, the shift direction of one register indicated by said serial write pointer is opposed to the shift direction of the other register.

Abstract: An object is to enable a semiconductor integrated circuit device to perform the second action, without waiting for the first action to finish after the first action starts. Aside from a resistor containing input signal pulses, an input signal pulses recognizing circuit is provided so that it detects signal input which activates the second action during the execution of the first action and controls driving with the result thereof. In a device such as EEPROM, CPU moves on the next action after writing operation starts. CPU checks periodically whether writing operation is being conducted or has finished, so that the processing ability of a whole device can be improved to the maximum.

Abstract: A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.

Abstract: A method for computing n-dimensional decomposable image transformation using the 1D approach with constrained transpose memory provides a minimized rounding/truncation error. The method minimizes transpose memory size required to fulfill a defined accuracy requirement for n-dimensional image transformation. A set of input data elements are stored. Then, a first transform, of the multiple dimension transform, is performed on the set of input data elements so as to form an array of transformed data elements, each of the transformed data elements having a larger number of bits than the input data elements. A common range of the transformed data elements is determined, and a minimum number of bits required to represent the common range without loss of information is then determined. The memory word size available for storage of the transformed data elements is compared with a minimum number of bits so as to determine an excess number of bits.

Abstract: A parallel data transfer circuit wherein processing at a data transfer source circuit is simplified to reduce the time required for transfer and a data storage area of a data transfer destination circuit can be used effectively is disclosed. A plurality of data register sets for temporarily latching parallel data and a plurality of corresponding flag register sets are provided between a data transfer source circuit and a data transfer destination circuit. A register designation signal is outputted from the data transfer source circuit to designate a data register into which data should be written. Only when data should be written into the data register, a flag is placed into a corresponding flag register. Since the data transfer destination circuit fetches data only from those data registers corresponding to those flag registers in which a flag is held, parallel data can be received without forming a discontinuous empty portion in data storage area of the data transfer destination circuit.

Abstract: The present invention discloses an apparatus for receiving an ordered sequence of input data and for delaying the output of a delay output item by a variable-length delay-time. The apparatus includes an input port for receiving the ordered sequence of input data and the variable-length delay-time. The apparatus further includes an integrated data storage, a random access memory (RAM) for storing the ordered sequence of input data according to a storage-order corresponding to the ordered sequence of the input data. The apparatus further includes a delay output port for accessing and outputting the delay output item in the storage means according to the variable-length delay-time and the storage-order such that the delay output item is delayed by the variable-length delay-time.

Abstract: The present invention provides a memory device for preventing data circulating on a plural number of linear CCD array from being corrupted, for accessing data at a high speed, and for reducing the device's electric power consumption.A memory device according to this invention downsizes a block of a memory cell by circulating data on a plural number of linear CCD arrays which are for storing data by an electric charge on a cell and keeping analog data, which sets a clock generation means for circulating data on all arrays and another clock generation means for circulating at a high speed only the array loops having necessary data.

Abstract: Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles, allowing the write buffer FIFO to make the space consumed by the current write available at the start, rather than at the end of the write cycle. This effectively makes the write buffer "four and one-half" entries deep, thereby increasing performance of the buffer without adding additional FIFO entries.

Abstract: A memory control device for controlling writing and reading data in and from a line memory made up of a plurality of FIFO memories. Writing clocks are circularly applied to the plurality of FIFO memories of the line memory. Also, reading clocks are circularly applied to the plurality of FIFO memories. Thus, although data written in the FIFO memories are discrete, data circularly read from the plurality of FIFO memories are sequential in such order as they are written in the line memory.

Abstract: A plurality of transfer bit lines each extend longitudinally across a memory array block. Transfer switch circuits are disposed between the transfer bit lines and a serial register. Transfer switch circuits are disposed between the transfer bit lines and a shared sense amplifier circuit. The transfer switch circuits are controlled by internal transfer signals, respectively. Transfer switch circuits are controlled by internal transfer signals, respectively.

Abstract: An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Abstract: An integrated circuit including a serial interface (12) having a nonvolatile memory (30) coupled to a and configuration of circuit boards and entire systems. A configurable circuits (10) containing switches, resistors, capacitors or digital logic devices has an unique identification code and is electrically configured by connection to a nonvolatile memory (30). An interrogation shift register (38) and a configuration data shift register (36) are serially connected to receive a serial bit stream (50) containing an interrogation code section and a configuration data section. The interrogation code, which is identical to the identification code of a selected one of the configurable circuits, is compared with the circuitidentification code to provide a match pulse (42) that enables a program signal to initiate transfer of data from the data shift register (36) to the nonvolatile memory (30).

Abstract: A First In First Out shift register memory system (10) with a plurality of memory word registers (50) having data inputs connected to a common data-in bus (16), and a plurality of data outputs connected to a common data-out bus (22). A read address ring counter (36) and write address ring counter (32) are responsive to respective read and write pulses to sequentially perform memory read and write operations. A comparator (40) compares the address outputs of the ring counters (36, 32) for equality. A read and a write signal generator (80, 60) are provided for producing respective read and write pulses in response to input transitions of read and write commands. A last operation R/W flip-flop (70) maintains an account of the last read and write memory operation processed by the system.