Abstract: A semiconductor memory device with shift registers used for a video RAM, including a memory cell array, bit lines, and word lines, a pair of shift registers, and transfer gate circuits arranged between the bit lines and the shift registers. Each parallel data transfer circuit is provided between the shift registers for transferring parallel data between the shift registers, so that high-speed reading and writing of data for a CRT display is realized.

Abstract: A semiconductor memory device including a memory cell array 1, a serial data input circuit for high-speed, large data store in memory cells and a serial data output circuit for high-speed, large data read-out from the memory cells. The serial data input circuit includes a plurality of shift registers 15, for consecutively storing serial input data S.sub.IN applied from an external circuit, and a plurality of first gates 14, for operatively and simultaneously connnecting the shift registers and a plurality of bit lines BL of the memory cell array to store simultaneously the serial input data stored in the shift registers into desired memory cells selected by a desired word line.

Abstract: A semiconductor memory device in the form of a shift register is supplied with two-phase clock signals. One of the two-phase clock signal lines is connected to even order shift register elements of the shift register, and the other of the two-phase clock signal lines is connected to odd order shift register elements of the shift register. Each of the shift register elements includes an output node, a gate connected between the output node and a clock signal supplying node, a charge-up circuit responsive to the output signal of the preceding shift register element for preliminarily charging a control node of the gate, and a discharge circuit responsive to the output of the succeeding shift register element for releasing the charge of the control node of the gate.

Abstract: A circuit has a logic memory, a preceding logic circuit, a succeeding logic circuit, and a function defining circuit. An input signal is taken by the preceding logic circuit, where a new logic state is produced based on the input signal and a present logic state in the logic memory executing a defined calculation. The content of the logic memory is taken over by the new logic state. The succeeding logic circuit produces an output signal based on the logic state of the logic memory executing a defined calculation. The calculation executed in the succeeding or preceding logic circuit is defined by the defining function circuit. Thus, the whole circuit operates with a desired function.

Abstract: A FIFO status circuit suitable to detect the full or empty status of a RAM based FIFO which is asynchronously addressable by write and read access signals. The circuit detects whether the preceding addressing of the FIFO was a read or a write operation to determine whether the FIFO is empty or full. In one form, the trailing edges of the FIFO write and read signals trigger respective pulse generators. Short duration matched pulses drive the corresponding set and reset inputs of a flip-flop. The out Q and Q outputs from the flip-flop are coupled individually to a pair of AND gates. Each AND gate is also driven by a FIFO equal signal, a signal which indicates that both the read pointer and write pointer of the FIFO memory are directed to the same address. Because the FIFO equal signal is stable before the pulses reach the flip-flop, it serves to mask metastable conditions which may arise in the flip-flop.

Abstract: A shift register which, including a plurality of cells each comprising a data latch section and a shift control section, operates without external clocks, wherein the shift control section includes a terminal for receiving a shift start control signal; a terminal for receiving a shift inhibition control signal; a shift allowance control circuit which receives signals indicating as to whether each of the particular cell and the cells adjacent thereto is in a shift operation and signals indicating as to whether each of the adjacent cells is in a state which allows the shift of the particular cell, and generates a shift allowance signal to be given to the particular cell and the adjacent cells on the basis of the states of these cells and the shift inhibition control signal; a shift control circuit which receives the shift start control signal, the output of the shift allowance control circuit, the state signals of the particular cell and the adjacent cell, and makes the data latch section to conduct a shift ope

Abstract: A memory device with a register interchange function includes a register file with a plurality of registers, one of which is selected according to select signals, and a register select circuit. The internal memory state of the register select circuit is updated according to the internal memory state and a pair of interchange data for interchanging the select signals. In a register selection mode, a level setting of the select data is performed depending on the internal memory state and the register select data.

Abstract: There is disclosed a modular memory cell structure including a data latch, an occupancy bit latch and control logic. Each memory cell has access to the occupancy bit status of adjacent cells and to the input, output, control, and status busses. The occupancy status provides positional address information enabling each cell to determine if data in its data latch is the first, intermediate, or last element of a data queue. When a group of memory cells and an initialization circuit are interconnected, a modular integrated circuit design results which can function as either a first in-first out (FIFO) or a last in-first out (LIFO) memory.

Abstract: A series/parallel/series shift register memory system having storage positions provided on a substrate. In addition to the single parallel-connected storage registers required to achieve the nominal storage capacity, there are provided groups of first and second nominally redundant single storage registers. The first redundant registers are used as substitutes for faulty single storage registers, so that the nominal storage capacity can be maintained. The second redundant registers are used for the transport of redundant code data. Also provided is a multi-state sequencer for indicating, in each state, the information to be carried by a particular group of storage registers and for forming, on the basis of this information, an error-detecting or error correction code which is carried by the second redundant storage registers.

Abstract: A wafer-scale integrated circuit wherein a plurality of memory cells on a wafer are connectable from a port to form a chain memory looping away from and back to the port by means of a serial connection of forward moving data registers and a serial connection of backward moving data registers between cells, has a reduced risk of any individual, otherwise functional cell being non-functional as a result of a failure elsewhere on the wafer of an associated global signal line by achieving a reduction in the numbers of global lines by providing the clock signal for controlling the shifting of data in the registers between the cells in parallel with the data, the inter-cell clock operating a multiple clock pulse generator in each cell.

Abstract: For use in a packed nine-bit-byte data processing system, a shift circuit comprises a shifter for subjecting a datum given by a bit sequence of nine-bit bytes to a shift of a preselected whole number N of digits or, more particularly, a shift of [9N/2] and [9(N-1)/2+5] bits when the whole number is an even and an odd integer, respectively. Before written in a register, the shifted bit sequence is edited by an editor into an edited bit sequence wherein each prescribed binary bit in each nine-bit byte is produced as it stands when the whole number is even and is placed, when the whole number is odd, at a next more significant bit than a four-bit byte which is next more significant in the shifted sequence than that binary bit.

Abstract: A first-in-first-out memory device which is operable at a high-speed is disclosed. The memory device comprises a plural stages of memory units and a plural stages of control unit, each of the control units including a circuit for indicating whether its stage holds effective data or not, a circuit for receiving a signal of the indicating means of the previous stage, and a circuit generating a write signal when the memory cell holds no effective data and the previous stage hold effective data, in which the write signal is used to remove data stored in the previous memory cell to the corresponding stage memory cell.

Abstract: A FIFO memory comprises a plurality of readable and writable data banks, a mode indicating circuit for indicating a write mode to a plurality of data banks repetitively, and a read/write control circuit for writing received data to the data bank to which the write mode has been indicated and reading the data from the data banks to which the write mode is not indicated.

Abstract: An electronic circuit for regulating the entry of new data into a static synchronous register comprising a bank of D type, master-slave flip-flops. The circuit selectively passes the first phase of a two-phase, nonoverlapping clock signal used for synchronization and control of the data. A bootstrap operated, series pass, transistor configuration couples the first phase signal to the electrode actuating the master stage of each flip-flop. With provisions for the series pass transistor to transition into a conductive state prior to the onset of the first phase signal, the circuit ensures substantial replication of the first phase signal characteristics in terms of both time and amplitude.

Abstract: A memory device which is effectively utilized as serial access memory with variable shift length of stored data is disclosed. The memory device comprises memory cells arrayed in a matrix form, a shift register whose output is used for selecting memory cells and control means for varying shift length of the shift register.

Abstract: A shift register of the type capable of performing shift operations by changing the access of a random access memory, which is capable of performing the operations at a high speed, with respect to the address for reading data and the output of a counter, the input to which is a clock pulse. In order to increase the operations of the shift register, the operation of the address is performed in a power form or each input data is written at two different addresses of the random access memory.

Abstract: A storage register which may be used to store several sets of data. The storage register may also be used as a demultiplexer to separate two or more sets of data that were received by the register over a single data line. The storage register includes a closed circuit loop of pairs of field effect devices and pairs of clocking devices wherein the clocking devices are coupled between the field effect devices. Input and output terminals are coupled to selected field effect devices. Embodiments of this storage register permit several bits of information to be stored simultaneously in the closed circuit loop and still remain accessible to input and output terminals at different times controlled by the clocking means. A further embodiment provides for several closed circuit loops to be arranged for the parallel storage of data bits.

Abstract: A data buffer circuit is disclosed for receiving from a serial-to-parallel ata conversion interface circuit a plurality of sixteen-bit parallel data words, for storing therein for a predetermined time period each of the parallel data words, and for transferring to a computer, so as to allow for processing by the computer, each of the parallel data words.

Abstract: Apparatus is described for recording certain operating conditions of a motor vehicle, those conditions occurring upon the braking of the vehicle, and the apparatus is particularly applicable to vehicles equipped with antilock braking systems. A shift register is controlled by an oscillator in continuously shifting operation. When a predetermined driving condition occurs, the state of the first register location is changed. In the event the device is used for recording a braking condition, there is provided a time delay switch which locks the shift register at the point it has reached when a predetermined delay time is exceeded. The aforementioned shift register can be constructed in the form of an electromechanical shift register which responds to a signal generated through the operation of a stop lamp switch.

Abstract: An input bias circuit for a charge transfer device array in which the fat zero signal level is a function of device threshold voltage and other device parameters. The use of such a circuit eliminates the need to adjust or tune the reference or bias level from array to array. The circuit includes the addition of a diode connected field effect transistor and capacitor between the input device, the source of the first charge transfer device stage, and the input gating device such that the minimum discharge level is set, on the input node, a threshold voltage drop above the reference level. When device threshold voltages are higher the charge established on the input node is decreased to compensate for the decrease in charge transferred by the register stages. Matching of the sizes of the diode connected field effect transistor with the input device and the devices in each stage of the array insures accurate tracking with process variations.

Abstract: A serial recirculating store is provided with data processing units distributed along its length and a fast data line interacts with the serial store at each processing unit for controlling processing operations. The store is divided into segments with selectively operable bypass lines. A processing unit can operate on information passing therethrough from the associated segment and from the succeeding segment via the bypass line. Autonomous data processing routines can be effected in recirculating portions of the store as data thereon repeatedly leapfrogs other data utilizing the bypass lines.

Abstract: A data buffer memory of the "first-in, first-out" type, having a fixed input by which data are applied to the buffer, and an output bus by which data are extracted from the buffer. The buffer includes logic means whereby a variable output location can be selected. The logic means determines by means of status signals in cooperation with signals applied from outside the buffer, where data are read from the buffer and, if necessary, when data in the buffer are to be shifted further from the input location.

Abstract: A shift register is described particularly adapted for selectively controlling the energization of the windings of a stepping motor so as to provide selective overlapping phase energization. The shift register consists of four stages each having master and slave sections with each stage controlling the energization of an associated motor winding. A shift register control unit, responsive to stepping and directional signals, directs the shifting of information between the various stages of the shift register. In response to a step high input signal, a high level of one shift register stage is shifted in a selected direction to the adjacent stage with both stages directing the energization of their respective motor windings. Similarly, in response to a step low signal the low levels of the shift register stages are shifted in a selected direction to their adjacent stages causing the deenergization of the respective motor windings.

Abstract: A register data transmission system has a plurality of register devices connected in series to form a data transmission link between a sending device and a receiving device. This register system can function between independent synchronous operating units of a computer such as a pair of data buffers. As data is transmitted, the individual register devices absorb the data as compactly as necessary within limits, to form the data path. Each register device has two data registers and two control flip-flops. The two data registers are the primary and secondary data rank registers. The secondary data rank register only receives data when the primary data rank register cannot receive data. The two control flip-flops are the primary and secondary full-bit flip-flops. Each register device has a clock control. In operation, data travels from the sending device through each register device to the receiving device while a control signal travels from the receiving device to the sending device.

Abstract: A diagnostic arrangement is disclosed for determining the length of arbitrary shift registers not exceeding a maximum length. Knowledge of this length is an essential prerequisite for data manipulations by means of shift registers. Concerned are the reading of shift registers and the display of the contents stored in them, as well as the writing of arbitrarily selectable patterns into said shift registers.The arrangement proper includes circuitry connected to the shift register or test object for generating a test shift pattern of the length L.sub.max +K, with K.gtoreq.2, which pattern is made up of a defined bit configuration, for example, only binary ones, with a defined transition at the end facing the test object and which is shifted through the test object. Also provided is storage means of length L.sub.max +K, which is connected to the output of the test object and which, as the test shift pattern is shifted, accommodates the information of the length L.sub.x of the test object and the part L.sub.

Abstract: A volatile/non-volatile RAM cell employing a bistable multivibrator with non-volatile, alterable-threshold capacitors coupled to the output terminals thereof to provide backup data storage in a power-down situation. In one embodiment, the non-volatile capacitors each have a non-alterable section and an alterable section, the non-alterable section having either a depletion or an enhancement threshold. The V/NV RAM cell employs a pair of field effect transistors of depletion or enhancement type to couple the non-volatile capacitors to the output terminals. These coupling transistors form with the non-volatile capacitors a pair of nodes. The coupling transistors are biased such that a write voltage signal applied to the gates of the non-volatile capacitors produces a bootstrapped voltage on one of the pair of nodes which is effectively isolated from the output terminals of the cell.

Abstract: A nonvolatile semiconductor memory apparatus is provided which comprises a flip-flop circuit formed of a pair of MOS FETs and a pair of MNOS FETs coupled to the bistable output terminals of the flip-flop circuit, respectively. The memory apparatus further has a pair of MOS FETs coupled to have the current paths in parallel with the current paths of the pair of MOS FETs of the flip-flop circuit.

Abstract: A shift register is described particularly adapted for selectively controlling the energization of the windings of a stepping motor so as to provide selective overlapping phase energization. The shift register consists of four stages each having master and slave sections with each stage controlling the energization of an associated motor winding. A shift register control unit, responsive to stepping and directional signals, directs the shifting of information between the various stages of the shift register. In response to a step high input signal, a high level of one shift register stage is shifted in a selected direction to the adjacent stage with both stages directing the energization of their respective motor windings. Similarly, in response to a step low signal the low levels of the shift register stages are shifted in a selected direction to their adjacent stages causing the deenergization of the respective motor windings.

Abstract: A sense line termination circuit is provided intercoupled between a sense line of a plurality of static memory cells and a supply bus of high pull-up voltage to provide fast access to the memory cells with limited medium power dissipation. The termination circuit functions to pull up the sense line toward a predetermined intermediate high voltage value (which is about one threshold voltage Vt below the high pull-up voltage) when no memory cell has a low voltage memory node coupled to the sense line. The sense line termination circuit limits the voltage excursion of the sense lines and also permits the sense line to be pulled down with predetermined current limitation to a low voltage value when the sense line is coupled to a low voltage memory node.

Abstract: An information handling apparatus capable of having a large number of input/output ports includes a plurality of independent processors connected to respective positions around a plurality of closed rings of shifting registers arranged in parallel which form the main storage medium for the apparatus.

Abstract: A data source is connected through a gating circuit to all stages of an asynchronous shift register. The gating circuit senses the full or empty status of each stage of the shift register and enters an incoming bit of data into that stage of the shift register which is the empty stage nearest the output, and has no stage preceding it which is full. The arrangement decreases the delay time normally encountered by data as it is shifted through the shift register, the decrease in delay time being related to the number of empty stages in the register at the time a bit of data is entered.

Abstract: This disclosure is directed to a First In First Out memory which comprises a register, an input control section, a register control section, and an output control section. The imput control section allows data to be entered into the First In First Out memory while the register control section shifts the data through the memory queing up at the locations closest to the output. The output control allows data to be taken out of the FIFO at a different rate than data is entered into the memory by the input control section. The register control section monitors the succeeding location and the previous location in the register to determine when data may be shifted in the register.

Abstract: An improved electrically alterable non-volatile memory for storing information is described incorporating an array of memory cells comprised of variable threshold field effect transistors, means for selecting a row in the array, means for writing information into the memory cells of a selected row, and means for reading information from the memory cells of a selected row by comparing the voltage difference of successive memory cells in the selected row.

Abstract: Disclosed is a plurality of parallel resistive-capacitive clamping circuits ndividually coupling the bit "input" and bit "output" terminals of a multi-bit, serial/parallel (S/P), synchronous/asynchronous (S/A) shift register (e.g., CD-4034A). The clamping circuits provide the contents of the shift register with an increased immunity from the effects of transients, radiation, and temporary power failures.

Abstract: A circular shift register memory system comprising L sections each having K circular charge storage shift registers of N bits each for storing blocks of N, K-bit words and accessing the words or blocks thereof in parallel. The L memory sections are refreshed by N-bit clock bursts which are successively and periodically applied to the memory sections by a refresh counter, decoder and gating logic. A read/write decoder decodes memory section addresses and controls the application of N-bit clock bursts to the particular addressed memory sections for access purposes. In a random access mode, word access is facilitated by counters which count the number of read/write or refresh clock pulses for comparison to a word address.

Abstract: This disclosure relates to a charge coupled device memory that is content or associative addressable with the respective word locations (loops) being searched concurrently although word access is serial in manner. Data bits in respective word loops are arranged in a staggered manner such that when the first bit of the first word is at its comparison location, the second bit of the second word is at its comparison location and so forth. The comparand and mask bits are shifted serially from comparison location to comparison location and recirculated in synchronism with the recirculation of the word loops. Content addressing logic includes a series of match bit shift registers, one for each comparison location, to record match occurrences. When a word match occurs, the address of the respective word loop is sent to the memory to read out the data bits stored therein.