Abstract: An apparatus and method of clock synchronization of a powerline modem network for a plurality of devices are provided. A plurality of devices are provided having a powerline modem and a clock (100). The powerline modem permits communication between the plurality of devices over a powerline network. A synchronization message is provided over the powerline network (102). The synchronization message includes an instruction for each of the plurality of devices to update their clock in accordance with a clock time provided in the synchronization message (104). A synchronization device may be provided to update device clocks on a powerline network.

Abstract: The present invention relates to a mobile terminal (1) for a wireless telecommunication system and a method providing accurate real time information in such a mobile terminal (1). The mobile terminal (1) comprises input means (3) for inputting basic time information (T0), memory means (4) for storing basic time information (T0) input via said input means (3), real time means (2, 5) for continuously providing real time information (Tx) on the basis of low frequency oscillation signal and said basic time information (T0), and processing means (5) for computing a correction value (K) for correcting said real time information Tx to obtain an accurate real time information (Tacc) on the basis of an accurate time difference between a first accurate time information (T1) and a second accurate time information (T2) and a real time difference between a first real time information (Tx1) and a second real information (Tx2) from said real time means (2, 5).

Abstract: A synchronous analog clock movement is provided for use in a secondary clock of a master-slave clock system. The movement keeps time independent of the master clock through a primary time base and a clock counter of a microprocessor. The movement is capable of receiving a time-correction signal from the master clock. The microprocessor controls a quartz movement motor. The microprocessor receives and recognizes the time-correction signal from the master clock, and then performs the time-correction process of advancing the movement to the correct position. The processor can keep time during a power failure through the use of a reserve power supply and secondary time base. Upon restoration of power, the processor will advance the quartz movement to the correct position. Optical sensors are connected to the microprocessor for determining the position of the hour and minute hands, or associated gearing, of the quartz movement.

Abstract: In accordance with one embodiment of the invention, an integrated circuit includes: a digital signature module coupled in the integrated circuit so as to receive a time of day signal string from a clock module and digitally sign the signal string.

Abstract: A time information repeating installation in a radio clock system, which receives advance notice information, distinguishes advance notice content by detecting means 9, sets a transmission start time by addition setting means 10 in accordance with the content, sets an additional period by change period setting means 11, and stores the content into transmission start time storage means 12. When the stored time agrees with the time of a main counter 8, transmission starts. Therefore, even when a sudden time change occurs, the repeating installation can perform transmission at the reception timing of a subsidiary device. The subsidiary device can effectively update time data for summer or daylight savings time.

Abstract: A network user station (2), which in a transmitting mode transmits telegrams (5) to another network user station (2) and in a receiving mode receives telegrams (5) from another network user station. Said telegrams contain messages of identical message length in a message string. One of said messages is a time message (5d) provided with a time of day. The network user station is provided with means (11; 13) for substantially preventing inaccuracies with respect to a transmittal and/or processing instant of the time of day.

Abstract: A network user station (2), which in a transmitting mode transmits telegrams (5) to another network user station (2) and in a receiving mode receives telegrams (5) from another network user station. Said telegrams contain messages of identical message length in a message string. One of said messages is a time message (5d) provided with a time of day. The network user station is provided with means (11; 13) for substantially preventing inaccuracies with respect to a transmittal and/or processing instant of the time of day.

Abstract: To set the initial time in a clock managed by an operating system in a personal computer system, when the power is turned on, the ROM-BIOS of the personal computer system is checked and the operating system is booted. Next, the current time is read from a CMOS clock of the personal computer system and the time read is set as the initial time in a clock managed by the operating system. Then, the current time is read from the CMOS clock again and the read current time is compared with the time of the clock managed by the operating system. If the times do not match each other, the above reading and setting processes are repeated. Thus, the time managed by the CMOS clock and the time managed by the OS clock in a PC system can coincide so that the time managed by the OS clock can be reliable for application programs requiring an accurate real-time management.

Abstract: A system is disclosed for synchronizing a clock in a well containing a drill string with a clock located near the surface of the well. The system includes devices for transmitting and receiving a pair of acoustic signals between locations associated with each clock and processing those signals. The system determines the time of arrival of each acoustic signal by analyzing the shape of a function of the acoustic signal chosen from a group of functions suitable to determine a clock offset with millisecond accuracy.

Abstract: A network subscriber (2c) is provided with a clock (8) and is connected to a further network subscriber (2a) via a network (1). In a receiving mode, the further network subscriber (2a) supplies a time message (5, Un) containing a time of day to the network subscriber (2c). The network subscriber (2c) includes a synchronization assembly in the form of an adjustment unit (10) that permits improved synchronization accuracy of the time of day. If a deviation between the time of the day included in the time message (5, Un) and a further time of the day indicated by the clock (8) is smaller than a predefined limit value, the synchronization assembly synchronizes the clock (8) with the time of the day that is included in the time message (5, Un) supplied by the further network subscriber (2a).

Abstract: A time information management system with a simple configuration that instantaneously causes the individual time information of a plurality of timekeeping means within a prescribed area to coincide with standard time information, is formed by time information signal generating means that generates time information that includes standard time information, a time information adjusting means that includes within it a first timekeeping means, receives a time information signal, and outputs time information of the timekeeping means, and second timekeeping means 5-1, 5-2, . . .

Abstract: A system and method is disclosed for synchronizing clocks in a plurality of devices connected by a communication channel. A master control device is coupled to one or more slave control devices, e.g., event recorders, across a communication channel. Preferably, the communication channel is implemented according to an RS-485 interface. By periodically interrogating and monitoring the responses of each of the slave control devices, the master control device determines the transit time, i.e., communication, delays to each of the slave control devices. Operating in conjunction with this data, the master control device can then interpret and/or adjust any event times reported by the event recorders to improve the relative time accuracy of the event recorders as compared to a time maintained by the master control device. Consequently, the control system can achieve a relative time synchronization accuracy between the master and slave times to within 100 microseconds and preferably 100 nanoseconds or less.

Abstract: A technique for setting time of an apparatus which receives signals either from a single analog channel and a single digital channel or from a plurality of analog channels and a plurality of digital channels. In the case that the apparatus receives signals from a plurality of analog channels and a plurality of digital channels, a determination is first made as to whether an input signal is from one of the analog or digital channels. Then, if the input signal is determined to be a signal from one of the digital channels, the current time is set based on current time information from the signal of the digital channel. Conversely, if the input signal is determined to be a signal from one of the analog channels, the current time is set based on the current time information from an arbitrary digital channel.

Abstract: An electro-luminescent night light includes an analog time piece. The time piece display includes a mechanical analog clock illuminated by at least one electro-luminescent element positioned around the shaft assembly for the clock, the shaft extending from a conventional analog time piece unit powered by a conventional power source, with the electro-luminescent element being powered by prongs arranged to be inserted into an AC outlet or other power source, or to be powered by a separate battery and circuit that causes the electro-luminescent element to illuminate in case of a power failure or a condition such as the presence of smoke, an earthquake, or the like, the time piece also optionally including additional functions. In addition, the orientation of the time piece display may be made variable in order to enable the night light/time piece to be used in different orientations.

Abstract: A redundant computer system including two systems capable of independent operation. The two systems correspondingly employ two independent clock generation and distribution (CGD) units which each issue clock and clock definer signals. The clock and definer signals of each system are used internally and are also sent to the other system. When the two systems are split, phase locked loops in each system are disabled, and each system is controlled by a precision oscillator in its own CGD unit When the two systems are merged, one CGD is designated as master and remains under control of its internal oscillator. The clock and definer signals of the master system are employed in the slave system to derive a signal which is used as the reference input to the slave system's phase locked loop from which the slave system's clock and definer signals are developed. Preferably, dual flip-flop phase detector type phase locked loops are employed.

Abstract: A clock synchronized by date and time information taken from Caller ID information packets delivered with incoming calls on a telephone line provided with Caller ID service.

Abstract: A device (10) for automatically adjusting a device containing a clock (70) that derives its timing function from the frequency of an alternating current signal on a power line is provided. The device (10) includes a controller (15) that receives user-entered controls for adjusting the clock (70) and generates control signals in response to the user-entered controls. The device also includes a frequency changer (11) that responds to the control signals to increase or decrease the frequency of the alternating current signal applied to the clock (70) so that the clock (70) may be adjusted.

Abstract: Many devices (in particular white goods or brown goods) in a household may contain a clock. Some systems allow connection of such devices and their related clocks to a common bus or network. The commands for controlling the clocks are in general limited to reading or writing a given time or to broadcasting the time of a given clock to one dedicated device or to the entire system or to a part of the system. In such known systems it is not specified in which manner a clock should react if it receives the time broadcast by another clock. It is possible to initialize all clocks to a given time, but due to tolerances in the different clocks, so achieved synchronization will not be maintained. Regular broadcasting by a special device master clock has the disadvantage of introducing one device with different capabilities. In case there are several master clocks, conflicts may occur and the advantages of a high precision clock will fade away if a lower precision master clock overrides it.

Abstract: A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.

Abstract: A method of providing a standard coordinated time throughout spatially separated functional modules of an industrial controller employs a module operating as a time master which transmits a coordinated time to various dependent modules through communication modules. The dependent modules have local clocks which are synchronized to the coordinated time value by adjusting their clock frequency according to the difference between local time provided by that clock and the coordinated time value. This gradual correction prevents lost count values and disruption to the control process. The most and least significant bits of the time value may be transmitted at separate rates to reduce link traffic.

Abstract: A clock apparatus has a first clock unit, a backup power supply unit, a second clock unit, and a control unit. The first clock unit is used to count time, and the backup power supply unit is used to supply a backup power voltage to the first clock unit, when a general power supply unit does not supply a general power voltage to the clock apparatus. The second clock unit has a higher accuracy than the first clock unit. The control unit is used to adjust the time counted by the first clock unit in accordance with a specific period counted at the second clock unit, and the control unit is also used to control the resetting of an operation of the second clock unit, when the general power supply unit starts to supply the general power voltage to the clock apparatus after the general power supply unit has been stopped.

Abstract: A clock synchronizing apparatus is constructed of a multi-input PLL circuit. The multi-input PLL circuit comprises a phase comparator, a variable frequency oscillator, a loop filter, and an adding device. The phase comparator includes a plurality of subtracting devices for subtracting an output signal from each of input signals and a plurality of amplifiers for obtaining a phase comparison characteristic corresponding to the output signal of each subtracting device and for amplifying each phase comparison characteristic by a predetermined gain. Each gain is predetermined for each input signal. One dominant gain is greater than the sum of the other gains.

Abstract: Apparatus and methods are provided for synchronizing a clock to a network clock. In one embodiment the apparatus includes a device for receiving a first compressed code representative of, and compressed in length from, the combination of a channel, a time-of-day, and a length of time for a first program on a first day and on a first channel currently displayed on a television, a decoder for decoding the first compressed code into a first channel, a first time-of-day, and a first length of time, a device for receiving an end of program indication for the program, and a device for loading the sum of the first time-of-day and the first length of time into the clock calendar in response to receiving the end of program indication.

Abstract: Disclosed is a clock distributing apparatus for distributing clock signals with a desired phase to each of devices provided between a clock generating section (10) for generating clock signals and a plurality of devices (30) for receiving the clock signals. A delay generating section (21) generates a plurality of delay clock signals by imparting a plurality of delay quantities to the clock signals from the clock generating section. A clock distributing section (22) has a plurality of input terminals corresponding to the plurality of delay clock signals and a plurality of output terminals corresponding to the respective devices. The clock distributing section (22) distributes desired delay clock signals to one or more output terminals by selecting the input terminals corresponding to the desired delay clock signals.

Abstract: A master secondary clock system of the analog impulse type consisting of separate motor driven secondary clocks and a master control unit. The secondary clocks can be set at any time by an appropriate signal from the master clock so that even widely scattered secondary clocks can be brought at any time to the correct time. In one disclosed embodiment, the secondary clocks are moved by a series of rapid pulses form the master clock to a predetermined known time, the secondary clocks are brought into registry, the master clock calculates the time disparity between the registration time and the real time, and the secondary clocks are moved in unison to the real time.

Abstract: An electronic system is used with one or more digital clocks. The electronic system comprises a two-wire module, attached to the digital clock, for allowing each digital clock to be run and reset to the correct time. A master clock controls a DC supply voltage applied to the two-wire module. The DC supply voltage keeps the digital clock in synchronization with the master clock. Interrupting the DC supply voltage and subsequently reapplying the DC supply voltage causes the two-wire module to set the digital clock to a predetermined time. Reversing polarity of the DC supply voltage for a calibrated time period electronically activates the two-wire module to reset the digital clock to the correct time.

Abstract: In a process for operating computing units in communication with each other by serial data transfer over a data bus, each unit having its own clock generating system and the computing units exchanging timing information over the data bus, provision is made to generate a system timing using the transfer protocol that is valid for the system. For this purpose, a time registration start signal is first fed into the data bus; thereupon, each computing unit stores its own time value upon identification of the time registration start signal, transfers the stored own time value at a later moment in time to the other computing units and stores the time values received from the other computing units. Each computing unit then compares its own stored time value with the stored time values of the other computing units and calculates the present time value of the other computing units taking into account its own present time value.

Abstract: A method and provides for transmitting a time reference throughout a residence or other facility for use by appliances operating within the facility. A time reference is received from the headend of a cable television (CATV) system at the subscriber converter and is retransmitted to set the internal clock timers of residential appliances throughout the house. The time reference is received by the CATV converter, then encoded and modulated for transmission on the residential AC wiring system which also carries AC power to all of the appliances in the house. Individual appliances receive the encoded time reference from the AC power line, demodulate the received signal and use the received time reference to set its internal clock timer. In such manner, a residential appliance does not need to have its internal clock set by the consumer.

Abstract: A clock supply apparatus provided in each slave office, wherein a single master clock is received at a clock receiver unit; 0-system and 1-system system clocks are paired and are distributed to the transmission units at terminal ends via a plurality of duplexed clock supply routes; and multistage clock selection units are hierarchically inserted into the duplexed clock supply routes. The system-selection unit for controlling the selection of the 0-system or 1-system at each clock selection unit is given a 0-system and 1-system duplexed structure and is constituted by a system switching command unit for instructing this system-selection.

Abstract: An improved system for providing ensemble time from an ensemble of oscillators is provided. The improved system provides an ensemble time definition whose large number of possible solutions for an ensemble time are constrained to a limited number of solutions. In one embodiment, a substantially infinite number of solutions is constrained to a single solution.

Abstract: A system for operating a pair of microprocessors with independent system clocks while at the same time providing synchronization by a common interrupt signal, and in which the system clocks are cross-monitored to thereby provide Fail-Safe operation.

Abstract: A master/secondary clock system of the impulse type consisting of stepper motor driven secondary clocks and a master control unit. At five minutes before a predetermined registration time, for example 6:00, the sensor of each secondary clock movement is activated by a reverse polarity signal from the master control unit and a series of reset pulses are thereafter transmitted to the secondary clocks with each secondary clock stopping as the window in its drive train gear moves into alignment with the emitter and detector of its sensor mechanism. After this five minute pulse reset phase to correct clocks that are five or less minutes fast, the master control unit transmits a rapid pulse train so as to quickly move all of the remaining clocks to the 6:00 position with each clock being halted at the 6:00 position by movement of the window of its gear into alignment with the emitter and detector of the sensor mechanism of that clock.

Abstract: A master clock generator for a variable speed constant frequency electric power system includes a frequency select circuit for selecting an external or internal frequency reference signal and a phase comparator for producing a phase error signal representative of the phase difference between the frequency reference signal and an output clock signal. The phase error signal is combined with a control signal to produce an adjusted phase error signal. This adjusted phase error signal is integrated and a voltage control oscillator is used to produce the output signal in response to the integrated adjusted phase error signal. The control signal introduces a desired phase error between the reference signal and the output signal. Clamping circuits are provided to limit the maximum and minimum magnitudes of the integrated adjusted phase error signal, thereby limiting the maximum and minimum frequencies of the output clock signal.

Abstract: A clock synchronous system which secures time synchronization in a network station including a master station and a plurality of slave stations. The system monitors, at all time, a time difference between a reference time of the master station and a present time of the slave station. When the time difference exceeds a predetermined value, the system divides that time difference by a predetermined correction number to find a time correction coefficient and gradually corrects the time difference of the slave station by the time corrections coefficient.

Abstract: An improved system for providing ensemble time from an ensemble of oscillators is provided. In the system, a more complete ensemble definition permits a more accurate ensemble time to be calculated. The system takes into account at least weighted time and weighted frequency aspects or weighted time and weighted frequency aging aspects of each oscillator in the ensemble. Preferably, the system takes into account all of the weighted time aspects, weighted frequency aspect, and weighted frequency aging aspects for each oscillator in the ensemble. The weights with respect to each clock can be chosen to be either zero or any positive value such that the sum of the weights for each aspect sum to one. The system can be implemented using a Kalman approach.

Abstract: A method of operating and maintaining the clock of the system for determining a reference clock of the system when starting an operation and maintenance processor (OMP), comprises the steps of: a first step of requesting and receiving a hardware clock from a network synchronizing processor (NSP); a second step of checking if the received hardware clock does not fall between a predetermined minimum and a predetermined maximum, and if so, providing an alarm message which requires an operator to provide information on a reference clock and if not, requesting reference clocks from all of the processors except an operation and maintenance processor (OMP); and a third step of comparing the hardware clock and the received reference clocks as many times as the number of the received reference clocks, and determining the hardware clock as a reference clock of the system if a difference is less than or equal to a predetermined time for more than the predetermined number of times and if not, providing an alarm message w

Abstract: A power system includes as many synchronizing units as the number of the power units. Each synchronizing unit has been designed to receive an activation signal at its input and to be connected to the other units through of a first and a second discs. Each synchronizing unit delivers to its output a synchronizing clock signal for the respective power units. The first synchronizing unit which receives the activation signal is qualified as the master unit. This master unit applies a predetermined polarity to the first bus and a clock signal to the second bus in order to synchronize the other units in response to the detection of the polarity on the first bus, the other units are characterized as slave unit.

Abstract: A clock control system for a multiple channel electric power system includes a master clock circuit and control circuitry in each parallel connected channel. The channel control circuits are intially phase-locked to a master clock signal. If the master clock signal is out of a preselected frequency range, the individual channel control circuits are decoupled from the master clock signal and one of those circuits produces a backup clock signal. The control circuits in the remaining channels are then phase-locked with the backup clock signal to provide continued parallel system operation.

Abstract: A timepiece receives an externally transmitted radio signal corresponding to an accurate time of day. Disposed within the timepiece is a detecting mechanism for detecting the time of day being displayed by the timepiece. The signals are compared to determine the accuracy of the timepiece. The detection mechanism comprises an optoelectrical system which includes an emitter for directing a beam of radiation toward the sensor. The wheels of the gearworks intersect the beam ahead of the sensor to normally block the beam from the sensor. The wheels include orifices which, when aligned with the beam, permit the beam to reach the sensor, thereby providing an indication of the position of the wheels, and thus of the time being displayed.

Abstract: A remote time calibrating system has a calibrating station with a reference time and a remote station having a local time, the local time having to be adjusted to coincide with the reference time. The calibrating station receives telemetry signals sent from the remote station, each of the telemetry signals including data indicating the local time of the remote station from which the telemetry signal is transmitted. Responsive to any first difference between the receive reference time and the local transmit time is detected and calculated by taking into account the signal propagation delay of the telemetry signal between the remote station and the calibrating station. Responsive thereto, the local time is calibrated at the remote station.

Abstract: A system is provided for distributing coded time or other information signals through the electrical gridwork of a facility such as a home, office, factory, or mobile vehicle for purposes of information display and/or control and monitoring of equipment and activities thereof.

Abstract: A method of synchronizing a digital timer with the frequency of a source of A.C. power to provide long term temporal stability. The timer produces internal, fine resolution, synchronization and real time timing signals from a source of clock signals. The periods of all the timer produced timing signals are integral multiples of the period of its internal timing signal.A.C. reference timing signals which are a function of the frequency of the source of A.C. power are applied to the timer. The quotient of the period of the synchronization timing signals by that of the A.C. reference timing signals is an integer "n". Once n is determined, the number of fine resolution timing signals in each synchronization period for every n.sup.th A.C. timing signal is compared with a reference value. The timing of the fine resolution timing signals is adjusted to maintain the number of fine resolution timing signals in each synchronization period at which the n.sup.th A.C.

Abstract: Time referenced RF signals are periodically received and processed for updating a microprocessor-controlled clock. The clock automatically scans several frequencies at which the coded RF timing signals are transmitted, selecting the strongest received signal for synchronization therewith and causes a capture LED to be illuminated upon detection of a sufficiently strong signal at the beginning of a minute tone at one of the received frequencies. The microprocessor periodically determines the timing difference between an internal timer and the received RF timing signals. A time difference correction is provided to a digital-to-analog converter which provides an appropriate voltage to a varactor diode in a crystal oscillator circuit for adjusting the microprocessor's operating frequency until it can no longer resolve a difference between the received RF timing signals and its internal timer.

Abstract: A master/slave clock system including a slave clock configured for inexpensive and reliable control from the master. Each slave clock has an unregulated d-c supply adapted to be supplied with a-c power from the master clock. Threshold switching means in each slave clock is coupled across the d-c supply to sense an abnormally low d-c voltage level intentionally created by lowering the a-c supply level from the master. The threshold switching means switches the clock from the normal operating mode to the set mode where time is incremented at a predetermined rate for a duration controlled by the master clock in order to controllably set all slave clocks in the system to the correct time of day. The system conveniently allows all slaves to be reset to the same time when time is reset at the master, provides for automatic recovery after power failures, and provides a convenient means for automatically resynchronizing all slave clocks twice a day.

Abstract: A timer system (10,110,210) of two or more timers (10,110,210) measures the response time between an initiating event and a dependent event. The initiating and dependent events may be physically separated or electrically isolated. The timer system (10,110,210) permits recording of associated initiating and dependent events for a response time test followed by the recording of additional associated initiating and dependent events for additional response time tests while the timers remain separated. Thus, the timer system (10,110,210) permits serial recording of information for a large number of response time tests. The timers (10,110,210) may be identical. The timers (10,110,210) are interconnected and synchronized, then disconnected and separated to record the time of occurrence of the physically separated or electrically isolated events. The timers (10,110,210) are then again interconnected for a simultaneous recording of the elapsed time on each timer.

Abstract: A method for synchronizing a master clock and a remote slave clock which nominally has the same pulse frequency but may be out of time-phase comprising transmitting a master pulse to the slave, measuring the time delay, .DELTA..tau., between the received pulse and the nearest succeeding (in time) slave pulse, delaying the latter slave pulse by .DELTA..tau. to provide a conjugate slave pulse, transmitting the conjugate pulse to the master station and measuring the time difference .DELTA. between time of reception of the conjugate pulse and time of generation of the original master pulse. The time .DELTA. is equal to twice the error between the master and slave pulses. The process can also be done at the slave station if the slave pulse is transmitted to the master and a conjugate-phase master pulse is retransmitted to the slave where the measurement is accomplished. The phase of the slave pulse can then be adjusted by .DELTA./2 to synchronize it with the master pulse.

Abstract: A programmed digital secondary clock which functions as a master clock, a sub-master clock or a slave clock. The master clock maintains an updated real time count based on a 50 hz or 60 hz ac line or digital oscillator signal, displays the count, and serially transmits digital information representative of the updated real time count for use by a slave clock. The sub-master clock, receives an hourly or twice-a-day correction signal from a conventional master clock or a conventional electronic receiver, corrects the real time count, displays the corrected count, and serially transmits digital information representative of the corrected real time count for use by a slave clock. Identical programmed digital secondary clocks can be connected in daisy chain. The first clock can operate as a master clock or as a sub-master clock. The following clocks can be operated as slave clocks.

Abstract: A device for adjustment of an electrical clock with a clockwork train, the latter having an hour pointer driven via an hour gearwheel and via an hour intermediate wheel, a minutes pointer which is driven by means of a minutes gearwheel (the hour intermediate wheel being coupled in clock drive operation with the minutes gearwheel) and a minutes intermediate wheel, as well as having additional gearwheels with a first transmission ratio, the minutes intermediate wheel being coupled with a motor via the additional gearwheels. The minutes gearwheel is decouplable from the minutes intermediate wheel for the coarse adjustment of the minutes pointer and, by means of at least one additional gearwheel with a second transmission ratio which is more direct than the first transmission ratio, the minutes gearwheel is coupleable with the motor.

Abstract: A portable, self-contained, cummulative elapsed time recorder unit for personal use which records and stores data representing time spent by an individual working on each of a number of different work assignments, to provide a time record for billing purposes. The recorder unit includes a counter which is incremented when the unit operates in a timing mode to record a time element representing time spent working on an assignment, and a memory having a plurality of data storage locations, each assigned to a different work assignment for storing the time elements, the data storage locations being individually addressable by manually operable select switches. The recorder unit includes a display unit which provides a numerical display of the data stored at a selected memory location while the unit is operating in the display mode.