Transmitting Time Of Transition And Logic State Patents (Class 370/301)
  • Patent number: 11652809
    Abstract: A secure control system includes a network of multiplexers that control end/field devices of an infrastructure system, such as an electric power grid. The multiplexers have a default secure lockdown state that prevents remote access to data on the multiplexers and prevents modification of software or firmware of the multiplexer. One or more of the multiplexers include a physical authentication device that confirms the physical proximity of a trusted individual when remote access is requested. A user accesses the network and one of the multiplexers remotely by way of login credentials. The trusted individual confirms the identity of the remote user and operates the physical authentication device connected with and in proximity to that multiplexer, thereby confirming that the remote user can be trusted to access data and reconfigure the multiplexers.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: May 16, 2023
    Assignee: HUBBELL INCORPORATED
    Inventors: Michael David Kramarczyk, Emmanuel Duvelson, Robert Walker
  • Patent number: 10616394
    Abstract: A cordless telephone that establishes a call with a telephone of a destination via a base unit includes a controller and a radio unit. The controller modulates control data for controlling radio communication and voice data to be transmitted to the telephone, and stores a modulation control signal of the control data and a modulation voice signal of the voice data in a half slot of a Digital Enhanced Cordless Telecommunications (DECT) system. The radio unit transmits, by radio, the half slot to the base unit.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: April 7, 2020
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hiroyuki Ishihara, Akira Shibuta, Hirokazu Sugiyama
  • Patent number: 10090953
    Abstract: A method of messaging in a communication system that operates in accordance with a standard protocol limited in the number of uniquely addressable remote terminals by a message frame that sequences the messages into a limited number of time slots includes redefining the message frame into a plurality of major frames. Each major frame includes at least one minor frame occupying a unique time slot to address a unique remote terminal. Messages are sequenced into the at least one minor frame. Each minor frame includes a set of time-division multiplexed messages. Each message in the set includes an address field identifying the address of a remote terminal and an additional message to each major frame encoding an output path. The output path encoded in each major frame and the unique time slot in the minor frame determines which remote terminal is addressed by the message.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: October 2, 2018
    Assignee: GE Aviation Systems LLC
    Inventors: Stefano Angelo Mario Lassini, Rusty Jay Benmark
  • Patent number: 9325646
    Abstract: One or more first devices may receive, from a second device, program information as part of a request to provide a contextual message, associated with particular content corresponding to the program information, to a third device. The program information may identify a time, a geographic location, and a television channel identifier associated with the particular content. The one or more devices may cause the particular content to be identified based on a fingerprint of the particular content; receive the contextual message that was identified based on the fingerprint; provide the contextual message to the third device; and provide, for storage in a content schedule, information identifying the particular content, a time period during which the particular content is broadcasted, the geographic location, and the television channel identifier. The content schedule may be used to identify the particular content after the particular content has been initially identified based on the fingerprint.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 26, 2016
    Assignee: VERIZON PATENT AND LICENSING INC.
    Inventors: Shrividhyaa N. Kannan, Syed Mohasin Zaki, Raju T. Ramakrishnan, Karthic Chinnadurai
  • Patent number: 8935371
    Abstract: Methods and apparatus, including computer program products, are provided for controlling the state of components of a system. In one aspect, there is provided a computer-implemented method. The method may include receiving a request to place a system into a state. The system may include one or more components of a distributed computing system. A controller may place, based on a defined structure for the system, the one or more components into the state by sending one or more messages to the one or more components. Related apparatus, systems, methods, and articles are also described.
    Type: Grant
    Filed: February 25, 2008
    Date of Patent: January 13, 2015
    Assignee: SAP SE
    Inventors: Alexander Gebhart, Erol Bozak
  • Patent number: 8635302
    Abstract: In certain embodiments, a device for outputting updated messages a determinate number of times is provided. The device may comprise an output, an input, one or more processors, a memory, code stored in the memory and executed by the processor, wherein at least one message is received from time to time by the device through the input, and wherein the code selects if and when the at least one message is to be provided on the device via the output a determinate number of times. The operation of the enabled device can allow the message to be delivered to the user as the result of some action in regards to enabled device usage.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: January 21, 2014
    Assignee: StratosAudio, Inc.
    Inventors: Kelly M. Christensen, John Phillip Hansen, Thomas Daniel Mock
  • Patent number: 8190722
    Abstract: Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment, it can be determined how long it takes to propagate a signal to each box in the chain. These values are then recorded in each box in a delay register so that each box has a recorded delay value corresponding to the time required to propagate a signal to or receive a signal from every other box. Each box applies a control signal, such as a run signal or a trigger signal, to the ports in the box only after the expiration of the delay value indicated in the delay register. The box initiating the signal has the largest delay since the other boxes need to get the signal before the boxes can begin to operate with a common counter, with successive boxes having smaller delays.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: May 29, 2012
    Inventors: Randy Oyadomari, Arthur Michael Lawson
  • Patent number: 8155580
    Abstract: Methods and apparatus for efficient data distribution to a group of users. In an aspect, a method is provided for distributing information. The method includes detecting one or more requests for the information, determining whether the information is to be broadcast, and transmitting the information in a broadcast transmission based on the determination. In another aspect, an apparatus is provided for distributing information. The apparatus includes a detector configured to detect one or more requests for the information, a determination module configured to determine whether the information is to be broadcast, and a transmitter configured to transmit the information in a broadcast transmission based on the determination.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: April 10, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Mark Maggenti, Eric C. Rosen
  • Patent number: 8134983
    Abstract: A disclosed base station apparatus includes: a TTI-length determining unit which determines, based on downlink receive quality information transmitted from a mobile station, whether data is to be transmitted in a first TTI with, as a unit, a predetermined period no shorter than a subframe length, or in a second TTI with, as a unit, a period shorter than the first TTI; a number-of-subframes determining unit which determines a number of subframes making up the determined TTI; a reporting unit which reports the determined TTI and the number of subframes making up the determined TTI to the mobile station; and a scheduler which performs scheduling based on the determined TTI and the number of subframes making up the determined TTI.
    Type: Grant
    Filed: June 13, 2007
    Date of Patent: March 13, 2012
    Assignee: NTT DoCoMo, Inc.
    Inventors: Atsushi Harada, Minami Ishii, Sadayuki Abeta
  • Patent number: 7813382
    Abstract: A method of synchronizing a network includes transmitting a tone signal to convey time information and setting a local time according to the conveyed time information. The method may also include detecting an occurrence of a predefined aspect of the tone signal, and setting a local time based on the occurrence of the predefined aspect of the signal.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 12, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Arati Manjeshwar, Lakshmi Venkatraman, Bhaskar Srinivasan
  • Patent number: 7729406
    Abstract: Detection of a process state change includes, in each of a number of filters having differing time constants, generating an estimated average process state from observed samples of the process. A number of state change decisions are generated by comparing each of the number of estimated process states with a respective one of a number of threshold values. It is then decided that the process has changed state if any one or more of the state change decisions indicates that the process has changed state.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: June 1, 2010
    Assignee: Ericsson Technology Licensing AB
    Inventor: Stefan Zürbes
  • Patent number: 7573831
    Abstract: The present invention generally relates to a method for analyzing billing packets transmitted from a billing collector to a billing converter. A first packet of data transmitted from a billing collector to a billing converter is received. The first packet includes billing data and a transmission time. A second packet of data being transmitted from the billing converter to the billing collector is received. The second packet includes an acknowledgement of the first packet and a transmission time. A first time difference between the transmission time of the first packet and the transmission time of the second packet is determined.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: August 11, 2009
    Assignee: Sprint Communications Company L.P.
    Inventor: Joel Mark Studtmann
  • Patent number: 7519005
    Abstract: A single-wire serial communications bus has a master device and one or more slave devices. The slave devices are addressed according to a predetermined addressing scheme in an address space. The master device starts a transmission with a number of line state changes which define a clock period to be used by the slave devices in clocking and framing the serial data. This permits omitting a clock line, thus saving a pin and saving printed circuit board space. This also permits the slave devices to shut down their own clocks during periods of inactivity on the bus, thus saving power. Likewise the master device is able to shut down its clock during periods of bus inactivity.
    Type: Grant
    Filed: April 28, 2003
    Date of Patent: April 14, 2009
    Assignee: Semtech Corp.
    Inventors: Carl Hejdeman, Victor Marten, Andrew McKnight
  • Patent number: 7450529
    Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce the signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. Preferably, the destination port is in a first cross link multiplexer, the origin port is in a second cross link multiplexer, and the first cross link multiplexer is configured to convey the signal toward the second cross link multiplexer in more than one direction. In an embodiment, the signal is capable of being represented as a series of characters, and a character is capable of being represented as a number of bits. Preferably, the plurality of cross link multiplexers includes a delay buffer to delay conveyance of a first bit so that it remains substantially synchronized with a second bit.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 11, 2008
    Assignee: Broadcom Corporation
    Inventors: Abbas Amirichimeh, Howard Baumer, Dwight Oda
  • Patent number: 7450530
    Abstract: A cross link multiplexer bus comprising a plurality of cross link multiplexers and a plurality of interconnects. The plurality of cross link multiplexers has a destination port configured to receive a signal and an origin port configured to produce said signal. The plurality of interconnects has a set of interconnects coupled between a pair of adjacent cross link multiplexers. The signal is capable of being represented as a series of characters. A character is capable of being represented as a first data bit, a second data bit, and a control bit. A first interconnect is configured to convey the first data bit. A second interconnect is configured to convey the second data bit. A third interconnect is configured to convey the control bit. The third interconnect is positioned substantially between the first interconnect and the second interconnect.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: November 11, 2008
    Assignee: Broadcom Corporation
    Inventors: Abbas Amirichimeh, Howard Baumer, Dwight Oda
  • Publication number: 20080025237
    Abstract: A multiplex transmission apparatus for multiplexing and transmitting a synchronous signal synchronized with a clock signal and an asynchronous signal asynchronized with a clock signal, the apparatus includes a clock extracting unit that extracts a first clock from the synchronous signal, and a multiplexing unit that multiplexes the synchronous signal and the asynchronous signal into a multiplexed signal to be transmitted in accordance with the first clock.
    Type: Application
    Filed: July 26, 2007
    Publication date: January 31, 2008
    Applicant: NEC CORPORATION
    Inventor: Keiichi YAMADA
  • Patent number: 7106761
    Abstract: Data arriving from a plurality of channels asynchronously to each other are respectively stored in separate FIFOs (10). A controller (12) monitors the status of the FIFOs (10), retrieves the stored data in a predetermined order, and multiplexes the data, together with timing data indicating the presence or absence of the data, into a serial signal having a frame structure in which time slots are fixedly assigned to the respective channels. On the serial data, the same value appears successively as data, and when the data is valid, the corresponding timing data changes from a 0 to a 1. When the data is invalid, the value of the corresponding timing data does not change.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: September 12, 2006
    Assignee: Fujitsu Limited
    Inventors: Kazunari Shiota, Hidetoshi Kawamura, Seiji Miyahara, Isao Takata, Kanji Naito
  • Patent number: 6907090
    Abstract: Methods and corresponding apparatus to recover data from a signal comprising groups of pulses generated in response to analog waveforms are described. Data recovery in accordance with the invention is based on parameters characterizing the groups of pulses. These parameters are the basis for mapping the groups of pulses to information symbols which collectively constitute the data to be recovered.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: June 14, 2005
    Assignee: The National University of Singapore
    Inventor: Guo Ping Zhang
  • Patent number: 6791953
    Abstract: An interface apparatus includes a pulse generating unit which detects the change of reading target data and generates a start pulse, an adjusting unit which generates an adjusting signal that changes from a first signal level to a second signal level in response to the start pulse, a register unit comprising a register which fetches first reading target data synchronously with a clock when the adjusting signal is at the second signal level, and holds the data and outputs the data as second reading target data when the adjusting signal is at the first signal level, and a driver unit which outputs the first reading target data synchronously with the reading signal that is asynchronous with the clock when the adjusting signal is at the second signal level, and outputs the second reading target data synchronously with the reading signal when the adjusting signal is at the first signal level.
    Type: Grant
    Filed: March 6, 2003
    Date of Patent: September 14, 2004
    Assignee: NEC Electronics Corporation
    Inventors: Makoto Ogawa, Tetsuya Hashimoto
  • Patent number: 6463092
    Abstract: The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: October 8, 2002
    Assignee: Silicon Image, Inc.
    Inventors: Gyudong Kim, Min-Kyu Kim, Seung Ho Hwang
  • Patent number: 5987560
    Abstract: A flexible general input/output function utilizes a programmable logic circuit in conjunction with general purpose input/output pins. A programmable logic circuit receives the input signals from the input terminals. The programmable logic circuit program conditions the input signals and provides conditioned input signals to the remainder of the integrated circuit. An input register receives the conditioned input signals from the programmable logic circuit, and stores values representing the state of respective conditioned input signals. A transition detection circuit detects a specified transition for each of the conditioned input signals it receives and provides an indication of the specified transition. An interrupt circuit is responsive to transition indications provided from the transition detection circuit to generate an interrupt signal associated with the specified transition of a respective conditioned input signal.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: November 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Dale E. Gulick
  • Patent number: 5889781
    Abstract: The asynchronous timing generator is comprised of a clock signal generator that generates a master clock signal. The master clock signal is used by a master clock counter to generate a bit clock. The master clock counter divides the master clock signal's frequency down to a lower frequency. Control signal information is extracted from the data stream's slot-framing to control the use of a predefined count value to a variable counter. The variable counter uses this lower frequency clock signal to generate the sub-bit count clock signal and slot bit numbers. These signals are generated in response to the control signals, coupled to the timer, indicating the different fields of the slot used to resynchronize data recovery in the received stream. In a preferred embodiment, the asynchronous timing generator is used in a communications transceiver device to permit resynchronization of received communications data.
    Type: Grant
    Filed: June 11, 1996
    Date of Patent: March 30, 1999
    Assignee: VLSI Technology
    Inventors: Michel Eftimakis, Gianmaria Mazzucchelli