Abstract: A correlation memory section 105 stores a prescribed table in which each control data is grouped for each kind of it (for each message unit) to be correlated to each other. A control data synchronization section 104 successively accumulates input control data into a control data accumulation section 106. At this time, the control data synchronization section 104 refers a table stored in the correlation memory section 105 to correlate a plurality of control data for each group for accumulating the control data. By such operation, a plurality of control data are multiplexed for each group, and the control data are handled by the group as one data. Then, a control data processing section 107 generates multiplexed control data that are multiplexed for each group as one packet, and the control data processing section 107 transmits the generated packet to a communicating party.

Abstract: Disclosed are methods and apparatus for data tapping within a storage area network (SAN) and providing tapped data to a third party device, such as an appliance. In general, mechanisms are provided in a SAN to allow a data tap of data flowing between an initiator and a target. In one implementation, a data virtual target (DVT) in created in a network device to intercept data sent by a specific initiator to a specific logical unit of a specific target. The data or a copy of the data is sent to both the specific logical unit of the specific target and to an appliance. The data routing may be accomplished by use of a virtual initiator (VI), which is configured to send the data (or a copy of the data) to the specific target and the appliance. In a transparent mode of operations, the DVT has a same PWWN (port world wide name) and FCID (fibre channel identifier) as the specific target. In a first proxy mode of operation, the DVT has a different PWWN and FCID than the specific target.

Abstract: Systems, methods, and software products for moving and/or resizing a producer-consumer queue in memory without stopping all activity is provided so that no data is lost or accidentally duplicated during the move. There is a software consumer and a hardware producer, such as a host channel adapter.

Abstract: Tree data structures are stored among and within multiple memory channels, which may be of particular use with, but not limited to tree bitmap data structures. A subtree (or entire tree) typically includes one or more leaf arrays and multiple tree arrays. One or more leaf arrays are typically stored in a first set of memory channels of N+1 sets of memory channels, the N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels. Paths of the multiple tree arrays are typically stored in said N memory channels, wherein each tree array of the multiple tree arrays associated with one of said paths is stored in a different one of said N sets of memory channels.

Abstract: Method, system and program product are provided for packet flow control for a switching node of a data transfer network. The method includes actively managing space allocations in a central queue of a switching node allotted to the ports of the switching node based on the amount of unused space currently available in the central queue and an amount of currently-vacant storage space in a storage device of a port. In a further aspect, the method includes separately tracking unallocated space and vacated allocated space, which had been used to buffer packets received by the ports but were vacated since a previous management update due to a packet being removed from the central queue. Each port is offered vacated space that is currently allocated to that port and a quantity of the currently unallocated space in the central queue to distribute to one or more virtual lanes of the port.

Abstract: Provided is a computer system capable of cutting the cost of running and managing a company network and improving the security of the network by reducing wrong settings and skipped settings due to human factor. The computer system has switches which constitute a network, a management computer which is connected to the network and manages the network, and clients which are connected to the switches. The management computer sets each switch such that client authentication is executed at port provided in the switch that can be connected to the client. The client authentication is processing of verifying whether the client has the right to connect to the network.

Abstract: A communication device configured to assign a data packet to a memory bank of a memory device is provided. The communication device includes an input port for receiving the data packet, a look-ahead logic module, a pointer assignment module, and an output port. The look-ahead logic module is configured to select an address of the memory bank of the memory device by overriding an address mapping scheme that permits successive data packets to be assigned to the same memory bank. The pointer assignment module is configured to assign a pointer to the data packet based upon the memory bank determined by the look-ahead logic module. In addition, the output port is configured to transfer the data packet to the memory bank of the memory device.

Abstract: A method and system for providing a data service in interworking wireless public and private networks, allows for data service data being transmitted through the private network when a data service is to be transmitted through the private network within the network where the wireless public network and the wired/wireless private network are interworked.

Abstract: A communications system may include at least one data storage device for storing messages for respective users, and a plurality of mobile wireless communications devices each associated with a respective user for accessing the messages stored on the at least one data storage device. Moreover, the communications system may further include an adaptive polling engine for polling the at least one data storage device for stored messages and providing the polled messages to mobile wireless communications devices of respective users. The adaptive polling engine may advantageously learn respective user usage patterns for each mobile wireless communications device, and change a respective rate of polling for each mobile wireless communications device based thereon.

Abstract: A communications system may include at least one data storage device for storing messages for respective users, and a plurality of mobile wireless communications devices each associated with a respective user for accessing the messages stored on the at least one data storage device. Moreover, the communications system may further include an adaptive polling engine for polling the at least one data storage device for stored messages and providing the polled messages to mobile wireless communications devices of respective users. The adaptive polling engine may advantageously learn respective user usage patterns for each mobile wireless communications device, and change a respective rate of polling for each mobile wireless communications device based thereon.

Abstract: In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data source generates a first data source signal, a first frame source signal, and a first clock source signal in response to a selected one of the first and second frame reference signals. Similarly, a second data source generates a second data source signal, a second frame source signal, and a second clock source signal in response to a selected one of the first and second frame reference signals. A timing recovery circuit generates a recovered reference signal and a recovered clock signal in response to a selected one of the first and second frame reference signals. A phase aligner stores the first data source signal in response to the first frame source signal and the first clock source signal.

Abstract: In a method of communicating between a communication station (1) and at least one data carrier (2 (DC)) comprising an information data block (IDB) and useful data (UD=N×UDB), an inventorization procedure with successive procedure runs is carried out at least one part of a block region (NKP-IDB) of the identification data block (IDB) not yet known in the communication station (1) and, in addition, specific useful data (n×UDB) are transmitted from each data carrier (2 (DC)) to the communication station (1) in the implementation of the inventorization procedure, such that after termination of the inventorization procedure at least one part of the identification data block (IDB) of each data carrier (2 (DC)) and the associated specific useful data (n×UDB) are known in the communication station (1).

Abstract: A signal router routes N inputs to M outputs. All inputs signals are ultimately applied to a data buss by spreading across multiple buss lines and time multiplexing. The data are read from the buss and written in identical images to K random access memories. The memories are addressed and read according to a different schedule for each of K output signals that are ultimately demultiplexed to M outputs. As each RAM image is read, another RAM image is written and vice versa. Since each RAM image contains the same data, the generation of signals from each RAM to supply each of the respective K output signals can be done at a rate that is substantially more independent of the input, buss, or RAM write operations than prior art techniques permit.

Abstract: A method for managing a content addressable memory (CAM) look-up table using the longest prefix matching (LPM) is provided. The method includes providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers stores the next higher address of data having the highest address in each band of data; and making a space in which data is to be added in the CAM look-up table by moving data having the addresses stored in the pair of pointers provided per each band of data that has a shorter prefix length than the prefix length of the data to be added, when data is added to the CAM look-up table. According to the method, it is possible to easily and efficiently add new data into the look-up table of the CAM.

Abstract: The present invention provides efficient and effective quality of service for information that is time sensitive (e.g., real time data). An intermediate network communication system and method (e.g., a router) of the present invention performs cut through switching to reduce latency problems for time sensitive information. In one embodiment of the present invention, communication packet header information is encoded with a time sensitive identifier that identifies the information as time sensitive. In one exemplary transfer control protocol/internet protocol TCP/IP implementation of the present invention, time sensitive indication is provided in the link layer information. In one embodiment of the present invention, time sensitive information is dropped if the intermediate network device can not communicate the information within specified timing constraints.

Abstract: A method and system for designing a bi-connected ring-based network is provided, which designs from scratch or converts an existing network to a dual-homed ring-based network. The network covers the locations capable of being bi-connected with one or more cycles/rings. The traffic demand is then routed via the cycles, in such a way so as to minimize the amount of network traffic management equipment required.

Abstract: Techniques for efficient storage and retrieval of Preferred Roaming Lists are disclosed. In one aspect, PRL entries are stored in two tables. One table contains records that are common to two or more PRL entries. Another table stores any information that is unique to a PRL entry, as well as an indicator of which common record is associated with it. The common record is concatenated with the unique information to generate the uncompressed PRL entry. Various other aspects of the invention are also presented. These aspects have the benefit of reducing the memory requirements for storing a PRL. In addition, time required to download the compressed PRL is reduced.

Abstract: A switch for a network. The switch comprises a memory mechanism in which portions of packets are stored. The switch comprises a mechanism for instituting changes to the memory mechanism while the memory mechanism continuously operating on packets. A method for switching packets. The method comprises the steps of receiving changes for a memory mechanism of a switch at a buffer of the switch. Then there is the step of implementing the changes to the memory mechanism when the memory mechanism receives an implementation signal while the memory mechanism continuously operates on packets.

Abstract: A signal processor is adapted for aligning two or more hyper-concatenated data streams, each data stream being conveyed within a respective parallel channel and having substantially equivalent bit and frame rates. The signal processor comprises a respective channel processor for each channel for processing a respective data stream. Each channel processor includes a framer, a memory, an interface, and an output timer. The framer generates a local strobe signal indicative of a timing of incoming frames of the respective data stream. The memory buffers incoming bits of the respective data stream. The interface selectively sends the local strobe signal to, and receives a master strobe signal from, an adjacent channel processor. The output timer controls a timing of outgoing bits of the respective data stream based on a selected one of the local and master strobe signals.

Abstract: In a TDMA/TDD transmitter, a control data generation unit receives assignment terms for a number of time slots and slot data from an external source, produces a set of assignment control data according to the assignment terms and the slot data and stores the set of assignment control data into an entry of a control data table in response to a transfer command signal. A sequence controller analyzes sets of assignment control data maintained in the control data generation unit and produces a number of address pointers. The address pointers are stored in an address pointer table in such a sequence that they can be sequentially read out in a desired transmission sequence. The aforesaid transfer command signal is supplied from the sequence controller to the control data generation unit in response to each of the address pointers.

Abstract: An apparatus and method for generating a comparand in a content addressable memory array. The apparatus includes a content addressable memory (CAM) array and translation circuitry to receive translation information indicative of translation of a bit group from an initial position in input data to a different position in a comparand transmitted to the CAM array. The translation circuitry includes a switch circuit, one or more storage elements to store the translation information, and one or more decode circuitry to decode the translation information and establish switch circuit connections between the initial position and the position in the comparand. The apparatus also includes program circuitry to provide a bit level programming interface with the translation circuitry. The apparatus may also include a programming bit register to store programming information in the form of a binary pattern where each bit represents a bit group of the input data.

Abstract: A system for allocating storage resources in a storage area network is described. A logical unit number (LUN) mapper receives at least one storage request parameter and maps the storage request parameters to at least one physical LUN. The LUN mapper includes at least one LUN map. The storage request parameters include a host id parameter, a target LUN parameter, and a target host bus adaptor (HBA) parameter. The LUN mapper uses the host id parameter to select the one of the LUN maps that corresponds to the host id parameter. The LUN mapper applies the target LUN parameter and the target HBA parameter to the selected LUN map to locate the physical LUN(s) stored in the selected LUN map. The LUN mapper issues the received read/write storage request to at least one storage device that houses the physical LUN(s). The one or more storage devices are located in the storage area network.

Abstract: Broadband switching including the implementation of and control over a massive sub-microsecond switching fabric. To effect the attributes of the switching fabric, conditionally nonblocking components are used a building-blocks in an interconnection network which is recursively constructed. The properties of the interconnection network are preserved during each recursion to thereby configure the massive switching fabric from scalable circuitry.

Abstract: A switch switches time division multiplexed (TDM) data and packet data from input ports to output ports. The swich comprises: a plurality of input ports receiving data, wherein each data comprises either TDM data or packet data; a plurality of output ports transmitting switched data; and a shared memory coupling the input ports to the output ports. The shared memory sequentially receives the data from the input ports, and switches a sequentially received data from a respective input port to a respective output port. Switching of packet data by the shared memory has no latency or jitter effect on switching of TDM data by the shared memory.

Abstract: At a master controller of a space switch in a node in a data network, a request is received from a source node that requests a connection to be established through the space switch. This request is compared to other such requests so that a schedule may be established for access to the space switch. The schedule is then sent to the source nodes as well as to a slave controller of the space switch. The source nodes send data bursts which are received at the space switch during a short guard time between successive reconfigurations of the space switch. Data bursts are received at the space switch at a precisely determined instant of time that ensures that the space switch has already reconfigured to provide requested paths for the individual bursts. The scheduling is pipelined and performed in a manner that attempts to reduce mismatch intervals of the occupancy states of input and output ports of the space switch.

Abstract: Techniques for efficient storage and retrieval of Preferred Roaming Lists are disclosed. In one aspect, PRL entries are stored in two tables. One table contains records that are common to two or more PRL entries. Another table stores any information that is unique to a PRL entry, as well as an indicator of which common record is associated with it. The common record is concatenated with the unique information to generate the uncompressed PRL entry. Various other aspects of the invention are also presented. These aspects have the benefit of reducing the memory requirements for storing a PRL. In addition, time required to download the compressed PRL is reduced.

Abstract: A data structure depicting unicast queues comprises a Structure Pointer memory for storing pointers to a location in memory of a segment of a packet associated with a respective queue. A Structure Pointer points to a record in the Structure Pointer memory associated with a successive segment, and a packet indicator indicates whether the segment is a first and/or a last segment in the packet. A Head & Tail memory stores an address in the Structure Pointer memory of the first and last packets in the queue, and a free structure memory points to a next available memory location in the Structure Pointer memory. To support multicast queues the data structure, a multiplicity memory stores the number of destinations to which a respective queue is to be routed. A scheduling method and system using such a data structure are also described.

Abstract: A system for determining an order of service of temporarily stored objects, at least one priority flag being attached to certain objects, includes a set of storage units disposed in a matrix organized into C subsets of elements, where C is the number of objects stored temporarily. Each subset corresponds to an object and all the subsets include the same number P of elements corresponding to P time positions. Each element includes a memory which can receive at least one time priority flag. A first time position selector determines, within the matrix, and from all the subsets, the element(s) marked by a particular time priority flag and corresponding to the time position having the lowest value.

Abstract: A method and apparatus for managing multiple pointers is provided. Each pointer may be associated with a partition in a partitioned memory, such as DDR SDRAM used in a high speed networking environment. The system and method include a free pointer pool FIFO, wherein a predetermined quantity of pointers is allocated to the free pointer pool FIFO. The system selects one pointer from the free pointer pool FIFO when writing data to one partition in the partitioned memory, and provides one pointer to the free pointer pool FIFO when reading data from one partition in the partitioned memory. The system and method enable self balancing using the free pointer pool FIFO and decreases the number of memory accesses required. The system can be located on chip.

Abstract: A method and apparatus for the early termination or deletion of frame data that is being transmitted or is scheduled for transmission from one network station to another network station. A network interface in the transmitting network station is able to read and transmit frame data as a central processing unit in the transmitting network is writing frame data into memory. The network interface reads a descriptor associated with frame data to determine if the frame data, which is either being transmitted or is scheduled for transmission, has a termination field indicating that the frame data is to be deleted. A descriptor management unit in the network interface reads the termination field in the descriptor and determines whether the frame data is currently being sent or is scheduled for transmission. If the frame data is scheduled for transmission, then the frame data is flushed from the data memory of the transmitting network station.

Abstract: One aspect of the present invention provides a method and an apparatus for setting the size of a variable buffer. The method in one embodiment includes setting the initial size of the buffer to zero, reading messages into and out of the buffer, and increasing the average depth of the variable buffer, if underflow occurs. In another embodiment, the method includes repeatedly reading messages and increasing the average depth of the buffer if underflow occurs, until the average depth of the buffer converges to a point to produce a substantially low delay in message transmissions while substantially reducing the possibility of future underflows due to packet delay variation.

Abstract: Pipe regions PIPE0 to PIPEe (or endpoint regions) are allocated in a packet buffer, registers in which are set page sizes MPS0 to MPe (maximum packet size) and numbers of pages BP0 to BPe for the pipe regions are provided, and data is transferred between pipe regions and endpoints, region sizes RS0 to RSe of the pipe regions being set by the page sizes and numbers of pages. The page sizes and numbers of pages are set in registers that are used in common during both host operation and peripheral operation in accordance with the USB on-the-go standard. Transfer condition information such as transfer types TT0 to TTe is set in the registers, transactions with respect to the endpoints are automatically issued, and data is automatically transferred. Pipe regions are allocated in the packet buffer during host operation whereas endpoint regions are allocated during peripheral operation.

Abstract: A switching apparatus incorporated in a time division multiplying system has a read control memory for storing addresses indicative of parts of different messages to be transferred to different channels, and a read controller checks the read control memory so as to determine the memory areas of a message memory for selectively transferring the parts of different messages to the channels, thereby making the memory structure simple.

Abstract: This invention is an implementation of a host channel adapter and method for transferring packet data over a network. When packets are distributed by a packet-switching system, a control unit and a plurality of header buffers allow the packet transmission to be carried out efficiently in executing the actions of reading and moving the packets. This reduces repetitions in reading and moving the packets, which enables the host channel adapter to use the bandwidth of the memory efficiently through the help of the control unit.

Abstract: A system for managing interconnections between connection points of a network element controlled by a management center includes the use of an information model. The management system establishes the information model on the basis of initial data and allowing for limitations in the network element at a given time. It updates the model and communicates the model and its updates to the management center to enable it to set up paths in the network element.

Abstract: An Ethernet switch having a share memory structure in which the share memory reads/writes packet data and records network routing data when switching packet data among network ports. Furthermore, a buffer manager in coordination with a buffer table is provided to manage the memory by a sharing memory method. The Ethernet switch includes a memory device, a memory controller, a data switching controller and more than two network ports. Furthermore, the memory device provides network packets accesses and routing data storage. The memory controller is coupled to the memory device for managing/controlling network packets in the memory device. The data switching controller is coupled to the memory device for selecting/learning packet routings. Each network port is coupled to the memory controller and data switching controller.

Abstract: A format programmable hardware packetizer (110) receives real-time raw input data (125) from a multimedia data source (103) via an analog to digital converter (105) and a data encoder (120) gated by encoder interrupts (127). The real-time raw input data is buffered in an internal byte collector of the packetizer (110). A main CPU interrupt (117) is issued to the main processor (130) when a packet boundary code is received. The packetizer (110) formats the data according to a desired format selected on line (115) for dump to the main memory (140) while providing a managed, much lower level of interrupts to the main processor (130) on the CPU interrupt line (117). A plurality of hardware packetizers (110) can be deployed according to alternative constructions for efficient real time packetizing in various selected formats.

Abstract: A method for managing a content addressable memory (CAM) look-up table using the longest prefix matching (LPM) is provided. The method includes providing a pair of pointers per every band of data having the same prefix in length, wherein one of the pair of pointers stores the address of data having the lowest address in each band of data, and the other pointer of the pair of pointers stores the next higher address of data having the highest address in each band of data; and making a space in which data is to be added in the CAM look-up table by moving data having the addresses stored in the pair of pointers provided per each band of data that has a shorter prefix length than the prefix length of the data to be added, when data is added to the CAM look-up table. According to the method, it is possible to easily and efficiently add new data into the look-up table of the CAM.

Abstract: An off-load engine for processing a packet conveyed between a target and a network over a transport connection, the packet including a payload and a header. The engine includes a payload buffer, for holding data exchanged between the off-load engine, the network, and the target for inclusion in the payload, and a packet processor, for processing context of the transport connection.

Abstract: According to one embodiment, a method is disclosed. The method includes receiving a first identification (ID) at a computer system from a server via a transmission medium, comparing the first ID with a second ID stored at a first analog front end coupled to the computer system, and certifying a first software-defined radio for operation if the first ID matches the second ID.

Abstract: A format programmable hardware packetizer (110) receives real-time raw input data (125) from a multimedia data source (103) via an analog to digital converter (105) and a data encoder (120) gated by encoder interrupts (127). The real-time raw input data is buffered in an internal byte collector of the packetizer (110). A main CPU interrupt (117) is issued to the main processor (130) when a packet boundary code is received. The packetizer (110) formats the data according to a desired format selected on line (115) for dump to the main memory (140) while providing a managed, much lower level of interrupts to the main processor (130) on the CPU interrupt line (117). A plurality of hardware packetizers (110) can be deployed according to alternative constructions for efficient real time packetizing in various selected formats.

Abstract: A crosspoint switch includes a large number of ports and a separate pass transistor linking each possible pair of ports. When a pass transistor is turned on or off, it makes or breaks a signal path between the pair of ports it links. Each port can process signals passing through the port in any one of several operating modes, with a current operating mode being selected by input mode control data. The crosspoint switch also includes a random access memory (RAM) having a separate addressable storage location corresponding to each port. Each RAM storage location stores routing data for controlling the pass transistors connected to a corresponding port and also stores mode control data controlling the mode of the corresponding port. A memory controller responds to a parallel command from a host computer by concurrently writing routing and mode control data to two storage location of the RAM, thereby quickly making and/or breaking a signal path between two ports and selecting the operating mode of both ports.

Abstract: An asynchronous transfer mode (ATM) switch (20) has plural switch ports (24) connected by respective bidirectional links (27, 28) to a switch core (22). Connected to each switch port is a corresponding row column unit (40), each row column unit managing the writing of service cells to one row of cross point units (32) and the reading of service cells from one column of cross point units. The bidirectional links between each switch port and its corresponding row column unit of the switch core carry both service cells and control cells. Cells of differing sizes are carried on the bidirectional links between the switch core and the switch ports. Service cells have a differing cell size than the control cells, and the cell size of the service cells need not necessarily be uniform. Differing types of control cells—link connection control (LCC) cells and link synchronization control (LSC) cells are provided. The link connection control cells (LCC) are used e.g.

Abstract: A transmission apparatus includes an input port part having a plurality of input ports, an output window part having a plurality of buffers, a switch part making connections between the plurality of input ports and the plurality of buffers, a selection control circuit controlling the switch part so that data from the plurality of input ports are stored in buffers that have available areas among the plurality of buffers in accordance with data storage states of the plurality of buffers, and a time division multiplexing part multiplexing the data read from the plurality of buffers in time division multiplexing for transmission.

Abstract: An integrated multiport switch (IMS) having a receive FIFO structure with a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM.

Abstract: A data buffering storage circuit automatically allocates a portion of shared storage area to the direction in which data buffering is required. This scheme allows use of fewer parts on a piece of networking hardware, which in turn lowers the cost, simplifies the design, and uses existing on-board memory in a more efficient manner. In at least one embodiment, a first area is allocated to the buffering of a first port of a network switch, a second memory area is allocated to the buffering of a second port of the network switch, and a third area is shared among the buffering of the first port and the buffering of the second port.

Abstract: At each network node, a packet classification unit makes a judgement to transfer only a packet necessary to be processed by software to a packet processing program processor and transfer other packets directly to a routing processor. Processing history information indicating the process history executed at each network node on a network route is transferred to the other network nodes so that other network nodes can store the processing history information in respective processing history repository table. Each node refers to this table and further transfers only the packet necessary to be processed by software to the packet processing processor.

Abstract: A method, apparatus and system for dynamically routing selected calls through an intelligent switched telephone network are described. The method leverages the resident switching power in the Public Switched Telephone Network by departing from the Advanced Intelligent Network (AIN) call model while adhering to the basic principles of ISUP common channel signaling to introduce new flexibility in call routing. Using the method, calls can be efficiently routed and rerouted through the network. Control of a call can be effected by either the called party or the calling party. The method can be practised using either a virtual switching point (VSP) or an ISTP. The VSP is a physical mode in the signaling plane of the network and a virtual node in the switching plane. Calls are routed to the VSP using dedicated trunk groups which may be loop-back ISUP trunks or inter-switch ISUP trunks. Calls are routed to the dedicated trunk groups using standard routing translation tables and methods.

Abstract: An ATM-switch for high transmission rates is built of primary switch cores. A path for a cell through the switch is determined at the arrival of the cell at the switch and this path is coded as a control word, which is transferred through the switch in parallel to the cell itself. The control word indicates directly how the transfer through each primary element of the switch is to be made. Each primary element must only have two inputs and two outputs. The control word then consists of one bit for every stage of primary switch elements in the switch and this bit indicates directly the output from which the cell is to be forwarded from a considered switch element. The switch cores are constructed of intermediate storage memories, one for each pair of one input and one output, and these intermediate storage memories can have a rather limited capacity for storing only a few cells together with their associated control words.

Abstract: A memory system and management method for optimized dynamic memory allocation are disclosed. A memory manager requests a large area of memory from an operating system, and from the viewpoint of the operating system, that memory is fixed. That fixed memory area is then divided up into an integral number of classes, e.g. by the memory manager. Each memory class includes same-size blocks of memory linked together by pointers. The memory block sizes are different for each class, and the sizes of the different class memory blocks are selected to conform to the CPU and memory access bus hardware (e.g. align with a bus bit width) as well as to accommodate the various sizes of data expected to be processed for a particular application. The memory manager maintains a separate, linked list of unused blocks for each class. Each memory block is zeroed initially and after release by a process previously assigned to it. When a block of memory is assigned to a particular process, a flag is set to indicate that it is in use.