Contention Resolution For Output Patents (Class 370/418)
  • Patent number: 6549532
    Abstract: For allocating radio resources in a time-division multiple access packet mode radio communication system, each remote station stores transmit authorizations for each time slot of a frame in a table. The packets are stored in a plurality of queues in each remote station. The table is duplicated and one table is read during a frame while the other table is being written.
    Type: Grant
    Filed: November 15, 1999
    Date of Patent: April 15, 2003
    Assignee: Alcatel
    Inventor: Marc Dieudonne
  • Publication number: 20030053469
    Abstract: Stations of a communication network have internal queues for accumulating and transmitting data messages over a shared communication channel. Each queue within a station accumulates and transmits data messages that have a different level of priority than those accumulated and transmitted by other internal queues of that station. While preferential access to the shared channel is given to data messages having higher levels of priority, data messages having the same priority are transmitted according to a set of rules common to all of the stations. That is, a queue in one of the stations is configured to delay and/or transmit data messages of a given priority level according to a set of rules that applies identically to the queue of any other station that handles data messages of that same priority level. Transmission opportunities are thus fairly allocated between all queues containing data messages of the same priority level.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 20, 2003
    Inventor: Maarten Menzo Wentink
  • Patent number: 6487213
    Abstract: A hierarchical arbitration method in which requests are grouped, using a logical OR operation for example, and provided to higher levels of the hierarchy. Then, grant signals from higher levels of the hierarchy are either propagated down through each level of the hierarchy where they are used to modify, using a logical AND operation for example, grant signals. Alternatively, grant signals from all higher levels of the hierarchy may be provided to a leaf layer of the hierarchy where they are all used to modify, using a logical AND operation for example, grant signals.
    Type: Grant
    Filed: January 4, 1999
    Date of Patent: November 26, 2002
    Assignee: Polytechnic University
    Inventor: Hung-Hsiang Jonathan Chao
  • Patent number: 6487210
    Abstract: A method and apparatus for a high bandwidth multi-source interconnection using point-to-point buses that may be utilized in a communication switch is presented. In the communication switch, a number of output buffers are included to correspond to the outputs of the switch. Each output receives data from a number of different inputs to the switch. Each output buffer includes a plurality of queuing elements where each queuing element receives data from at least one of the inputs and buffers the data prior to insertion into an output data stream corresponding to the output of the output buffer. The plurality of queuing of elements are intercoupled in a daisy chain configuration such that a daisy chain output of one queuing element is coupled to the daisy chain input of the succeeding queuing element. The daisy chain configuration provides a data path through which a data stream that becomes the output of the output buffer is carried.
    Type: Grant
    Filed: March 24, 1999
    Date of Patent: November 26, 2002
    Assignee: Alcatel Canada Inc.
    Inventors: Mark William Janoska, Albert D. Heller, Henry Chow
  • Patent number: 6473424
    Abstract: Provided are methods, apparatuses and systems for balancing the load of data transmissions through a port aggregation. The methods and apparatuses of the present invention allocate port assignments based on load, that is, the amount of data being forwarded through each port in the group. The load balancing of the present invention is preferably dynamic, that is, packets from a given stream may be forwarded on different ports depending upon each port's current utilization. When a new port is selected to transmit a particular packet stream, it is done so that the packets cannot be forwarded out of order. This is preferably accomplished by ensuring passage of a period of time sufficient to allow all packets of a given stream to be forwarded by a port before a different port is allocated to transmit packets of the same stream. The invention may be used in a variety of different network environments and speeds, including 10Base-T, 100Base-T, and Gigabit Ethernet, and other network environments.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: October 29, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: Gregory L. DeJager, James R. Rivers, David H. Yen, Stewart Findlater, Scott A. Emery
  • Patent number: 6456620
    Abstract: Disclosed is a method for all-to-all personalized exchange for a class of multistage interconnecting networks (MINs). The method is based on a Latin square matrix corresponding to a set of admissible permutations of a multistage interconnecting network. Disclosed are first and second methods for constructing a Latin square matrix used in the personalized exchange technique. Also disclosed is a generic method for decomposing all-to-all personalized exchange patterns into admissible permutations to form the Latin square matrix for self-routing networks which are a subclass of the MINs.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: September 24, 2002
    Assignees: Verizon Laboratories Inc., The University of Vermont
    Inventors: Jianchao Wang, Yuanyuan Yang
  • Patent number: 6414766
    Abstract: An ATM switching matrix has input ports, output ports and a passive optical core consisting of optical couplers. Each output port includes at least p optical receivers which are tuned to the same fixed wavelength which is specific to the output port. Each receiver has an input respectively connected to a port of one of the p couplers, a buffer having p inputs respectively connected to the outputs of the p receivers and an output connected to an output of the matrix. The matrix includes distributed allocation arrangements which control switching arrangements of each input port to connect, to k separate couplers, k respective input ports which at the time concerned are receiving k cells addressed to the same output port, k being less than or equal to p, and this operation being repeated for each output port.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: July 2, 2002
    Assignee: Alcatel
    Inventors: Paul Vinel, Pierre Parmentier
  • Patent number: 6396843
    Abstract: The total implementation complexity of packet schedulers which aim at approximating the Generalized Processor Sharing (GPS) policy is the combination of the complexity of their system-potential function and the complexity involved in sorting the timestamps in order to select the packet with minimum timestamp for transmission. Given that several scheduling algorithms which use a system-potential function of O(1) complexity have been introduced (among them, the Minimum-Delay Self-Clocked Fair Queuing (MD-SCFQ) algorithm achieves optimal delay and excellent fairness properties), the major contribution to the total complexity comes from the task of sorting the timestamps every time a packet is transmitted or received, which is common to all GPS-related schedulers.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: May 28, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Fabio Massimo Chiussi, Andrea Francini, Joseph George Kneuer
  • Patent number: 6388993
    Abstract: An ATM switch having the buffer threshold controller to control the cell input into the switching element using the back-pressure signal and a method for determining the buffer threshold according to the buffer threshold controller are disclosed. The ATM switch includes buffer pool storing the cell input to the switch; buffer pool control part storing the buffer pool occupancy information per input port of the buffer pool; threshold control part receiving the buffer pool occupancy information from the buffer pool control part and calculating the threshold per input port periodically and then sending it to the buffer pool control part; input crosspoint control part controlling the cells input to the buffer pool by receiving the control signal from the buffer pool control part; and output crosspoint control part controlling the cells output from the buffer pool by receiving the control signal from the buffer pool control part.
    Type: Grant
    Filed: June 11, 1998
    Date of Patent: May 14, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Jin Shin, Kyung-Geun Lee, Dan-Keun Sung, Jeong-Won Heo, Sung-Hyuk Byun, Ju-Yong Lee, Jin-Woo Yang
  • Patent number: 6377998
    Abstract: An improved frame processing apparatus for a network that supports high speed frame processing is disclosed. The frame processing apparatus uses a combination of fixed hardware and programmable hardware to implement network processing, including frame processing and media access control (MAC) processing. Although generally applicable to frame processing for networks, the improved frame processing apparatus is particular suited for token-ring networks and ethernet networks. The invention can be implemented in numerous ways, including as an apparatus, an integrated circuit and network equipment.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: April 23, 2002
    Assignee: Nortel Networks Limited
    Inventors: Michael Noll, Michael Clarke, Mark Smallwood
  • Patent number: 6370112
    Abstract: In a connection-oriented packet switching network, different paths through the network from one point to another are likely to have different delay. The invention is a method and network architecture for rerouting data packets from one path to another path without loss, duplication, or mis-ordering of the packets (or cells) despite unpredictable differences in delay incurred by packets on the replacement path relative to packets on the original path. The invention uses a marker cell, which is either transmitted along one path or along both paths. At the downstream convergence of the original and replacement path, all pre-marker data packets arriving on the original path are first transmitted and then all post-marker data packets on the replacement path are transmitted. Proper use of the marker provides a means for ensuring that the data packets will be delivered in the proper order, despite the order in which the data packets are received over the original path and the replacement path.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: April 9, 2002
    Assignee: Lucent Technologies Inc.
    Inventor: John Alvan Voelker
  • Publication number: 20020018482
    Abstract: A switching matrix comprises an input stage for assigning incoming data to a connection, a memory element having a plurality of FIFO's which are each time assigned to a connection to buffer-store the incoming data, an output stage to emit the data buffer-stored in the FIFO's, and a control unit. The control unit is set up to define a sub-area of the memory element as a FIFO and to assign it to a transmission connection extending across the switching matrix.
    Type: Application
    Filed: May 7, 2001
    Publication date: February 14, 2002
    Inventor: Martin Gotzer
  • Publication number: 20010040891
    Abstract: In respective leaf tables (LT(1) to LT(m)) of a coupling management table (20), there are provided delete operation identifiers (D(1) to D(m)) indicating that leaf queues (LQ) respectively next to them toward the upstream direction are under delete operation. When one of the leaf queues (LQ(n)) should be deleted, if the leaf queue (LQ(n)) to be deleted stores any element, the delete operation identifier (D(n+1)) is set to 1. Thereby, the leaf table (LT(n−1)) can acknowledge that the leaf queue (LQ(n)) is currently under delete operation. Therefore, the coupled packet queue after deletion of the leaf queue and the coupling management table can be maintained consistent.
    Type: Application
    Filed: December 26, 2000
    Publication date: November 15, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Jun Hasegawa, Toshitada Saito, Yoshimitsu Shimojo
  • Patent number: 6307834
    Abstract: In a transmission system in which redundant message cells are forwarded via redundant transmission paths according to the Asynchronous Transfer Mode, a transmission path is blocked after the occurrence of a small number of errors in the sequence of the transmitted message cells, while for an admission of a transmission path a large number of successive message cells without error in the sequence is required.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: October 23, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventor: Thomas Worster
  • Patent number: 6307852
    Abstract: Several rotator switch architectures are provided that enhance performance of a basic rotator switch. The rotator switches having double buffered tandem nodes, multiplexing two or more sources onto each tandem node, partitioning the rotator into two or more parallel space switches, two or more rotator planes multiplexing front/to source and destination nodes to provide data path redundancy, priority queueing on source nodes scheduled locally or globally, or redundancy in the schedulers are shown.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: October 23, 2001
    Assignee: Nortel Networks Limited
    Inventors: David Anthony Fisher, Michel Langevin
  • Publication number: 20010021174
    Abstract: A switching device comprising several input ports and several output ports, whereby each of the input ports is connectable to a corresponding switch adapter. At least one switch controller controls the routing of incoming data packets from the input ports to the output ports. For each output port a congestion controller is arranged which in operation, generates grant information which signals whether the switch adapters are allowed to send the data packet to the output port. For each of the input ports a data packet access controller marks a data packet as non-compliant if the packet was erroneously sent from said output port.
    Type: Application
    Filed: March 5, 2001
    Publication date: September 13, 2001
    Applicant: International Business Machines Corporation
    Inventors: Ronald P. Luijten, Michel Colmant
  • Patent number: 6282197
    Abstract: Disclosed is an ATM switching apparatus capable of reducing a probability an IAM acceptance being rejected due to a difference in bandwidth acquiring algorithm. The ATM switching apparatus is constructed such that when receiving an IAR due to the difference in bandwidth calculation algorithm for the IAM indicating a use of a certain VPC, a calculated bandwidth value is set in an estimated free bandwidth value about the VPC within a bandwidth management table, a value given by Calculation Bandwidth Value/Free bandwidth Value is set in a ratio, and the VPC is selected by using not the free bandwidth value but the estimated free bandwidth value (=Free Bandwidth Value×Ratio) when transmitting the IAM. It is another contrivance that when the free bandwidth value changes, the estimated free bandwidth value is also changed to establish “Estimated Free Bandwidth Value=Free Bandwidth Value×Ratio” without changing the ratio.
    Type: Grant
    Filed: January 26, 1998
    Date of Patent: August 28, 2001
    Assignee: Fujitsu Limited
    Inventors: Satoshi Takahashi, Yoshihiro Watanabe, Kohei Ueki
  • Patent number: 6262986
    Abstract: A packet scheduling scheme capable of realizing a fair scheduling regardless of weights of connections. A packet scheduler has a plurality of packet queues for temporarily storing entered packets, to each of which a weight is set up; a packet input unit for entering packets into the packet queues; a scheduling information management unit for managing scheduling information for specifying an order to read out packets stored in the packet queues, according to a queue length of each packet queue and the weight set up for each packet queue; and a packet output unit for reading out and outputting desired packets from the packet queues according to the scheduling information.
    Type: Grant
    Filed: July 8, 1996
    Date of Patent: July 17, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Oba, Tsuguhiro Hirose
  • Patent number: 6247058
    Abstract: A network device receives packets from a first network segment, time stamps the packets as they arrive, and transmits the packets to a second network segment. By time stamping packets as they arrive, stale packets can be identified and discarded. A stale packet is a packet that has been pending in the network device longer than an active timeout interval, which may be varied based on network traffic levels to conserve network bandwidth. Packets may also be discarded to conserve packet buffer memory in the network device. For example, when an incoming packet arrives and an output buffer in which the packet must be stored is full, the output buffer is scanned to identify and discard packets that have exceeded a minimum timeout interval, thereby allowing the incoming packet to be stored in the output buffer. Many network protocols initiate the retransmission of packets after a timeout interval has expired and an acknowledge packet has not been received.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: June 12, 2001
    Assignee: Hewlett-Packard Company
    Inventors: John P. Miller, Erik E. Erlandson
  • Patent number: 6233239
    Abstract: A package for communication equipment has a housing fitted with a locking mechanism and electrical/communication power supply and distribution, and includes UP, DOWN, RIGHT, LEFT faces for assembly with other housings. The locking mechanism includes a rotatable axle penetrating the housing and having a first end located outside of the housing and a second end located inside of the housing. A camming hook having a distal end is mounted on the rotatable axle inside the housing to rotate with the axle and locks into position when rotated in a first direction, to bring a movable electrical contact to make resilient electrical contact with a stationary live contact. When the rotatable axle is rotated in a direction opposite to the first direction, the mechanism becomes unlocked and breaks the electrical connection at the movable electrical contact.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: May 15, 2001
    Assignee: Cisco Systems, Inc.
    Inventors: Alain Benayoun, Jean-Francois Le Pennec, Patrick Michel, Patrick Cavallo
  • Patent number: 6229789
    Abstract: An ATM routing switch has a plurality of output ports for handling digital signal cells on a first type requiring integrity of cell transmission and a second type accepting some loss of cells in transmission, the output ports having control circuitry to provide a plurality of queues of cells at each output port, each queue comprising only cells of a single type while each port outputs a mixture of cells of both types on a common output path flow control indicators on incoming cells being used to inhibit output of cells along any path to a destination for which a flow control indicator has indicated congestion.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: May 8, 2001
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Robert Simpson, Neil Richards, Peter Thompson, Pascal Moniot, Marcello Coppola, Pierre Dumas, Thierry Grenot, David Mouen Makoua
  • Patent number: 6198725
    Abstract: A system for allocating resources at network elements along a path through a communications network. Resources are allocated at a network element along the path in response to a connection request message. The delay budget is the minimum of a calculated cell transfer delay and a calculated cell delay variation. The calculated cell transfer delay is determined by finding a difference between a target end to end cell delay and an accumulated cell delay, and then dividing that difference by a number of network elements remaining in the path between the network element and the end of the path. To determine the calculated cell delay variation, the network element first finds a difference between the Max CDV QoS parameter and the sum of the accumulated cell delay variation and the switching delay for the network element. The calculated cell delay variation is then equal to that difference divided by the number of network elements remaining in the path between the network element and the end of the path.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: March 6, 2001
    Assignee: Fujitsu Network Communications, Inc.
    Inventors: Robert Constantin, David E. Hammond, David N. Peck, Salma Abu-Ayyash, Stephen R. Veit, Thomas A. Manning
  • Patent number: 6198558
    Abstract: An improved access system for use in a Fiber-In-The-Loop (FITL) communications network is disclosed. The access system comprises a host digital terminal (HDT) and a plurality of subtending optical network units (ONUs). The digital signal processing (DSP) functions traditionally executed by line interface units (LIUs) within the ONUs are migrated to the HDT, rendering the individual ONUs simpler, cheaper and more reliable. This is made possible by the provision in each ONU of an oversampling codec for sampling (and conversion) of upstream and downstream data at a very high bit rate. The large bandwidths of the data communicated between the ONUs and the HDT are easily handled by the fiber optic medium therebetween. In the HDT, DSP functions are executed by a common pool, or bank, of DSP ASICs. Decimators are provided in the HDT in order to properly format the data for processing by the DSPs.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: March 6, 2001
    Assignee: Nortel Networks Limited
    Inventors: Alan Frank Graves, Todd Douglas Morris, Donald Russell Ellis
  • Patent number: 6192029
    Abstract: A data communications system includes a server router (102), such as an access controller gateway, operably coupled to at least one client router (104), such as a base radio controller, by an asynchronous link, such as a LAN (106). The client router forwards data received from the server router and stored in the client router's outbound queue (110) synchronously to a device, such as a mobile station (202). The client router's outbound queue is maintained between a lower queue limit and an upper queue limit so as to both reduce the occurrence of data starvation and reduce the amount of data lost should the mobile station hand off to a new serving site. The server router calculates an optimum average send rate and transmits data in bursts at regular intervals, and adjusts the average send rate in response to changes in the outbound rate of the client router.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: February 20, 2001
    Assignee: Motorola, Inc.
    Inventors: Rod Averbuch, Jeff Blanchette, Richard Van Egeren, Todd A. Leigh
  • Patent number: 6188690
    Abstract: Methods and devices useful in high-speed scalable switching systems include a memoryless switch fabric, per virtual channel queuing, digital phase aligners, randomized and complement connection modes, a mid-point negative acknowledge and output negative acknowledge scheme among other elements. A particular implementation of a routing table and switch element is described in part to illustrate the various techniques and devices of the invention.
    Type: Grant
    Filed: December 11, 1997
    Date of Patent: February 13, 2001
    Assignee: PMC-Sierra, Inc.
    Inventors: Brain D. Holden, Brian D. Alleyne, Darren S. Braun, Kevin Reno, Chee Hu, Raghavan Menon, Steve Sprouse
  • Patent number: 6185222
    Abstract: In a network switch node, an asymmetric switch. The asymmetric switch comprises a plurality N of inputs each for coupling to a corresponding one of a plurality N of port modules and a plurality M of outputs each for coupling to one of the plurality of port modules. M is greater than N such that at least one of the plurality of port modules is coupled to more outputs than inputs. The asymmetric switch also includes a switching fabric operative to switch packets received from the inputs to the outputs. According to one embodiment, M=kN such that each port module can have one input line to the asymmetric switch and k output lines from the asymmetric switch. Such an asymmetric switch-to-port interface results in less blocking and allows output buffering wherein the output buffers are provided at the ports, rather than at the switch.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: February 6, 2001
    Assignee: Cisco Technology, Inc.
    Inventor: David A. Hughes
  • Patent number: 6185211
    Abstract: To realize an ATM cell switch capable of reducing the transmission rate of cells to be transmitted, a output buffer-type ATM cell switch includes input units buffer unit, and output units, wherein the buffer units reduce the transmission rate of the cells. Furthermore, the ATM switch compares the destinations of the cells with destination set signals that are provided to address filter units in the buffer units, and controls the transfer of cells to the buffer memories in the buffer units, thereby efficiently reducing the transmission rate of cells.
    Type: Grant
    Filed: December 16, 1997
    Date of Patent: February 6, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kenichi Nagatomo, Masami Hagio
  • Patent number: 6178235
    Abstract: Telecommunications traffic is dynamically distributed at a telecommunications node among plural telecommunication routes. A current distribution of traffic is detected for both incoming routes and outgoing routes. Traffic is automatically redistributed among the outgoing routes based on the distribution currently detected for the corresponding incoming routes. More specifically, the detected amount of incoming traffic for a particular network operator, carrier, route bundles, or route is compared with the amount of outgoing traffic detected for a corresponding network operator, carrier, route bundle, or route at the switching point. Traffic is rerouted, in one example embodiment, so that each outgoing network operator, carrier, route bundle, or route receives its “fair” share of traffic based on how much traffic it is currently delivering to the node.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: January 23, 2001
    Assignee: Telefonaktiebolaget LM Ericsson
    Inventors: Ren{acute over (e)} Petersen, Tommy M. Petersen
  • Patent number: 6144640
    Abstract: An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: November 7, 2000
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Robert Simpson, Neil Richards, Peter Thompson, Pascal Moniot, Marcello Coppola, Pierre Dumas, Thierry Grenot, David Mouen Makoua
  • Patent number: 6122252
    Abstract: Cells are discarded in conformity with the order of priority when congestion occurs by discarding cells of a traffic class without any special contract for a transfer rate at the time of setting up a connection. A node stores priority information concerning cell discard corresponding to a connection identifier and controls the cell discard in accordance with the discard condition determined by the accumulated number of cells for each connection in the node and cell priority.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: September 19, 2000
    Assignees: Hitachi, Ltd., Hitachi Information Technology Co., Ltd.
    Inventors: Takeshi Aimoto, Takeki Yazaki, Yoshihiko Sakata, Nobuhito Matsuyama
  • Patent number: 6101193
    Abstract: A packet scheduling scheme which is capable of improving the fairness characteristic in a short time scale by suppressing the burstiness of traffic compared with the conventional weight fair queueing algorithm such as DRR. Packets are held in a plurality of packet queues by inputting arrived packets into the packet queues. Then, an output packet queue is sequentially selected from the packet queues, according to a prescribed criterion based on an amount of packets currently transmittable by each packet queue, such that the output packet queue is selected to be different from a previously selected output packet queue when there are more than one packet queues that satisfy the prescribed criterion. Then, a top packet is outputted from the sequentially selected output packet queue.
    Type: Grant
    Filed: September 10, 1997
    Date of Patent: August 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshihiro Ohba
  • Patent number: 6092108
    Abstract: A multiported device is provided connected to a switching device providing switching functions. The multiported device receives frames and is connected to an application processor. Some of the received frames are passed to the application processor via an application processor port having a port bandwidth. The multiported device includes an application receive buffer having a receive buffer size for storing frames and providing frames to the application processor for processing. A programmable logic unit is provided for monitoring a level of data in the receive buffer and monitoring a type of frame forwarded to said application processor. The frames each have a discriptor frame associated with it with data indicating one or more of priority status and broadcast/unicast status. The logic unit monitors the level of data based on at least one threshold level for dropping frames upon a data level in said receive buffer reaching the threshold level which have a status.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: July 18, 2000
    Inventors: Bruno DiPlacido, Lawrence A. Boxer
  • Patent number: 6081505
    Abstract: A system and method for managing elements of information at a network node received from a user access node. An access node includes a user/network interface (UNI), and a core network node includes a cell filtering unit. The UNI includes a measuring unit, which measures the actual momentary bit rate of a connection between the UNI and the core node, and a priority level computing unit, which computes the priority level of each cell using the measured bit rate and an established nominal bit rate (NBR). NBR represents an expected, but not guaranteed, bit rate associated with a particular user or connection. The connection may be a real-time or a non-real-time connection. A scheduling unit of a node accepts or discards an arriving cell based on the occupancy of a real-time buffer and a non-real-time buffer provided at the node.
    Type: Grant
    Filed: March 20, 1997
    Date of Patent: June 27, 2000
    Assignee: Nokia Telecommunications, OY
    Inventor: Matti Kalevi Kilkki
  • Patent number: 6067301
    Abstract: A method and apparatus for forwarding packets from contending queues of a multiport switch to an output of a finite bandwidth involve first prioritizing the contending queues into different priorities that relate to priorities of the packets that are being forwarded in the network. Bandwidth of the output is then allocated among the prioritized contending queues and the bandwidth of the output is consumed by the queued packets according to the allocated proportions. Any unconsumed bandwidth is distributed to the queues on a priority basis such that the highest priority queue is offered the unconsumed bandwidth first and lower priority queues are offered the remaining unconsumed bandwidth in priority order. An advantage of the invention is that queues are not starved of bandwidth by higher priority queues and unconsumed bandwidth is not wasted when there are not enough packets to consume an allocated portion of the output bandwidth.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: May 23, 2000
    Assignee: Cabletron Systems, Inc.
    Inventor: Deepak J. Aatresh
  • Patent number: 6026089
    Abstract: A package for a communication equipment fitted with mechanical locking mechanism and electrical and communication connectivity for allowing power supply distribution as well as communication at least at four distinctive faces (UP, DOWN, RIGHT, LEFT). Each communicating face is fitted with optical transmission and reception devices allowing digital communication between adjacent apparatuses. Each package comprises two faces having each one protrusion at one surface that is intended to enter into a groove machined at a corresponding surface of the next adjacent package in said structure. Each protrusion comprises a locking mechanism for power supply that comprises a camming hook (2200) having a distal end which forceably engages a locking aperture (2210) when pivoted. The hook is pivotally coupled to an axel (2101) extending respectfully through an elongated aperture (2301) formed at one end of a lever arm (2300), and an elongated aperture (2302) of the hook.
    Type: Grant
    Filed: December 20, 1996
    Date of Patent: February 15, 2000
    Assignee: International Business Machines Corporation
    Inventors: Alain Benayoun, Jean-Francois Le Pennec, Patrick Michel, Patrick Cavallo
  • Patent number: 6021132
    Abstract: A method and apparatus for shared memory management in a switched network element is provided. According to one aspect of the present invention, a shared memory manager for a packet forwarding device includes a pointer memory having stored therein information regarding buffer usage (e.g., usage counts) for each of a number of buffers in a shared memory. An encoder is coupled to the pointer memory for generating an output which indicates a set of buffers that contains a free buffer. The shared memory manager further includes a pointer generator that is coupled to the encoder for locating a free buffer in the set of buffers. The pointer generator is further configured to produce a pointer to the free buffer based upon the output of the encoder and the free buffer's location within the set of buffers.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: February 1, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Shimon Muller, Ariel Hendel, Ravi Tangirala, Curt Berg
  • Patent number: 6009078
    Abstract: In an ATM switch device having a plurality of input ports and a plurality of output ports, a port buffer is arranged for each of the output ports and is given a minimum guaranteed value which represents the minimum number of output cells sent to each output port even when traffic congestion takes place at the other output ports. A total queue monitoring buffer is also arranged to monitor a total number of output cells which is equal to a total sum of the minimum guaranteed values determined for the respective output ports and is counted up only when the counts of the port buffers exceed the minimum guaranteed values. With this structure, it is possible to detect traffic congestion all over the ATM switch device by the total queue monitoring buffer and to assure delivery of the output cells equal to the minimum guaranteed value. Each minimum guaranteed value may be determined for each service class and a multicast cell.
    Type: Grant
    Filed: February 7, 1997
    Date of Patent: December 28, 1999
    Assignee: NEC Corporation
    Inventor: Noboru Sato
  • Patent number: 5987008
    Abstract: An ATM routing switch for bidirectional transmission of digital signal cells some requiring integrity of transmission while others accept some loss of cells in transmission, has a plurality of output ports each handling a plurality of cell queues and control circuitry for decoding control bits in each input cell to determine which output port is to be used, which queue is required and whether flow congestions exists at the source of the input cell.
    Type: Grant
    Filed: August 28, 1997
    Date of Patent: November 16, 1999
    Assignee: SGS-Thomson Microelectronics Limited
    Inventors: Robert Simpson, Neil Richards, Peter Thompson, Pascal Moniot, Marcello Coppola, Pierre Dumas, Thierry Grenot, David Mouen Makoua
  • Patent number: 5818839
    Abstract: Data traffic such as cell streams in an ATM communication network frequently contain data destined for multiple output ports having different transmission data rates. In order to accurately schedule such traffic a clocking signal unique to each output data rate is required. This invention provides systems and methods for generating the necessary clock signals utilizing a single timing reference.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: October 6, 1998
    Assignee: Newbridge Networks Corporation
    Inventors: Jason T. Sterne, David W. Carr, Joey M. W. Chow
  • Patent number: 5818815
    Abstract: A method and an apparatus for shaping the output traffic in the transmit part of a network node adapter. The network node supports fixed length cell switching user information traffic between a source unit and a destination unit. The method and apparatus use two lookup tables called an active and a standby calendar per output line. Each entry in the calendars represents the position of one cell in the output cell stream. Three parameters tables are used to store the information on user traffic in the descending order of the user bandwidth share negotiated at traffic establishment time for the calendars. The active calendar is continuously read by a transmit device and the corresponding cells are sent onto the output line. Under control of a control device, a placement device places entries in the standby calendar reserved as changes occur in the traffic. Once filled up, the standby calendar is swapped to the active calendar and is read by the transmit device.
    Type: Grant
    Filed: September 19, 1995
    Date of Patent: October 6, 1998
    Assignee: International Business Machines Corporation
    Inventors: Regis Carpentier, Rene Glaise, Francois Kermarec, Thanh Pham
  • Patent number: 5796719
    Abstract: The present invention relates to the issue of providing end-to-end delay guarantees in a multi-node communication system. More specifically, the present invention addresses the problem of specifying operational parameters of rate-controlled service disciplines in a communication network in order to efficiently provide end-to-end delay guarantees. The key contribution is a method for specifying leaky bucket parameters as well as scheduling delays at each node, which are used as inputs to the rate-controlled service discipline.
    Type: Grant
    Filed: June 6, 1996
    Date of Patent: August 18, 1998
    Assignee: International Business Corporation
    Inventors: Vinod Gerard John Peris, Leonidas Georgiadis, Roch Andre Guerin, Subir Varma
  • Patent number: 5771234
    Abstract: A method and system are disclosed for scheduling the assignment and writing of cells from cell sources into a outgoing bitstream transmitted from each device of an ATM communications network. The timeslots are organized into fixed length cycles which cycles each have a sequence of N timeslots, where N is an integer >1. Furthermore, each cycle is divided into at least one round comprising a variable length subsequence of the timeslots of the cycle. During each timeslot of a uniform timeslot clock, at least one subset of the sources is identified. Each subset corresponds to a round. One cell from each subset is assigned to, and written into, a respective timeslot of the corresponding round. During each timeslot of the timeslot clock, each of the sources is assigned a priority state depending on how many cells of that source have been previously assigned to timeslots during the current cycle and whether or not that source has a cell available for assignment to a round during that timeslot.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: June 23, 1998
    Assignee: Industrial Technology Research Institute
    Inventors: Chiung-Shien Wu, Gin-Kou Ma
  • Patent number: 5768350
    Abstract: An improved communication system which allows data, voice, and/or other non-real-time and real-time data streams to be transferred from one station to another over a single telephone line with optimal use of the available bandwidth and with a transparency to data transferring processes such as in computer systems coupled to the station interface devices is disclosed. A local data+voice interface device accepts digital data at a data port, analog voice signals at a voice port, digitizes the voice signals, compresses them, packetizes both the digital data and the digital voice data, identifying for each packet the type of data contained therein, and transmits the packets to a remote data+voice interface device, which separates the packets by their identification, and reconstructs the separate voice and data streams.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: June 16, 1998
    Assignee: Phylon Communications, Inc.
    Inventor: Ganesan Venkatakrishnan
  • Patent number: 5761203
    Abstract: A system and method for frequency recovery that allows selection between either a synchronous recovery scheme or asynchronous recovery. A frequency recovery system for synchronizing a received data stream, comprising: a first timing signal generator configured to receive the data stream, extract any timing information included in the data stream, and output a first timing signal based on the extracted timing information;a clock source for providing a second timing signal; a data module for receiving the data stream and outputting the data stream at a desired rate, the data module utilizing either the first timing signal or the second timing signal to output the data at the desired rate; and a switch for selectively applying either the first timing signal or the second timing signal to the data module.
    Type: Grant
    Filed: April 4, 1996
    Date of Patent: June 2, 1998
    Assignee: Lucent Technologies Inc.
    Inventor: Luis E. Morales
  • Patent number: 5757771
    Abstract: A buffer management system and method for use in an ATM switch that allows for data processing of variable bit rate (VBR) and constant bit rate (CBR) traffic using a common buffer memory. The buffer memory is broken down into data sub-queues, each of which is assigned an output and purge priority. ATM cells are allocated to a particular data sub-queue by matching the desired quality-of-service of the cells with the output and purge characteristics of each sub-queue. The system and method dynamically sizes the data sub-queues so as to be equal to the number of ATM cells in the data sub-queue. In addition, age and size ratio thresholds may be assigned to each data sub-queue to better distribute available bandwidth among the sub-queues, and to ensure that cells are not excessively delayed.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: May 26, 1998
    Assignee: Yurie Systems, Inc.
    Inventors: Kwok-Leung Li, Yung-Lung Ho
  • Patent number: 5734650
    Abstract: An apparatus for queuing and scheduling ATM cells across an ATM switch comprises sustainable cell rate calendar connected in series with a peak cell rate calendar wherein cells are scheduled independently in each. The sustainable cell rate calendar guarantees the maximum ATM cell delay is not exceeded. The ATM cells are not placed on the peak cell rate calendar unless the peak cell rate threshold might be exceeded. In this case the cell is scheduled on the peak cell rate calendar and it is this that determines when the cell is sent. In this way, it is possible to guarantee absolute minimum and maximum cell rates of a connection.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: March 31, 1998
    Assignee: Roke Manor Research Limited
    Inventors: Andrew Timothy Hayter, Simon Paul Davis, Paul Parshee Momtaham
  • Patent number: 5732087
    Abstract: A switch for digital communication networks includes a queuing system cape of implementing a broad class of scheduling algorithms for many different applications and purposes, with the queuing system including both a tag-based primary queue which contain ATM cells organized by priority and a secondary queue which contains ATM cells which are not yet scheduled for transmission and which are organized by virtual channel. A queuing decision module is provided to determine in which queue an incoming ATM cell should be deposited. A requeuing module operates when an event occurs that unblocks a particular virtual channel. The requeuing module, on occurrence of such an event, accesses the secondary queue to obtain another cell, to assign it priority and to move it to the primary queue. The queuing decision module, along with a virtual channel table, can be used easily to block virtual channels when necessary. The combination of queues also allows for round robin scheduling.
    Type: Grant
    Filed: May 10, 1996
    Date of Patent: March 24, 1998
    Assignee: Mitsubishi Electric Information Technology Center America, Inc.
    Inventors: Hugh C. Lauer, Abhijit Ghosh, John H. Howard, Harufusa Kondoh, Randy B. Osborne, Chia Shen, Qin Zheng
  • Patent number: 5724358
    Abstract: A system and method for communicating multiple priority level data packets between input ports and output ports of a switch is disclosed where the data packet has a header portion identifying at least one output port destination and a level of priority, selected from a predetermined set of priority levels, of the data within the data packet. A buffer, shared by the output ports, stores the data packet in a selected buffer location based on the output port destination and priority level of the data packet. Pointers to buffer locations containing data packets having a particular priority level are stored in one or more priority sub-queues for one or more of the plurality of output ports based on the output port destinations and the priority level of the data packet. The data packets are output to the output ports in priority order.
    Type: Grant
    Filed: February 23, 1996
    Date of Patent: March 3, 1998
    Assignee: Zeitnet, Inc.
    Inventors: Kent H. Headrick, Kannan Devarajan
  • Patent number: 5712851
    Abstract: An apparatus an method for adaptive time slot scheduling of communications traffic generated by end-point host in ATM network. The scheduler includes a time slot ring including an array of time slots, wherein each of said time slots includes a virtual channel identifier (VCID) of a virtual channel (VC) to be serviced; a VC table including an array of VC descriptors, wherein the VCID stored in said time slot ring points to a VC descriptor in the VC table; and processor for scheduling the VCs in said time slots of said time slot ring, wherein the time slots ring are circularly processed in a continuous fashion thereby enabling scheduled transmission of ATM cells in the network. The processor is operable to queue the VCID of a newly calculated target slot in an already occupied time slot if the newly calculated target slot is occupied, thereby creating a linked list of VCs, and the processor is operable to service all VCs at a single time slot before proceeding to a next time slot.
    Type: Grant
    Filed: December 28, 1995
    Date of Patent: January 27, 1998
    Assignee: Lucent Technologies Inc.
    Inventors: Chinh Kim Nguyen, Sunder Raj Rathnavelu, Don Tipon
  • Patent number: 5706288
    Abstract: An available bit rate scheduling method and apparatus for asynchronous transfer mode communication of a plurality of cells over a network characterized by a system clock frequency f and an allowed cell rate ACR. Each cell belongs to an assigned virtual circuit communication channel which is defined by a set of negotiated traffic parameters. The invention partitions the ACR's of the virtual circuits into a smaller subset of profiles/sub-profiles and conducts a deterministic search to service them. The scheduler incorporates a profile generator for iteratively generating a number p of the profiles by (i) outputting a k*modulo 2.sup.i th one of the profiles during each kth iteration of the profile generator, where 1.ltoreq.i.ltoreq.p and 1.ltoreq.k.ltoreq.p-1; (ii) outputting a null profile during each 2.sup.p th one of the iterations; and, (iii) dispatching the profiles from the profile generator to the profile queue such that a particular profile is dispatched at a time T=T.sub.0 +(1/ACR)*f, where T.sub.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: January 6, 1998
    Assignee: PMC-Sierra, Inc.
    Inventors: Sivakumar Radhakrishnan, Stephen J. Dabecki, David Walden Wong