Contention Resolution For Output Patents (Class 370/418)
  • Patent number: 5691977
    Abstract: In a data access device for writing into or read from a data conversion table on the basis of a clock signal extracted from a cell being transferred over a line, a clock signal generator of the invention generates a second clock signal which differs from the first clock signal extracted from an incoming cell. A write/read control unit writes data into or reads data for maintenance from the data conversion table on the basis of either the first clock signal or the second clock signal when the line is normal. In the event of the occurrence of a failure in the line, on the other hand, the write/read control circuit permits the data conversion table to be written into or read from for maintenance on the basis of the second clock signal.
    Type: Grant
    Filed: December 29, 1995
    Date of Patent: November 25, 1997
    Assignee: Fujitsu Limited
    Inventors: Shuji Yoshimura, Satoshi Kakuma, Masami Murayama, Shiro Uriu, Tadashi Hoshino
  • Patent number: 5689508
    Abstract: A non-blocking switching network for routing packets from a plurality of inputs to a plurality of outputs includes a reservation ring mechanism for resolving conflicts among inputs contending for access to specified ones of said outputs. This reservation ring performs a sequence of step and compare operations in top-to-bottom ring-like order during at least one arbitration cycle for granting contending inputs access to said specified outputs in a top-to-bottom order that is also consistent with the order required by self-clocked weighted fair queueing or, alternatively, virtual clock, with up to a maximum permissible plural number of contenders being given access to such an output on each of the arbitration cycles.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: November 18, 1997
    Assignee: Xerox Corporation
    Inventor: Joseph B. Lyles
  • Patent number: 5689500
    Abstract: Multicasting of an ingress cell received at one of a plurality of input ports is provided through a multistage network to a plurality of output ports. The received ingress cell at a first input port includes a data payload and information identifying one or more routing queues to which a single copy of the data payload is to be outputted. A backpressure queue assignment is identified for the first ingress cell, the backpressure queue assignment identifying a backpressure indicator indicative of the congestion level at at least one routing queue of a subsequent stage. Using the backpressure indicator, it is determined if the first ingress cell is to be outputted from one or more of the routing queues. Thereafter, the first ingress cell is outputted from one or more of the routing queues when the congestion level is below or equal to a first threshold.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: November 18, 1997
    Assignee: Lucent Technologies, Inc.
    Inventors: Fabio Massimo Chiussi, Joseph George Kneuer, Vijay Pochampalli Kumar
  • Patent number: 5640389
    Abstract: A traffic shaper in a packet communication apparatus receives packets and immediately calculates a departure time for each received packet, using designated bandwidth allocation parameters. The packets are stored in a packet memory according to their calculated departure times. When each departure time arrives, the packets that have been stored for that departure time are transferred to an output queue. Packets are output in sequential order from the output queue.
    Type: Grant
    Filed: August 15, 1995
    Date of Patent: June 17, 1997
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Fumitoshi Masaki, Kiyoshi Shimokoshi
  • Patent number: 5636210
    Abstract: An asynchronous transfer mode packet switch for use in a Broadband Integrated Services Digital Network is disclosed. The asynchronous transfer mode packet switch is highly modular and allows expansion of the switch to handle applications having less than eight input and output devices to applications having up to 2.sup.14 input and output devices. The preferred asynchronous transfer mode packet switch is constructed as either a single-stage switch for routing data packets between up to 2.sup.6 input and output devices, a two-stage switch for routing packets between up to 2.sup.10 input and output devices, or a three-stage switch for routing packets between up to 2.sup.14 input and output devices.
    Type: Grant
    Filed: August 2, 1995
    Date of Patent: June 3, 1997
    Inventor: Jagannath P. Agrawal