Bus Extenders Patents (Class 370/502)
  • Publication number: 20020006139
    Abstract: A multiplex communication system includes a plurality of networks and a data relay unit. When an event occurs in a node belonging to one of the networks, the node (sender node) sends a wake-up frame before it sends an event frame. In response to the wake-up frame, the nodes belonging to the same network which includes the sender node are activated and the data relay unit sends a wake-up frame to the respective networks for activating the networks. When it is determined that each of the networks is activated, the data relay unit sends a network activation notifying (NAN) frame regarding the network to all the networks. The NAN frame regarding the network represents that the network is activated. The sender node sends the event frame in response to the NAN frame regarding the destination network of the event frame.
    Type: Application
    Filed: June 11, 2001
    Publication date: January 17, 2002
    Inventors: Hajime Kikkawa, Tomohisa Kishigami, Jiro Sato, Shinichi Senoo
  • Patent number: 6317417
    Abstract: A SCSI bus expander provides signal conditioning for transmitted data pulses that is particular to a negotiated data transfer rate. The expander monitors the bus arbitration to determine the devices involved in the transfer, and thereafter monitors the data transfer rate negotiations to determine the transfer rate to be used by that particular combination of devices. An indication of the transfer rate is stored in a memory device at an address determined by the device IDs. The transfer rate is then used to select tap values for tap lines that modify the pulse width and/or a propagation delay of the pulse, so as to correct for signal degradation and to align it better relative to other signals during data transmission. The specific tap values may vary for the different combinations of transmitting and receiving devices involved in the transfer, since the manner in which the pulse characteristics should be modified may be different for different transmission rates.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: November 13, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Keith Childs, Fee Lee
  • Publication number: 20010021200
    Abstract: The present invention concerns more particularly a method of isolating target cell signals originating from a target cell from active cell signals originating from an active cell in a cell search.
    Type: Application
    Filed: March 9, 2001
    Publication date: September 13, 2001
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA Tokyo, Japan
    Inventor: Marian Rudolf
  • Patent number: 6256312
    Abstract: A local area communication system is disclosed. The system includes a plurality of users connected to respective busses. A multiport bridge router recognizes destination addresses and diverts packets from one bus to another. Repeaters for several users may be formed on a single integrated circuit.
    Type: Grant
    Filed: April 9, 1997
    Date of Patent: July 3, 2001
    Assignee: Lucent Technologies, Inc.
    Inventor: Clarence Chulljoon Joh
  • Patent number: 6118809
    Abstract: A repeater set provides for delaying a character of data that passes through the repeater set from one receive channel to a set of transmit channels. In providing for the delay of a character, the repeater set includes a delay calculator for calculating a character delay value. The repeater set then receives a character that is to be provided on a transmit channel and delays the character in a delay module for a period of time equal to the character delay value. The character delay value is determined by the delay calculator by first calculating a bit delay value and then converting the bit delay value into the character delay value.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: September 12, 2000
    Assignee: Advanced Micro Devices
    Inventor: William Lo
  • Patent number: 6108312
    Abstract: An apparatus for automatically activating a clock master circuit in a stack of Fast Ethernet repeaters includes a first stackable Fast Ethernet repeater is disclosed. The first stackable Fast Ethernet repeater includes a first on pin having a first on pin logical state. The first on pin logical state is indicative of whether or not the first stackable Fast Ethernet repeater is configured in the stack of Fast Ethernet repeaters so that no other Fast Ethernet repeater occupying a position in the Fast Ethernet repeater stack that is before the position of the first Fast Ethernet repeater is powered on. A weak pull up voltage source is connected to the first on pin. The weak pull up voltage is derived from a switched power supply in the Fast Ethernet repeater so that when the Fast Ethernet repeater is powered on, the weak pull up voltage is present and when the Fast Ethernet repeater is powered off, the weak pull up voltage is not present.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: August 22, 2000
    Assignee: Cisco Technology, Inc.
    Inventor: Moshe Voloshin
  • Patent number: 6023476
    Abstract: A logical repeater set provides for delaying a character of data that passes through the logical repeater set from a receive channel in a receiving repeater set to a set of transmit channels in transmitting repeater sets. In providing for the delay of a character, the receiving repeater set calculates a receive channel character delay value, and receives a character that is to be provided on a transmit channel. The receiving repeater set then delays the character for a period of time equal to the receive channel character delay value and providing the character to the transmitting repeater set. Each transmitting repeater set further calculates a set of transmit channel character delay values for a set of transceivers. Each transmitting repeater set receives a character from the receiving repeater set that is to be provided on a transmit channel and further delays the character by a transmit channel character delay value.
    Type: Grant
    Filed: January 31, 1997
    Date of Patent: February 8, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: William Lo
  • Patent number: 5841360
    Abstract: A network topology allowing distributed sensing, control and communication, comprising a power source and a plurality of line-Powered, Serially connected Intelligent Cells (PSICs) coupled to the power source and to each other via respective communication channels comprising at least two electrical conductors. Each of the PSICs is uniquely addressed, preferably "on the fly" in real time, and at least one payload element is coupled to one of the PSICs for operating in accordance with control logic embedded in or fed to the corresponding PSIC. The communication channels allow for data transfer between adjacent PSICs in either or both directions independent of a simultaneous communication between another pair of adjacent PSICs.
    Type: Grant
    Filed: October 22, 1996
    Date of Patent: November 24, 1998
    Inventor: Yehuda Binder
  • Patent number: 5805596
    Abstract: In a backplane architecture for a logical stackable Ethernet repeater for an Ethernet network having a plurality of stackable repeater modules, each one of the stackable repeater modules being connectable via bus-type signal lines to one another for communicating packets via bus-type signal lines, and each one of said stackable repeater modules including a plurality of ports for connection to stations, a method is provided for communicating management information wherein a management module collects information about packets on the backplane from repeater modules, and the repeater modules transmit packet information only via bus-type signal lines. In a specific embodiment, transmitting comprises appending after each packet at each source port of each repeater module an information footer having a select number of information units, and conveying each packet with the information footer on the bus-type signal lines.
    Type: Grant
    Filed: December 21, 1995
    Date of Patent: September 8, 1998
    Assignee: 3 Com Corporation
    Inventors: David A. Kranzler, Wen-Tsung Tang, Edwin Ibe
  • Patent number: 5663950
    Abstract: An apparatus and method for fault isolation and bypass in a dual ring communication system provides a reconfiguration unit capable of attachment to a dual ring communication system having a plurality of reconfiguration units. The disclosed reconfiguration unit has a single adapter to the dual ring communication system and includes isolation and wrap switches capable of isolation and bypass of faults. A reconfiguration unit having a single adapter to the dual ring communication system detects failures on the ring and generates a failure frame which if not received from the ring causes the reconfiguration unit to enter a downstream wrap state. The reconfiguration unit enters an upstream wrap state if a failure frame is received from the nearest downstream reconfiguration unit.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: September 2, 1997
    Assignee: International Business Machines Corporation
    Inventors: Nai Po Lee, Jay Lee Smith