Abstract: A method for writing information to a first memory location controlled by a first computing system from a second memory location controlled by a second computing system that interfaces with the first computing system via a network connection is provided.

Abstract: An aspect of the invention relates to a method and apparatus for multiplexing content. In one example, a first transport stream is received. The first transport stream includes a sequence of burst cycles, each of the burst cycles having a plurality of packet bursts respectively associated with a plurality of primary services. In one example, a primary service is a national service. A packet burst stream is received that is associated with a secondary service. In one example, a secondary service is a regional service. The first transport stream is multiplexed with the packet burst stream to produce a second transport stream. The second transport stream includes a deterministic relationship between the plurality of packet bursts in each of the burst cycles and packet bursts of the packet burst stream. Additional packet burst streams associated with additional secondary services may be received and multiplexed in a similar manner.

Abstract: A method, apparatus and computer product for scheduling in a cellular system using a wired RS is disclosed. In one aspect, a BS collects CQIs of all MSs within a cell, calculates a transmittable data amount for each of the MSs according to the CQI, selects an MS having a highest PF metric, and allocates resources to the selected MS.

Abstract: Systems, methods, and apparatus for the detection of signals having spectral peaks with narrow bandwidth are described herein. The range of described configurations includes implementations that perform such detection using parameters of a linear prediction coding (LPC) analysis scheme.

Abstract: A system and method for partitioning a bandwidth of a single channel among plural multimedia streams in a time varying manner. The partitioning is undertaken by dynamically establishing first and second bit rates respectively associated with first and second multimedia streams.

Abstract: An output control unit outputs data of bit rate A to a first header-attaching unit and data of bit rate B to a second header-attaching unit. An instructing unit instructs the first or the second header-attaching unit to attach a header of bit rate being the least bit rate to the data of bit rate A or B. The first header-attaching unit creates a header of bit rate A, including an ID of a destination ONU of the data of bit rate A and information concerning the data length, and attaches the header of bit rate A to the data of bit rate A. The second header-attaching unit creates a header of bit rate A, including an ID of the destination ONU of the data of bit rate B and information concerning the data length, and attaches the header of bit rate A to the data of bit rate B.

Abstract: A telephony system and method is provided that reduces delay and provides better utilization of upstream bandwidth in delivering packet telephony services to a plurality of subscriber lines via a cable modem system. An exemplary system includes a plurality of voice processing modules, a host processor, and a buffer. Each voice processing module receives digital voice signals from a separate set of subscriber lines, compresses the digital voice signals to generate a voice packet, and transfers the voice packet to the buffer. The host processor then assembles a packet by concatenating the voice packets and transmits the assembled packet for delivery over a data network. Because the plurality of voice processing modules process the voice packets in parallel, delay is reduced in the assembly and transmission of the assembled packet.

Abstract: A method for rate-shaping media streams; the method includes: receiving multiple input media streams, transmission parameters, wired transmission limitations and wireless transmission limitations that represent a current status of a wireless medium; and rate-shaping at least one input media stream out of the multiple input media streams, in response to: (i) the transmission parameters, (ii) the wireless transmission limitations, and (iiii) input media stream parameters. A system for processing media streams; the system includes: a controller, adapted to determine rate-shaping parameters in response to: (i) the transmission parameters, (ii) the wireless transmission limitations, and (iii) input media stream parameters; and a rate-shaper, connected to the processor, adapted to receive multiple input media streams and perform rate-shaping according to the rate-shaping parameters.

Abstract: A clock recovery method and apparatus is provided. The high-order demultiplexing-demapping unit (102) demultiplexes and demaps the high-order OTN frame (101) into N low-order ODTUjk frames (103), and transmits the N low-order ODTUjk frames (103) to the low-order demapping unit (104); the low-order demapping unit (104) respectively demaps the N ODTUjk frames (103) into N ODUj frames (105), and writes the ODUj frames from memory unit 1 (106) to memory unit n (108) into memory unit n+1 (109) to memory unit 2n (111) by using the clock signal whose gaps are uniformly distributed; and the ODUj frame clock generating unit (113) adjusts the read out clock in memory unit n+1 (109) to memory unit 2n (111), i.e. ODUj frame clock (114), according to the data volume stored in memory unit n+1 (109) to memory unit 2n (111).

Abstract: A system for interleaving high speed data and slower data that is serialized and delivered to a microprocessor. The typical source of the high speed data is a camera and the source of the slower data is a keyboard. The high speed data and the slower data, illustratively, are interfaced with a micro-processor in a parallel fashion. The present invention mirrors the parallel interface to the microprocessor, and mirrors the parallel interface to the sources of the high speed (camera) and slower (keypad) data. The present system formats parallel data from the sources and passes that data in serial form, typically with a clock, on a flexible cable that joins two sections of many cell phones or other hand held devices.

Abstract: A circuit capable of processing signals of different signal types is provided for identifying the signal type by the signal type setting from an administrator or by the implementation of the optical module, thereby selecting a signal processor to be used. An OTN frame standardized by ITU is used in a fixed manner independent of the signal type to be accommodated, while a corresponding SDH/SONET frame standardized by ITU is used for signal accommodation.

Abstract: The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1.

Abstract: The disclosure relates to techniques for video packet shaping for video telephony (VT). The techniques can be used to prioritize audio packets to reduce audio delay. Channel conditions, excessive video content, or both can cause delays in audio transmission. When reverse link (RL) throughput is reduced, video packet size can overwhelm the RL and increase audio delay. The video packet may consume an excessive number of MAC RLP packets, resulting in delays between successive audio packets. The size of each video packet is adjusted so that audio packets are prioritized for transmission without substantial delay. The video packet size may be controlled based on channel conditions. The audio can be conveyed without substantial delay, even though the video may suffer from delay due to channel conditions. Although video may be compromised by channel conditions, video packet shaping ensures that the VT parties are able to smoothly carry on verbal conversation.

Abstract: A DTV transmitting system includes two pre-processors. The first pre-processor codes high-priority enhanced data for forward error correction (FEC) and expands the FEC-coded data. The second pre-processor codes low-priority enhanced data for FEC and expands the FEC-coded low-priority enhanced data. The DTV transmitting system further includes a data formatter generating enhanced data packets including the pre-processed data, a multiplexer multiplexing the enhanced data packets with main data packets, an RS encoder RS-coding the multiplexed data packets, a data interleaver interleaving the RS-coded data packets, and a block processor which codes each block of enhanced data in the interleaved enhanced data packets and bypasses the interleaved main data packets.

Abstract: A communication system is provided, which comprises a data conversion module and a framer. The data conversion module is configured to receive a first plurality of data streams. The data conversion module is also configured to provide a second plurality of data streams. Each of the second plurality of data streams comprises first data units, channel identifiers, and format indicators. Each of the first data units is associated with one of the channel identifiers and one of the format indicators. The format indicators are based on variable bandwidths of data streams. The framer is configured to receive the second plurality of data streams. The framer is also configured to identify channel information of the second plurality of data streams. The framer is also configured to allocate the second plurality of data streams into one or more self-describing superframes.

Abstract: An apparatus and method for generating a multiplex of media streams, the method includes the steps of: (i) receiving a set of media streams that comprises first type media stream components and second type media stream components; (ii) applying a modification process that is not adapted to modify second type media stream components, such as to provide at least one modified first type media stream component; and (iii) multiplexing at least the second type media stream components and the modified first type media stream components.

Abstract: Systems and methods for burden sharing in satellite based communication systems are disclosed. One or more users in a satellite based communication system may experience signal degradation or signal fading that can occur for an extended period of time, such as when the fade is due to rain fade. The system can improve a communication link with a particular user by varying the data rate. The data rate can be varied by reducing a coding rate to compensate for low signal quality. In a time multiplexed communication system where multiple users time multiplex the available communication bandwidth, the system can concurrently adjust a time allocated to a user based in part on the coding rate. The time allocated to a user can be increased for decreased coding rates in order to maintain a substantially stable symbol rate to the user for each time multiplex cycle of users.

Abstract: A communication node contains intelligence for directing both internet protocol (IP) packets and Asynchronous Transfer Mode (ATM) cells toward their destinations. The ATM cells and IP packets may be received within a common data stream. The respective devices process the ATM cells and IP packets to direct the cells and packets to the proper output ports towards their destinations. The device is capable of performing policing and quality of service (QOS) processing on both the ATM cells and the IP packets.

Abstract: System and methods are provided for multiplexing digital data. In accordance with certain implementations, a method is provided that includes coordinating transmission of digital data elements of a packet including digital data elements arranged 1 . . . n. The coordinating step may include transmitting a first stream of data elements stored in memory, starting with data element 1 of the packet and proceeding upward through the data elements of the packet in sequential order, and transmitting a second stream of data elements stored in the memory, starting with data element n of the packet and proceeding downward through the data elements of the packet in sequential order, wherein transmitting of the first stream and the second stream is attempted to be performed during the same time. The method may also include terminating any sending of the first and second streams of data elements when the entire packet has been received.

Abstract: A DTV transmitting system includes two pre-processors. The first pre-processor codes high-priority enhanced data for forward error correction (FEC) and expands the FEC-coded data. The second pre-processor codes low-priority enhanced data for FEC and expands the FEC-coded low-priority enhanced data. The DTV transmitting system further includes a data formatter generating enhanced data packets including the pre-processed data, a multiplexer multiplexing the enhanced data packets with main data packets, an RS encoder RS-coding the multiplexed data packets, a data interleaver interleaving the RS-coded data packets, and a block processor which codes each block of enhanced data in the interleaved enhanced data packets and bypasses the interleaved main data packets.

Abstract: Aspects of a method and system for reordered QRV-LST (layered space time) detection for efficient processing for multiple input multiple output (MIMO) communication systems are presented. The method may include receiving an ordered plurality of signals wherein each of the ordered plurality of received signals comprises information contained in an ordered plurality of spatial streams. Each spatial stream may comprise one or more frequency carriers, or tones. Information, or data, contained in a corresponding one of the ordered plurality of spatial streams may be detected. The order in which the information is detected may be determined for each individual frequency carrier.

Abstract: An integrated circuit includes current mode drivers that provide equalized outputs. A parallel-to-serial converter circuit receives data at less than one fourth the output data rate, and provides main data and equalization data at one fourth the output data rate to at least one four-to-one multiplexer. The main data and equalization data is multiplexed onto an output node at the output data rate.

Abstract: A plurality of programs are statistically multiplexed using a statistical multiplexing (stat mux) system. Rchannel, a constant total bit rate for the plurality of programs, is determined. Cl,Ff,picTYpe, a complexity for each picture in the plurality of programs, is determined. Tl,Ff,picType, a bit allocation for each picture in the plurality of programs, is determined based on Cl,Ff,picTYpe and Rchannel. The plurality of programs are encoded using a plurality of encoders, a combined encoder buffer, and Tl,Ff,picType to form a plurality of variable bit rate (VBR) compressed bit streams. The plurality of VBR compressed bit streams are multiplexed to form a single constant bit rate (CBR) bit stream.

Abstract: A method and apparatus for efficient provisioning of a VT/TU cross-connect includes checking a state of a control bit that specifies whether to assemble an output from multiple virtual tributary (VT1.5/VT2) or tributary unit (TU11/TU12) connections or handle the output as an synchronous transport signal (STS) or administrative unit (AU-3/AU-4) connection, and switching a predetermined number of entries together based on a state of the control bit.

Abstract: A data transfer system receives a first service flow, a second service flow, and a third service flow that comprise a data session for a user device. The data transfer system transfers the first service flow to a scheduler using a first data rate limit and transfers the second service flow to the scheduler using a second data rate limit. The data transfer system also transfers the third service flow to the scheduler. The scheduler schedules transfers of the first service flow and the second service flow at a higher priority than transfers of the third service flow. The data transfer system transfers the first service flow, the second service flow, and the third service based on the prioritized schedule and using a third data rate limit. Thus, the first and second service flows receive a limited amount of preferential bandwidth, and the third service flow obtains unused bandwidth from the first and second service flows, subject to the third data rate limit.

Abstract: In a data acquisition system, digitizing circuitry (2A) is powered up by a control signal (ADC_CONVST), superimposing a glitch (42-1) on a first multiplexed and amplified signal value (VINF) received by the digitizing circuitry. Sampling and holding of the first multiplexed and amplified signal value occurs during a delay provided between the glitch and a beginning of a first A/D conversion of the first multiplexed and amplified signal value to allow settling of the glitch. After the first conversion begins, a second multiplexed and amplified signal value is generated. The digitizing circuitry performs the first A/D conversion during initial settling of the second multiplexed and amplified signal value and then is powered down while the second multiplexed and amplified signal value continues to settle.

Abstract: An add/drop multiplexer where a first signal converter converts first-low-order-group signals received from DSn network, into high-order-group signals, which are transferred to SDH (SONET) network and to which second-low-order-group signals, slower in transmission speed than the first-low-order-group signals are added. A second signal converter converts high-order-group signals, received from SDH (SONET) network, into first-low-order-group signals. A selector selectively outputs first-low-order-group signals received from the DSn network, or first-low-order-group signals obtained by the second signal converter, as the input signals to the first signal converter.

Abstract: Systems and methods for conveying multiple low-bit-rate data streams over a data transport medium which is configured to transport data in a single, high-bit-rate data stream. In one embodiment, a plurality of low-bit-rate signals are received and a corresponding data rate is determined. Each of the signals is formatted in frames comprising a payload and overhead data. The high-bit-rate signal is also formatted in frames comprising a payload and overhead data, but the frames (including payload and overhead) contain more bits than those of the low-bit-rate frames. The payloads of the low-bit-rate frames are mapped into the payloads of the high-bit-rate frames. The overhead and timing data of the low-bit-rate frames are mapped into the unused portion of the overhead of the high-bit-rate frames. After the high-bit-rate signal is transported, the payload, overhead and timing data of each of the low-bit-rate signals is extracted, and the corresponding signals are reproduced.

Abstract: An audio codec in a baseband processor may be utilized for mixing audio signals received at a plurality of data sampling rates. The mixed audio signals may be up sampled to a very large sampling rate, and then down sampled to a specified sampling rate that is compatible with a Bluetooth-enabled device by utilizing an interpolator in the audio codec. The down-sampled signals may be communicated to Bluetooth-enabled devices, such as Bluetooth headsets, or Bluetooth-enabled devices with a USB interface. The interpolator may be a linear interpolator for which the audio codec may enable generation of triggering and/or coefficient signals based on the specified output sampling rate. An interpolation coefficient may be generated based on a base value associated with the specified output sampling rate. The audio codec may enable selecting the specified output sampling rate from a plurality of rates.

Abstract: In a DOCSIS-based communications system, different upstream channel descriptors (UCDs) all identify a single logical upsteam channel identifier (UCID) regardless of the type of cable modem (CM) to which the UCDs are sent. Different CMs having different capabilities (e.g., CMs configured according to the different DOCSIS standards 1.x, 2.0, and 3.0) receive their respective UCDs from an upstream headend. All the UCDs, however, refer to the same logical upstream channel. The different CMs therefore share this single logical upstream channel.

Abstract: A serial interface circuit includes a plurality of serial transmitters for a plurality of channels, respectively; and a plurality of serial receivers provided for said plurality of channels and connected with said plurality of serial transmitters, respectively. Each of said plurality of serial transmitters transmits a serial signal. Each of said plurality of serial receivers includes a receiver circuit configured to convert the serial signal into a data sequence; n (n is an integer more than 1) register groups configured to shift the data sequence; a data processing circuit configured to perform a data process on said data sequence based on n outputs of said n register groups and a detection result; and a header detecting circuit configured to detect a header of the data sequence when said b register groups from a first register group to a bth register group among said n register groups shift the data sequence, and to output the detecting result to said data processing circuit.

Abstract: Multiplexers are basic components widely used in VLSI designs. Switching activities of a multiplexer are one of the most important factors of power consumption. A multiplexer may have some sub-multiplexers. An extra dynamic controller is applied in the present invention to reconfigure control signals for decreasing switching activities of the composed sub-multiplexers. Thus, the power consumption of the multiplexer is reduced to achieve higher power efficiency.

Abstract: A method for adapting the rates of a certain number of asynchronous HDLC channels (15) to a single clock domain suited for interfacing with an HDLC processor (13) through a synchronous pseudo-TDM interface (14) in which the HDLC channels are multiplexed in time and vice versa in the opposite direction. In one direction the algorithm is based on the writing of the HDLC channels in a dedicated buffer (17) and in reading these buffers with a common synchronous clock just above the expected maximum HDLC rate. The under-run condition is avoided by inserting neutral information between the end byte and the start byte of the HDLC packets when this is suggested by the buffer fill monitoring function. A simple function to locate the first and last bytes of each HDLC packet read by the buffer is hence used in combination with the buffer fill monitoring function.

Abstract: A time zone start time point calculating unit calculates a time zone to be set in a VOBU in accordance with audio bit rate. A time zone comparing unit compares a time point at which an audio pack is to be multiplexed with the time zone calculated by the time zone start time point calculating unit. A flag setting unit sets whether the audio pack is to be completed or not in accordance with the result of comparison by the time zone comparing unit. Therefore, a completing process takes place before a VOBU boundary, and a completed PCK will not be generated immediately after the VOBU boundary. Thus, generation of a buffer overflow can be prevented.

Abstract: A fiber channel (FC) signal representing block encoded data is applied to a block decoder, which removes the block encoding from the data. The data is then applied to a simplified data link (SDL) protocol encoder, which maps the data into an SDL protocol packet for transmission over a SONET (Synchronous Optical Network)-based transport medium.

Abstract: A field-programmable gate array (“FPGA”) or programmable logic device (“PLD”) includes relatively general-purpose PLD core circuitry and relatively specialized high-speed serial interface (“HSSI”) hard IP circuitry. To better support applications that include forward error correction (“FEC”), some tasks related to FEC (e.g., FIFO operations) are performed in the PLD core circuitry, while other FEC tasks (e.g., FEC calculations) are performed in the HSSI hard IP circuitry.

Abstract: The area of the invention belongs to the transport technologies in UTRAN. This invention concerns a method for multiplexing a data stream onto a transport bearer between an originating network node and a receiving network node in a telecommunications network. This is done in order to ensure the effective usage of transport resources over the two interfaces, i.e. Iub/Iur. To accomplish this the RNC and/or Node B/RNC should check if the there already exists a transport bearer, which can be utilized for HS-DSCH transport over Iub/Iur interface. Because of this a transport bearer identification code or transport bearer id is needed to identify this bearer between RNC and Node B/RNC.

Abstract: A network diagnostic system may include a network diagnostic module. The network diagnostic module may be configured to generate one or more network diagnostic statistics. The network diagnostic module may be configured to automatically handle multiple data transmission rates.

Abstract: A system (104) is provided for filling a SONET SPE (204, 300, 500, 600, 700) with bytes of digital information. The system is comprised of data input ports (1-6) configured to receive payload signals comprised of payload information. The system is also comprised of data processing circuits configured to transfer bytes of payload information in sequence from the payload signals. The data processing circuits are also configured to break the payload information into byte segments. The data processing circuits are further configured to map the byte segments to the SONET SPE in a byte by byte manner. The SONET SPE is comprised of cells. The cells are filled from top to bottom in a manner proceeding row by row, from left to right in each row. A method for filling the SONET SPE with bytes of digital information corresponding to payload signals is also provided.

Abstract: A method of data transmission which includes providing a plurality of data streams, having different content, modulating the different data streams by respective modulators, multiplexing the modulated data streams into a single data stream alternately in time, such that the resultant stream includes at any specific time signals from fewer than all the data streams and transmitting the multiplexed single data stream onto a transmission channel.

Abstract: Disclosed are a radio link control (RLC) entity and a data processing method for the RLC entity. The RLC entity includes a transmission data storing module that stores PDUs corresponding to SDUs transmitted from a first upper layer and outputs the stored PDUs by SDU units, a ciphering module that ciphers the PDUs stored in the transmission data storing module and transmitting the ciphered PDUs to a first RLC entity, a deciphering module that deciphers the ciphered PDUs transmitted from a second RLC entity, and a received data storing module that stores the deciphered PDUs and outputs the PDUs toward a second upper layer in the form of SDU units.

Abstract: A DTV transmitting system includes two pre-processors. The first pre-processor codes high-priority enhanced data for forward error correction (FEC) and expands the FEC-coded data. The second pre-processor codes low-priority enhanced data for FEC and expands the FEC-coded low-priority enhanced data. The DTV transmitting system further includes a data formatter generating enhanced data packets including the pre-processed data, a multiplexer multiplexing the enhanced data packets with main data packets, an RS encoder RS-coding the multiplexed data packets, a data interleaver interleaving the RS-coded data packets, and a block processor which codes each block of enhanced data in the interleaved enhanced data packets and bypasses the interleaved main data packets.

Abstract: An apparatus and method are provided to perform a time multiplexing logic in a module, are provided including identifying a driving flop and a receiving flop in the module, receiving a modified input signal, and identifying a worst case timing path for the modified input signal to transmit from the driving flop to the receiving flop. The time multiplexing logic of the apparatus and method further identifies a predetermined point of the worst case timing path, and inserts a logic unit at the predetermined point allowing the time multiplexing logic circuit to process and output the modified input signal at a maximum frequency.

Abstract: A method and system for multiplexing a plurality of serialized data signals in which a first integrated circuit device generates a plurality of serialized data signals. A second integrated circuit device is in electrical communication with the first integrated circuit device. The second integrated circuit device includes a multiplexer operable to generate a multiplexed output signal from the plurality of serialized data signals received from the first integrated circuit. A phase data and byte snapshot back channel is transmitted from the second integrated circuit device to the first integrated circuit device. The phase data and byte snapshot back channel carries phase data and periodic snapshots of the serialized data signals. The phase data and byte snapshot back channel is used by the first integrated circuit device to adjust the phase of each of the plurality of serialized data signals to preserve bit and byte alignment. Such a method and system can be implemented as a 4×10 Gbit/Sec.

Abstract: A method for multiplexing digital data, wherein a packet of digital data is simultaneously sent from front to rear and from rear to front. Additionally, a method for multiplexing digital data, wherein a packet of digital data is simultaneously sent from the beginning of the packet towards the end and from the end towards the beginning. Additionally, a method for multiplexing digital data, wherein simultaneously a packet of digital data is sent and the same packet is sent backwards.

Abstract: A transmitting device includes a first buffer for temporarily storing audio data, a second buffer for temporarily storing video data, a multiplexing unit for outputting audio data coming from the first buffer and video data coming from the second buffer onto a single signal channel, and a transmission buffer monitoring unit for monitoring the amount of first buffered data stored in the first buffer and, if the amount of the first buffered data exceeds a first threshold, instructing the second buffer to discard video data.

Abstract: The remultiplexing apparatus includes a control information selector that selects a packet containing program control information from the inputted bit stream, a program control information editor that edits contents of the selected program control information and generates new program control information corresponding to an outputted bit stream, and a remultiplexer for multiplexing again the packet containing media information in the inputted bit stream and the program control information generated by the program control information editor.

Abstract: Methods and apparatus for sharing network bandwidth between devices connected to a bus are presented. Each of the devices belongs to one of a number of device classes. Each device class is associated with a respective data transfer rate at which information may be exchanged over the bus. An exemplary method includes the step of assigning a gap interval to each device based on at least the data transfer rate of the class to which the device belongs, the assigned gap interval being inserted between portions of a data stream sent by the corresponding device over the bus. The assigned gap interval may be inserted between portions of a data stream sent by the corresponding device over the bus to achieve the desired data rate resulting in an equitable sharing of bandwidth between the devices connected to the bus.

Abstract: The present invention provides methods and apparatus for reconfiguring protocol data for a multiplexed data stream which is reduced to carry fewer services for cable-side transmission in a cable television plant or the like. More particularly, the present invention provides methods and apparatus for reconfiguring protocol data for a desired combination of data streams contained within an incoming high data rate multiplexed data stream, such as a high data rate Quadrature Phase Shift Keying (QPSK) modulated multiplexed data stream, when the incoming multiplexed data stream is reduced.

Abstract: Provided is an optical transponder that receives a tributary signal such as a SDH/SONET signal, a GbE (Gigibit Ethernet) signal, and a SAN (Storage Area Network) signal in a WDM (Wavelength Division Multiplexing) transmission system and a SDH (Synchronous Digital Hierarchy)/SONET (Synchronous Optical Network) system, and more particularly, to an optical transponder having a switching function. The optical transponder having a switching function includes: a switch changing a data path of an input tributary signal from a plurality of channels (ports); an STM-64/OC-192 mapper/demapper mapping the tributary signal switched to a different data path by the switch to an STM-64/OC-192 signal or demapping the STM-64/OC-192 signal to the tributary signal; and a transmission delay time compensator compensating for a differential delay caused by a transmission route difference on an optical fiber link when the STM-64/OC-192 signal is demapped to the tributary signal.