Abstract: The invention provides an apparatus and method for transparently transporting four plesiochronous Gigabit Ethernet, Fibre Channel or other packet-based data signals over a network. Multiple plesiochronous Gigabit Ethernet data streams are aggregated onto an independent clock source at an ingress circuit through the use of transparent IDLE character insertion. The independent clock is selected such that the output data rate is greater than the composite input data rate of all the plesiochronous data streams. The signals are encapsulated with forward error correction and mapped to a reciprocal FEC interface prior to transport. An egress circuit at the receiving end recovers the modulated signal and extracts the data stream. Each independent data stream is mapped to a local clock domain via IDLE character insertion or removal. Therefore, the input and output signals are transparent and identical in content.

Abstract: A multi-access transmission method for effectively and efficiently utilizing bands of a synchronous digital hierarchy (SDH) path. The method has the steps of extracting a synchronous digital hierarchy path from signals input from a first point, recognizing all packets or cells input from the first point to select and drop a packet or cell to be dropped at a second point, multiplexing packets or cells not dropped and a packet or cell to be inserted at the second point at a packet or cell level, and sending signals created at the multiplexing step to a third point. With this method, packets or cells are multiplexed in a synchronous digital hierarchy path to share one synchronous digital hierarchy path among a plurality of communications.

Abstract: A synchronous transfer mode (STM)-256 adder/dropper which provides a communication path between STM-64 optical channels in an apparatus of multiplexing STM-64 optical channels into STM-256 electrical signals, is provided. The STM-256 adder/dropper transmits STM signals by multiplexing the STM signals at a low speed and simultaneously provides a communication path between lower channels.

Abstract: A method for fast and economic handling of overhead bytes of an incoming high order data stream to form a corresponding outgoing high order data stream, the method comprising a) presenting the incoming high order data stream as a plurality of N component data streams transmitted in parallel, b) providing a common overhead processing unit (COHPU) capable of handling overhead bytes of a single one of the component data streams, c) forwarding overhead bytes of the component data streams to the COHPU in a circular order, while keeping docketing (ID) information for each particular overhead byte; d) processing each of the overhead bytes in the COHPU, and e) modifying the N component data streams to obtain an outgoing high order data stream based on results of the processing and the ID information with respect to each of the processed overhead bytes.

Abstract: There is disclosed a method of carrying frame based data, eg Ethernet data, over a synchronous digital hierarchy network in order to provide local area network type functionality over a wide area network coverage. Specific embodiments disclose methods of mapping Ethernet data frames into SDH virtual containers, and distinguishing start and end boundaries of the Ethernet data frames within the virtual container payloads, by a selection of encoding methods including a segmentation, pointer methods, bit stufifng methods and byte stuffing methods. Data frames are encoded with a code which designates a boundary of each frame, and the encoded frames are input into asynchronous data channel.

Abstract: A method and apparatus for servicing massive interrupts in random access memory (RAM) are provided, comprising receiving a massive interrupt signal, and reading at least one unit interrupt register in a first RAM area in response to the massive interrupt signal. A set unit interrupt bit corresponds to an address in a second RAM area. Interrupt status registers are read at the corresponding address in the second RAM area in response to the set unit interrupt bit. A set interrupt status bit corresponds to an address in a third RAM area. Interrupt cause bits are read at the corresponding address in the third RAM area in response to the set interrupt status bit, and detailed information is obtained about the interrupt. The interrupt is serviced in accordance with the detailed information.

Abstract: A method is provided for selectively inserting data, from a plurality of data sources, into a transmitted stream of information. The method makes a first selection to store data from at least a first and second source in a TX_OH memory. Then, the method makes a second selection, inserting the data stored in the TX_OH memory, into a transmitted stream of information. Typically, the information stream is a SONET/SDH protocol communication in a frame structure which includes overhead bytes. The provided method permits the overhead bytes of a received SONET/SDH communication to be selectively replaced with overhead bytes from either an FPGA or microprocessor source. An apparatus and system for arbitrating between multiple data sources in a communication transmission is also provided.

Abstract: A method of distributing timing information across a packet network 7. The method comprises generating timing signals at a master clock 8 at predictable intervals using a clock reference of a given frequency. The timing signals are broadcast or multicast to a plurality of slave clocks 9 over said packet network 7, preserving the timing signal intervals. At each said slave clock 9, the intervals between successively received timing signals are determined. A clock recovery algorithm is applied to said determined intervals to recover in substantially real time the original clock frequency. The local clock frequency of the slave clock is synchronised to the recovered frequency.

Abstract: A communications system includes a physical layer device (PLD) and a logical link device (LLD), each having respective send and receive interfaces being substantially identical to define symmetrical interfaces for the system. Accordingly, design and manufacturing is simplified compared to conventional systems. In addition, advantages are also provided in terms of loopback capability and packaging options. The PLD comprises a PLD send interface including PLD parallel information outputs, and a PLD receive interface including PLD parallel information inputs. Similarly, the LLD comprises an LLD receive interface including LLD parallel information inputs, and an LLD send interface including LLD parallel information outputs. Parallel communications channels connect the PLD information outputs to respective LLD information inputs, and connect the LLD information outputs to respective PLD information inputs.

Abstract: A multi-channel communication link generates a transport data protocol unit (TPDU) corresponding to each data packet received at a particular interface in a packet switching network. Each TPDU may comprise a data packet in accordance with a standard data transfer protocol and a modified header comprising a sequence number responsive to the relative position of the data packet within a data stream. The multi-channel communication link may inverse multiplex the various TPDUs for transmission across a plurality of asynchronous communication lines. A multi-channel communication link in accordance with the present disclosure may comprise a source first-in first-out (FIFO) buffer, a source line multiplexer/demultiplexer, a plurality of asynchronous communication links, a destination line multiplexer/demultiplexer, and a destination FIFO buffer. The present disclosure also provides a method for transferring data between computing devices via a virtual transport link.

Abstract: An apparatus for decreasing the hardware load from L2 switch MAC address learning for Ethernet-Over-SONET technology that uses VLAN, simplifying frame transmission between Ethernet and SONET, and improving the reliability of each device is disclosed. An Ethernet frame and SONET frame convertible interface part establishes a register that holds an Ethernet frame specific VLANID and SONET frame specific STS path ID in opposition, and a multiplexing part that multiplexes an Ethernet frame having a specific VLANID corresponding to a specific STS path ID that is held by a register among an input plurality of Ethernet frame VLAN ID's.

Abstract: A method (60; 70) for processing data packets allows the same hardware that is used in a traffic-forwarding path to add timestamps to the data, which allow accurate measurements to be taken. By adding this function in the forwarding equipment itself, the measurements can be taken in a true operational network, i.e., under actual usage conditions. Moreover, if multiple systems in the traffic path support this functionality, the value of the measurements is enhanced to enable end-to-end path guarantees. One exemplary embodiment (10) of the present invention uses synchronized clocks to provide timestamps for use in performance monitoring within an operational system. Synchronized clock signals can be used to accurately time stamp incoming and outgoing packets to provide performance measurement of traffic through the system under actual operating conditions.

Abstract: A method and an inter-chip communication port for supporting a concatenated type of a high order SDH/SONET signal, with processing Transport Overhead bytes (TOH) and Path Overhead bytes (POH) thereof, in a structure which comprises a group of chips, wherein each of the chips is capable of supporting a lower order SDH/SONET signal with processing its TOH and POH, while one of them named a master chip is operative to coordinate operation of the remaining chips named slaves so as to cause them working in accord as one unit.

Abstract: Methods and apparatus for assigning and/or storing routing metric values for routing traffic in a network having line terminating equipment connected by an line data communications channel (LDCC), so that routing traffic is sent across the LDCC. These methods and systems include a node and network that use the LDCC for transmitting routing information, such as Intermediate System to Intermediate System Level 2 routing traffic.

Abstract: A highly interleaved Time Division Multiplexing (TDM) format allows for high data density transfer for a given port at a communications controller. The port is coupled to a Time Slot Assigner (TSA) that will steer the provisioned timeslots of the interleaved TDM data to appropriate Serial Communication Controllers (SCCs), both which are internal to the communications controller. Entries in a Serial Interface Random Access Memory (SI RAM) that is coupled to the TSA and a lookup memory in a clock gapping function block located at a TDM interleaving circuit, are programmed by the communication controller to facilitate the TSA in steering the timeslots.

Abstract: A serial data signal having a predetermined sequence to indicate a start of a frame of data is received. The serial data signal is compared to a plurality of values. The plurality of values include the predetermined sequence and one or more values representing logical rotations of the predetermined sequence. A match signal is generated in response to the serial data signal matching one of the plurality of values.

Abstract: A method for high-speed signal framing of an incoming bit stream includes receiving the incoming bit stream in a datapath and locating a predetermined framing pattern in the datapath by finding a predetermined number of repetitions of a first portion of the framing pattern, bit aligning the bits in the datapath based on the predetermined number of repetitions of the first portion, priority encoding bits in a next cycle of the datapath, identifying a location of a second portion of the framing pattern, word aligning the priority encoded bits. The method includes declaring the bit stream as in frame. The incoming bit stream is over a datapath of at least 64 bits and the predetermined number of repetitions is at least three repetitions. Further, the incoming bitstream is a parallelized bitstream, the parallelization being performed in a shift register.

Abstract: In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.

Abstract: The present invention discloses a packet transmission device and a packet transmission system which can realize high-capacity communication. The transmission device transmits packets over a wavelength division multiplexing (WDM) link by mapping the packets into an optical path signal directly without any other medium such as an SDH path. The present invention also discloses a packet transmission device and a packet transmission system which can realize high-capacity communication over an SDH transmission link by mapping the packets directly into an SDH section payload without adding any VC path overhead in order to use the entire SDH section payload area.

Abstract: A method and apparatus are provided to transport private line traffic over an ATM network. A first plurality of TDM private line traffic links, such as T1 or E1 circuits, are multiplexed to create a first rt-VBR virtual circuit such that the bandwidth of the first rt-VBR virtual circuit is not limited. A second plurality of TDM private line circuits are multiplexed to create a second rt-VBR virtual circuit such that the bandwidth of the second rt-VBR virtual circuit is not limited. This may be done by AAL2 multiplexing with substantially large SCR, PCR and MBS values and the removal of T1 frames that do not contain data (that is, frames that contain only frame delimiters). The first and second rt-VBR virtual circuits are combined for transport over a link in the ATM network. An overload control process may be performed based on the ATM network link utilization.

Abstract: An integrated circuit device for use in providing packet service via multiple lower speed communications links and methods of operation of same is disclosed. The device may be capable of supporting Ethernet packet network service using a bonded group of time division multiplex or digital subscriber loop communications links by distributing the data traffic over the individual connections in the group. An embodiment of the invention may also include SONET/SDH compatible optical carrier framing, cross connect, and packet mapping functionality. It may include a telecom bus compatible interface for the connection of additional communications devices, and may incorporate an M13 multiplexer to permit the merging of multiple DS1 data streams into a single DS3 data stream. An embedded microprocessor core and embedded memory may permit an embodiment to support enhanced remote diagnostic, trouble reporting, traffic management, and software update capabilities.

Abstract: SONET and SDH signals are framed multiplex signals which are composed of multiplex units according to a respective specified multiplex hierarchy, such that smaller multiplex units are multiplexed in larger multiplex units and that the larger multiplex units are transmitted in frames. Compared to the multiplex hierarchy of SONET, the multiplex hierarchy of SDH has an additional level, namely the VC-4. A method of converting a SONET signal to an SDH signal is disclosed in which the multiplex units of the SONET signals are converted to corresponding multiplex units of the SDH signal, which are multiplexed into multiplex units of the additional hierarchy level. Monitoring functions are applied to both signals in accordance with the SDH multiplex hierarchy. In applying the monitoring functions to the SONET signal, the additional level of the SDH multiplex hierarchy is simulated by setting parameters to be monitored to default values.

Abstract: A plurality of data signals are separated into parallel bit streams with each parallel stream having a bandwidth characteristic such that the combined cumulative effect of all the individual bandwidths produces a spectral characteristic of the data signals that match the spectral high speed data characteristic of a twisted pair.

Abstract: Indirect digital subscriber line (DSL) service generally involves connecting conversion equipment that converts between DSL service delivered to a customer premises and DSL service that connects back to a data network. Indirect DSL service may be delivered on the same loop to the customer premises that also carries a native 0-4 KHz POTS interface. For larger deployments, the conversion equipment may include inverse multiplexing to combine multiple links back to the data network to support DSL service. Furthermore, the conversion equipment may include functions to digitize the POTS service. Aggregating DSL data from multiple customers and/or digitizing POTS service that may be multiplexed with the DSL data allows for significant pair gain opportunities.

Abstract: A method and system for transporting traffic in a packet-switched network segments high priority pass-through traffic from low priority pass-through traffic. The high priority pass-through traffic is transmitted on an egress link preferentially over the low priority pass-through traffic and ingress high priority local traffic. The ingress high priority local traffic is transmitted on the egress link preferentially over the low priority pass-through traffic.

Abstract: The invention concerns a technology for detecting a frame synchronous pattern comprising:

Abstract: A heterogeneous network consists of an OTN-type sub-network and an SDH type sub-network. The sub-networks are interconnected by an interconnection node network element (NE) which has a first interface (O1-On) connected to OTN-type sub-network (OTN) and a second interface (S1-Sn) connected the SDH-type sub-network (SDH). Management information messages from the data communication channels of received SDH signals and management information messages from the general communication channels of received OTN signals are extracted in the corresponding interfaces. All messages are then fed via a LAN to a common routing engine (R), which routes the management information messages between the OTN and SDH sub-networks.

Abstract: A novel overhead engine for processing overhead blocks (e.g., SONET/SDH overhead rows of 3 bytes, etc.) in a telecommunications node is disclosed. Some embodiments of the present invention advantageously employ a single instance of logic to process overhead blocks for all of a node's input ports. The illustrative embodiment comprises a plurality of multiport cell processors for generating output overhead cells based on input overhead cells, a dispatcher for dispatching input overhead cells to the multiport cell processors, a plurality of aggregators for combining output overhead cells into output overhead blocks, and a scheduler for controlling the order in which output overhead blocks are sent to output processors associated with a node's output ports.

Abstract: In a data communication circuit, data is multiplexed onto a communication link through multiple multiplexer stages and demultiplexed from the communication link through multiple demultiplexer stages in order that a clock signal applied to each multiplexing circuit need only be precisely distributed to a limited, high frequency portion of the circuit. Each circuit is clocked by a multiplying delayed locked loop bit clock generator. Where the number of parallel bits in the signal between the two stages is greater than two, the higher frequency stage coupled to the communication link is clocked by an N-phase overlapping clock. In the case of a multiplexer, the intermediate frequency signal is enabled in the higher frequency data multiplexer by concurrence of two clock phases.

Abstract: In addition to a main monitor/control module, sub-monitor/control modules are provided, which monitor the operating conditions of transmission sections in real time through a CPU bus. The main monitor/control module collects monitor data from each sub-monitor/control module at a given timing through a LAN and processes the monitor data collected.

Abstract: A multi-stage switching network that can hitlessly reconfigure itself comprising a controller that controls each stage separately. The controller designates the paths through each stage according to the set of paths currently active. If the set of paths changes, the controller sends a new set of paths to the first stage while using the old set of paths for the second stage during a first frame. On the next frame, the controller causes both stages to use the new set of paths.

Abstract: Circuitry combines a plurality of digital communication channels in a telecommunication system with reduced hardware requirements. The circuitry accumulates samples of the input communication channels in a register using an adder. The bit width of the connection lines between the register and the adder may be selected considering the bit width and number of input communication channels, such that minimal bit widths are provided.

Abstract: A method and apparatus for generating massive interrupts in random access memory (RAM) are provided, comprising receiving and storing Time Slot network (TS Net) data frames comprising switching event information in a first RAM area. Compare operations are performed among prespecified ones of the TS Net data frames. Unit interrupt bits are set in a corresponding location of a second RAM area in response to detected bit differences resulting from the compare operations. Interrupt status bits are set in a corresponding location of a third RAM area in response to set unit interrupt bits. Massive interrupt signals are generated in response to set unit interrupt bit.

Abstract: A telecommunications node architecture is disclosed that facilitates the loop-back of a signal in an add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: A composite add/drop multiplexor architecture is disclosed that facilitates the loop-back of a signal in a composite add/drop multiplexor (e.g., a SONET/SDH node, a dense wavelength division multiplexed node, etc.) that uses automatic protection switching.

Abstract: The invention provides a termination equipment for use in a data network such as a SONET data network. The termination equipment has a data input for receiving a plurality of data frames, each data frame including an overhead component and a payload component. An overhead processor performs a termination operation on the overhead components of the data frames. The overhead processor has a control input to receive control information designating at least one data slot of the overhead component to be preserved during the termination operation. The overhead processor is responsive to the control information to perform a selective termination operation on the plurality of data frames, preserving data in the at least one data slot designated for preservation. The selective termination operation produces an output data stream containing payload data from the payload components of the plurality of data frames and data from the at least one data slot designated for preservation.

Abstract: A multiple device management communication mechanism uses the normally empty <GENERAL BLOCK> field of single destination address-based management communication TL1 protocol command structure to selectively insert a substitute recipient address, and thereby selectively transmit a management message from a host site over a communication link to any of plurality of remote subsidiary devices that would otherwise be remotely unaddressable.

Abstract: An optical receiver unit is connected to each of a work optical line and a protection optical line, and after an optical signal is converted to an electrical signal, only the overhead of the signal is extracted. Furthermore, bytes accommodated in the overhead are demultiplexed. K bytes are transferred to both an APS processing unit and a mismatching judgement unit. The mismatching judging unit judges whether or not a WTR, DNR, RR, etc. are set in the K1 byte received from the opposite station, compares the mode of the opposite station with the mode of its own station, and detects a mismatching between the modes of the opposite and own stations. The result of the detection is transferred to the APS processing unit, and if there is a mismatching, the mismatching is solved.

Abstract: A multi-mode framer/pointer processor apparatus can selectively accommodate one or more OC-192 data streams and can also selectively accommodate an OC-768 data stream.

Abstract: The system for broadband data payload conversion functions to efficiently convert broadband data between two sets of data formats. In particular, this software system converts between AUG/AU3/VC3 clear channel payloads and AU4/VC4/TU3/VC3 clear channel payloads in an efficient manner, which also complies with the industry standard data formatting requirements. The present system implements an efficient data format conversion process that uses existing circuitry and can effect the data format conversion with only a few bytes of delay instead of an entire frame of delay as is typically found in existing systems. This is accomplished by manipulating the format conversion to simplify the format conversion process.

Abstract: A single group of signals interfaces a computer system to either an analog display or a digital display. A video signal in digital format and a video signal in analog format are both supplied to a circuit that multiplexes the digital signal and the analog signal, generating an appropriate output signal for the display, either analog or digital, that is coupled to the computer system. In one example, the signal connector interfaces the computer system to either an analog CRT display or a digital FPD display. The multiplexer multiplexes the analog signal and the digital signal supplied by the computer system and generates an output signal that is suitable for the CRT display or the FPD display, depending on the type of display coupled to the computer system.

Abstract: A method of multiplexing a plurality of virtual channel connections into a single channel is disclosed. Each of the virtual channel connections is made up of a plurality of minicells within an AAL2 protocol. The user to user indication field of the minicell is used in addition to the connection identifier to identify each of the virtual channel connections. A method is also disclosed for demultiplexing virtual channel connections from a single channel into AAL2 minicells.

Abstract: Method and arrangement for multiplexing a multiplicity of digital data streams to form a digital overall data stream, as well as a method and arrangement for demultiplexing a digital overall data stream to form a multiplicity of digital data streams. When multiplexing data streams (DS), the data streams are grouped to form digital intermediate data streams (ZDS). The grouping is carried out in such a manner that identical data streams (DS) are jointly grouped to form an intermediate data stream (ZDS) and different data streams (DS) are grouped into different intermediate data streams (ZDS). Measures for error identification and/or error correction of the intermediate data stream (ZDS) are carried out for the intermediate data streams (ZDS). Finally, the intermediate data streams (ZDS) are grouped to form the overall data stream (GDS).

Abstract: An OTN cross-connecting apparatus (100) constituting a second network is arranged on a boundary to a first network. The OTN framer (220) of a client interface card (200) mounted on the OTN cross-connecting apparatus (100) stores an SDH/SONET signal into an OTN frame on a non-interfering manner and, using the overhead of the second network OTN frame, controls and manages the apparatus and the network.

Abstract: An FPGA is described using optical waveguides for routing signals through the FPGA. The routing is controlled electrically. Either coupling waveguides or resonant disks can be used for routing the optical signals. Lookup tables convert optical input signals to electrical signals for selecting values in the lookup table.

Abstract: An overhead processor processes overhead bytes in a stream of Synchronous Optical Network (SONET) frames in multiple levels. In one embodiment, the overhead processor includes three stages. A first stage provides access for external processing of a first set of overhead bytes in the stream of SONET frames. A second stage is programmable to process a second set of overhead bytes in the stream of SONET frames. A third stage processes a third set of overhead bytes in each frame in the stream of SONET frames.

Abstract: The invention relates to a device and a method for parallel signal dividing and signal processing in multiplex devices with a high ordinal number. The advantage of the inventive nth level multiplex device lies in the fact that n transmission-end signals are divided cyclically among n/m mth level multiplex devices at a second multiplex device level, said second multiplex device level enabling the n/m mth level multiplex devices to be processed parallel to n/m partial signals and these n/m partial signals to be cyclically and sequentially processed into one signal by a parallel serial converter at a first multiplex device level. The resulting signal already has the arrangement of channels and bytes prescribed by the SDH format. The sorting process at the first multiplex device level, which is demanding in terms of memory, is therefore no longer necessary.

Abstract: A national broadband network is based on fiber optic technology and scaled to cover a wide area, such as the contiguous lower United States. The network provides a high data rate interface for each subscriber and supports all the functions of the current telephone, Internet, and cable TV networks, with sufficient excess capacity to support future applications. Signals from several thousand subscribers are multiplexed on a single fiber pair connected to an intelligent switching center. Telephone central offices (COs) become multiplexing centers rather than switching centers, and the number of switching centers required to cover the nation is greatly reduced. Approximately 500 switching centers are interconnected by an optical backbone. Physical layer connections are established through the backbone between each pair of switching centers. Multiple ATM and/or STM connections are carried within each of these physical layer connections.

Abstract: Method and systems for improving utilization of high-speed time division multiplexed communications links at a signal transfer point are disclosed. A multi-port link interface module terminates two or more high-speed TDM links and generates internal data. Data received on one high-speed communications link is combined with the internal data used to fill outbound timeslots in an outgoing high-speed link. The data may include signaling data, bearer data, or signaling and bearer data.

Abstract: A telecommunications node architecture is disclosed that comprises multiple add/drop multiplexors that are interconnected in a novel topology to enhance the reliability of the telecommunications network. Furthermore, the architecture of the illustrative embodiment ameliorates the well-known “add-before-drop” problem.