Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows for more. In a supplemental or alternate embodiment, at least one virtual bus is limited to having no devices on it. A non-transparent bridge is provided on at least one of the special buses for providing cross-border routing of packets from one root domain to another root domain. The number-of-devices limitation placed on the special bus reduces the number of bits needed in a corresponding Device identifying field of a destination ID Tag to 4 or less, this integer number being smaller than the prescribed 5 bits called for by the PCI-Express standard for addressing the maximum of 32 devices per bus.

Abstract: A system and method for reliably transmitting large amounts of data over a high speed network with large latency, such as a communication satellite based network. A transmitting device transmits data transfer units (DTUs) to one or more receiving devices. The transmitting device forms and transmits burst consisting of reliably delivered sets of multiple DTUs. Both the transmitting device and the receiving devices process multiple bursts in parallel, such that subsequent bursts can be transmitted and received prior to the correct receipt of a previously transmitted burst at all of the receiving devices, and/or prior to receipt of a status report at the transmitting device regarding a previously transmitted burst. The transmitting device operates to transmit subsequent bursts even before the receipt of a status information regarding a previous burst, and the receiving devices process subsequently received bursts while awaiting retransmission of a lost or damaged DTU from a previous burst.

Abstract: A method and apparatus for accessing, controlling and utilizing a network communication medium. Various aspects of the present invention may comprise a first networked device with power-save capability. The first networked device may acquire control of a communication medium utilizing a medium access protocol, which may be contention-based. The first networked device may utilize the communication medium to communicate information to a second networked device. The first networked device may transfer control of the communication medium to the second networked device, whereby the second networked device may control the communication medium without having to acquire control of the communication medium by utilizing the medium access protocol. The second networked device may utilize the communication medium to communicate information to the first networked device while maintaining control over the communication medium.

Abstract: In existing standards for packet data communication over enhanced cellular networks, for a subscriber having a static address, the network relies on the terminal to provide the static address. Consequently, the terminal needs to know (be programmed with) its own static address and typically the address of a home agent element of the network. To eliminate the attendant need to provision such address data in the mobile station, the static address is stored in a node of the network, and the network assigns that one address to the mobile station, every time when the subscriber requests packet data service, for example, using a mobile IP (MIP) type address assignment procedure. The address assignment operation may also provide the home agent address to the station.

Abstract: A packet detection technique is disclosed in which an average correlation signal is generated representative of the match between a repetitive sequence of symbols; an average power signal is generated representative of the average power in the sequence of symbols; a scaled magnitude of the average correlation signal scaled by a first predetermined scale factor is produced; and one of the average power signal and scaled magnitude of the average correlation signal are multiplied by the second scale factor and compared to determine whether there is a match between a repetitive sequence of symbols.

Abstract: A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus; and an internal register in which is set interface information for specifying signal types of the interface signals output from the interface circuit. The interface circuit includes first to Nth interface circuits (N is an integer greater than one), and each of the first to Nth interface circuits generates an interface signal of a signal type according to the interface information set in the internal register.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: The present invention relates to a method and arrangement for controlling dataflow on a databus, especially for avoiding reception problems by a receiver unit. The databus connects at least one receiver unit to one or several transmitter units. The method comprises the steps of transmitting by the receiver unit on the databus a control data sequence to be received by the transmitting units, which alter transmission mode.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: The present invention relates to a mobile packet communication apparatus for supplying a terminating service to a mobile terminal and a packet communication control method employed for the communication network. In the case of the conventional techniques, an original side home gateway node cannot identify a path to a destination gateway node from the original IP packet header. It is thus impossible to supply any terminating service to a dynamic IP address mobile terminal. Under such circumstances, the present invention uses a dynamic DNS and a mobile terminal is provided with a dynamic DNS client function. When an IP address is allocated to a mobile terminal, therefore, the mobile terminal sends a DNS update message to the target subscriber node. The message includes a dynamically allocated IP address. Receiving the DNS update message, the subscriber node adds the home gateway node identifier (network identifier) of the mobile terminal to the message parameters to be sent to the dynamic DNS.

Abstract: The apparatus, method and system embodiments of the present invention provide for maintaining call control at a gateway mobile switching center (MSC), for roaming mobile units, utilizing a packet network or link, such as an ATM link. The preferred system embodiment includes a gateway MSC, a serving MSC, and a base station having a wireless link with the roaming mobile unit. The gateway MSC includes a protocol handler for voice (PHV).

Abstract: The present invention supports a message protocol on a wireless communication network between the access gateway and the proxy session initiation server. Upon disruption of a communication session with a mobile station, an information packet indication disruption of the communication session is transmitted from the access gateway to the proxy session initiation protocol server. Upon receipt of the information packet, the proxy session initiation server initiates a resource release procedure freeing network resources supporting the communication session. The proxy session initiation server releases the resources and transmits an information packet to the serving session initiation server, which also initiates a release procedure. Answer and acknowledgement messages are also sent in response to the release request and/or the release of resources.

Abstract: A system interface having: a packet switching network; a cache memory; and a plurality of directors. One portion of such directors is adapted for coupling to a host computer/server and another portion of the directors is adapted for coupling to a bank of disk drives, the plurality of directors and cache memory being interconnected through the packet switching network. Each one of the directors is coupled to a crossbar switch. The cross bar switch is directly connected to at least two other ones of the cross bar switches networks and indirectly connected to of other ones of the crossbar switches through the at least two directly connected crossbar switches.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A port adapter for connecting zero or more network interfaces to a host system having a SPI-4 bus is disclosed. The port adapter comprises zero or more network interfaces; a SPI-4 bus coupled to a host system to provide a communication channel between the host and the network interfaces; a control bus coupled to the host system for controlling and monitoring the port adapter; and interface logic that interfaces the SPI-4 bus and the control bus to the network interfaces. Methods are provided for selecting and using one of a small plurality of different packet formats for various networking technologies, so that the port adapter can hide details of the technology that it handles from the host system, and for operating the host system's SPI-4 bus at one of several speeds based on bandwidth requirements of the port adapter.

Abstract: The format of the transmission of isochronous data packets via the IEEE 1394 bus is defined in the IEC 61883 Standard. A bus packet used to transmit the data has a header at the beginning, which header describes the format of the bus packet. This is then followed by an isochronous data format header, which defines the data format of the useful data in the useful packet. The invention is concerned with the problem of compiling a bus packet for transmission via the 1394 bus. In the case of the invention, this is done in such a way that when the isochronous data transmission is set up, the isochronous data format header prescribed by the application is written both to a special register that is provided and to the buffer memory for the bus packets and the useful data are attached thereto. As a result, it is then possible that a data transmitting section has to take the data to be transmitted, including the isochronous data format header, only from the buffer memory.

Abstract: For transmitting delay-critical data in a digital, time division form in an additional channel of a cable television system, the slots of the channel are further divided into smaller mini slots, for the indication of which the same cyclic indication is used as with which the superframes controlling the use of the channel indicate the original slots. A method based on mini slots is compatible with DAVIC 1.0 and 1.1 specifications.

Abstract: An apparatus and method for connecting a plurality of computing devices, e.g. web servers, database servers, etc., to a plurality of storage devices, such as disks, disk arrays, tapes, etc., by using a stream-oriented (circuit oriented) switch that has high throughput, but that requires non-negligible time for reconfiguration is disclosed. An example of such stream-oriented switch is an optical switch. The preferred embodiment comprises a plurality of communication ports for connection to servers, and plurality of ports for connection to storage devices. The system decodes the requests from the computing devices and uses this information to create circuits, e.g. optical paths in embodiments where the stream-oriented switch is an optical switch, through the stream-oriented switch. The system uses these circuits to route traffic between the computing devices and the storage devices.

Abstract: A data processing system in accordance with an exemplary embodiment is provided. The data processing system includes a first host device operably coupled to a first PCI communication bus wherein the first host device substantially only performs tasks associated with facilitating communication through the first PCI communication bus. The data processing system further includes a first processing device operably coupled to the first PCI communication bus. Finally, the data processing system includes second and third devices both operably coupled to the first PCI communication bus. The second device is configured to request authorization from the first host device to transmit a first message through the first PCI communication bus, wherein the second device transmits the first message to the third device upon receipt of the authorization from the first host device even if the first processing device is not operable.

Abstract: A method includes extracting packets from within a received frame, generating digests of the extracted packets, and hashing the generated digests.

Abstract: A system and method is disclosed for providing concurrent data transmissions in a wireless communication network. The invention comprises a register unit within a base transceiver station that prepares data packets to be transmitted to mobile stations within a plurality of cell sectors. The register unit identifies the cell sector destination of each data packet in a first data call and sends the data packet to a buffer associated with the cell sector destination. The buffers store their respective data packets for each cell sector in a first subframe of a data frame. The buffers send their respective data packets within the first subframe to their respective antennas. The data packets for each cell sector are then concurrently transmitted during the first subframe. Data packets of a second data call are transmitted during the second and third subframe so that two data calls are concurrently transmitted.

Abstract: A method of processing a frame of a CPU intensive communications protocol includes disabling per frame interrupts of a CPU; enabling a periodic interrupt handler to interrupt the CPU upon an interrupt period; and upon an interrupt of the periodic interrupt handler, determining and processing a frame received in the interrupt period. Further, a frame sent acknowledgment stored in the interrupt period may be processed during the interrupt. A method of processing the transmission of frames of a CPU intensive communications protocol includes, when no MSU frame is queued for transmission, sending FISU frames that each point to itself; and if a MSU frame is queued for transmission, updating the MSU frame to point to a new FISU frame, updating a current FISU frame to point to the MSU frame, and sending the current FISU frame, the MSU frame and the new FISU frame.

Abstract: Methods and apparatus are disclosed for use in an electronic system where data is transmitted over signaling conductors from one electronic component to another using strobe signals accompanying the data. The edge or transition of the strobe signals identifies when, in a window of time, the receiving electronic component should latch the data. In many such systems, data is transmitted over the signaling conductors in the form of a plurality “beats”, of data, proper timing to latch each beat of data being identified by a transition of the strobe signal. Faults in components or errors in transmission must be handled. The present invention discloses apparatus and methods to communicate conditions relevant to data transmitted without requiring additional signaling conductors. The present invention discloses selecting a message from a plurality of messages, encoding the selected message, and transmitting the encoded message on existing strobe lines to communicate the condition encountered.

Abstract: Methods, apparatus, and articles of manufacture for efficiently handling incoming network traffic by preventing protocol stack overruns and minimizing packet latency are disclosed herein. Embodiments of the present invention monitor the level of a protocol stack's packet queue, and, in response to an increase in the level of the packet queue above an initial threshold value, disable the generation of receive interrupts from the communications interface, disable automatic packet indication of packets by the device driver to the protocol stack, and identify and indicate new incoming packets to the protocol stack at a rate equal to or less than the rate at which packets are being processed by the protocol stack. In addition, in response to a decrease in the level of the packet queue below an exit threshold value, the generation of receive interrupts and the automatic indication of packets to the protocol stack may be re-enabled.

Abstract: A method and apparatus for moderating packet ingress interrupts. A network interface includes a packet timer and an absolute timer or absolute counter. The packet timer functions to minimize packet latency during periods of low packet ingress at the network interface. Each of the absolute timer and absolute counter functions to minimize CPU load and packet latency during periods of high packet ingress at the network interface.

Abstract: A system includes a multithreaded processor. The multithreaded processor includes a plurality of microengines, a memory controller, a first bus interface and a second bus interface. The second bus interface includes a first-in-first-out memory with a plurality of elements to store packet data and packet status. The system also includes a system bus coupled to the first bus interface and a network bus coupled to the second bus interface.

Abstract: A communication system, network interface and communication port is provided that includes a media local bus. The local bus is connected between a controller and one or more multimedia devices located within a node of the communication system. The controller periodically broadcasts sync signals to the source device, or devices, to synchronize data transmission partitioned into time slots. Each time slot represents is dedicated to a particular data type. Thus, time slot 1 can accommodate packetized data, time slot 2 can accommodate synchronous data, time slot 3 can accommodate control data, and time slot 4 can accommodate isochronous data. Various combinations and variations of those time slots can occur where fewer than four data types can be present within a frame or all four data types can be present. The local bus includes a signal line and one or more data lines.

Abstract: A method and apparatus for moderating packet ingress interrupts. A network interface includes a packet timer and an absolute timer or absolute counter. The packet timer functions to minimize packet latency during periods of low packet ingress at the network interface. Each of the absolute timer and absolute counter functions to minimize CPU load and packet latency during periods of high packet ingress at the network interface.

Abstract: A method of processing a frame of a CPU intensive communications protocol includes disabling per frame interrupts of a CPU; enabling a periodic interrupt handler to interrupt the CPU upon an interrupt period; and upon an interrupt of the periodic interrupt handler, determining and processing a frame received in the interrupt period. Further, a frame sent acknowledgment stored in the interrupt period may be processed during the interrupt. A method of processing the transmission of frames of a CPU intensive communications protocol includes, when no MSU frame is queued for transmission, sending FISU frames that each point to itself; and if a MSU frame is queued for transmission, updating the MSU frame to point to a new FISU frame, updating a current FISU frame to point to the MSU frame, and sending the current FISU frame, the MSU frame and the new FISU frame.

Abstract: A method and system for generating multiple self-ID packets that are used for mapping a node topology is disclosed. The node topology is based on a computer system comprised of a high performance serial bus and a plurality of nodes coupled to the serial bus. Each node further includes an identification packet that is utilized for self-identifying itself on a network. In particular, a plurality of self-ID packets associated with the hardware actually present on the bus as well as a plurality of virtual nodes that are not actually present are generated during a self-ID process. Then, these self-ID packets are forwarded over the serial bus to identify themselves to other remaining nodes in the network. Thereafter, a topology mapping table from all of the self-ID packets is generated.

Abstract: A method for data streaming by a SCSI target includes transmitting a data packet information unit in a Packetized SCSI Protocol Data In phase. The SCSI target also generates a signal during the Packetized SCSI Protocol Data In phase to indicate whether a header packet information unit or another data packet information unit is to be transmitted next in the Packetized SCSI Protocol Data In phase.

Abstract: A bus arbitration system and a data transfer arbitration method, comprising (a) receiving bus requests from two or more master devices and arbitrating access to an address/control bus according to a predetermined arbitration algorithm, (b) receiving an access command packet containing information for data transfer preparation from the master device through the address/control bus in the order determined as a result of the arbitration and transmitting the received access command packet to a corresponding slave device, (c) receiving notification of transfer preparation completion of corresponding data from the slave device, (d) informing the master device of the start of data transfer, and (e) transferring data through the data bus. The slave devices may be high-speed devices such as synchronous DRAM (SDRAM). Bus efficiency is improved, as separate master devices can simultaneously and separately control the address/control bus and the data bus.

Abstract: A base station subsystem (BSS) and method is provided that handles an increase in traffic volume which temporarily overloads at least one terrestrial link in an IP network by gracefully downgrading the transmission rate of one or more calls. More specifically, the BSS includes a base station transmitter (BTS), an IP gateway and an IP network which passes at least one packet based call on a terrestrial link between the BTS and the IP gateway. The BTS and IP gateway each include an end-point having a buffer for measuring a delay in passing the at least one packet based call through the terrestrial link of the IP network and for downgrading a service when the delay as measured by one of the buffers exceeds a predetermined value.

Abstract: In accordance with the present invention a method is provided for encoding connection ownership information in the sequence number field of an outgoing TCP/IP data packet header. That connection information includes the network layer address of the processor node to which the packet is associated. With such an invention, the connection registration database is only updated after 32 megabytes have been transferred across that connection. Because fewer data packets are being registered in the connection registration database, sufficient time is allowed for registering other connections in background operations. Further, connections that do not send more than 32 megabytes of data never need to be registered.

Abstract: A bridge device, for coupling a parallel bus to a packet network, includes a bus interface adapter, coupled to the parallel bus so as to receive bus cycles from a master device on the bus. An outbound packet register, having a bus address in an address space of the bus, is adapted to store an outbound network address header and payload data written to the bus address of the register by the master device in one or more of the bus cycles received by the bus interface adapter. A network interface adapter is coupled to the network so as to transmit over the network an outbound packet containing the outbound network address header and payload data from the register, to a target device on the network specified by the network address header.

Abstract: A network-provisioning data generating method, by which manual data registration can be prevented so that correct network provisioning data can be collected and registered in real time, and a transmission device, which is constituted according to the generated network structure, are provided.

Abstract: An Internet network based telephone call forwarding system comprising a home unit to which a user's telephone calls are directed and a remote unit to which a user's telephone calls are forwarded, wherein the home unit has an incoming line connectable to a telephone network and an outgoing line connectable to an Internet network and the remote unit has a line connectable to the Internet network, wherein the home unit is operable to forward calls directed to the home unit on the incoming line to the remote unit on the outgoing line via the Internet network.

Abstract: In a coordinated computer system for encoding, transmitting, and decoding a series of data packets such as audio and/or video data, there may be a skew between the clock used by an encoder and the clock used by a decoder. In a method and device for compensating for this clock skew, the decoder calculates a drift metric representing the clock skew and modifies the time stamps of the data packets based on the drift metric. The decoder also performs a sample rate conversion on the digital data, in order to compensate for the clock skew between the encoder and decoder.

Abstract: The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. A packet diagnosis circuit diagnoses self-ID packets sent from many nodes, and detects the node that ought to become the isochronous resource manager (IRM) in accordance with IEEE 1394. The ID of that node is held in an IRM ID register. Firmware can discern the ID of the IRM by reading this register. If C and L bits of the self-ID packet of a node are both 1, the ID of that node overwrites the contents of the IRM ID register. Whether or not the system is within a self-ID period is detected and any packet that is sent in within that self-ID period is assumed to be a self-ID packet.

Abstract: A radio interface connects a mobile terminal device to a radio network. The mobile terminal device also has a communication interface for coupling to an external computer device, such as a notebook. The communication interface serves to provide real-time transmission of communication data or communication signals between the computer device and an input/output device of the mobile terminal device.

Abstract: An apparatus for classifying a packet within a data stream in a network includes a state machine into which certain functionality has been hardwired. Specifically, the state machine defines in hardware a predetermined number of states and a predetermined number of transitions between these states. The state machine outputs a state value which is indicative of the classification of a package. A programmable memory is coupled to the state machine, and stores transition parameters for each transition of the set of transitions, thus allowing the hardwired states and transitions to be programmable.

Abstract: A configuration access request packet is transmitted from a first hub agent onto a hub interface. The configuration access request packet comprises an address formatted in accordance with a peripheral component interconnect (PCI) specification. The configuration access request packet is received from the hub interface by a second hub agent.

Abstract: A digital information processing system ensures illegal-copy protection of video and audio signals without changing the structure or format of a stream of multiplexed video, audio and data packets. A packet demultiplexer selects packets from a packet stream according to the packet identifiers (PID) of the packets. The packet demultiplexer has a first output port electrically connected to video and audio signal decoders, and a second output port for digital processing such as storage. When a selected packet is a video or audio packet, the packet demultiplexer outputs the selected packet through the first output port. When the selected packet is a data packet, and packet demultiplexer outputs the selected packet through the second output port.

Abstract: Data which is transmitted over the internet or other transmission networks is first divided up into individual information packets, transmitted and then reassembled into useful data after reception. Parity packets are included in with the information packets in the transmission of data in order to enable the regeneration of any information packets which were lost or damaged during transmission. The grouping of information packets and parity packets derived therefrom is termed a chunk. Chunk arrangements to recover from all cases of single and double lost packets are disclosed. Bursts of lost packets are recovered by interleaving the transmission of packets from different chunks. If the recovery is not successful then retransmission occurs in a manner similar to TCP.

Abstract: A method for signaling an Integrated Messaging System (IMS) on an Internet Protocol (IP) based network to deposit a message, including the steps of sending a Session Initiation Protocol (SIP) SIP INVITE request to the IMS indicating a message deposit action; receiving a corresponding SIP message from the IMS agreeing to participate in the message deposit action; and sending an SIP acknowledge message to the IMS confirming receipt of the corresponding SIP message; and depositing the message in a destination mailbox. A method of signaling an IMS on an IP based network to retrieve a deposited message, the method including the steps of sending a SIP INVITE request to the IMS indicating a message retrieval action; receiving a corresponding SIP message from the IMS agreeing to participate in the message retrieval action; sending an SIP acknowledge message to the IMS confirming receipt of the corresponding SIP message; and retrieving the deposited message from a mailbox corresponding to known account information.

Abstract: A store-and-forward network switch uses an embedded dynamic-random-access memory (DRAM) packet memory. An input port controller receiving a packet writes the packet to the embedded packet memory. The input port controller then sends a message to the output port over an internal token bus. The message includes the row address in the embedded packet memory where the packet was written and its length. The output port reads the message and reads the packet from the embedded memory at the row address before transmitting the packet to external media. Packets are stored at row boundaries so that DRAM page-mode cycles predominate. Only one packet is written to each DRAM row or page. Thus the column address is not sent between ports with the message sent over the token bus. A routing table can also be included in the embedded DRAM.

Abstract: In a header decompression apparatus 709, a header decompressor 703 refers to reference information stored in a reference information manager 707 to decompress a compressed header of a packet received by a packet receiver 704. An error detector 702 detects a CRC error in the packet with its header decompressed by the packet receiver 704, and outputs only a correct packet. A successive error counter 705 counts the number of successive errors detected by the error detector 702. A successive decompression success counter 706 counts the number of decompression successes that successively appear. By referring to these counted numbers, an update request unit 708 transmits an update request to a transmitting side as required. A reference information manager 707 manages the reference information for header decompression. With this structure, the header decompression apparatus can request update of the reference information based on the state of the error.

Abstract: A method for detecting an erroneous IF board mounting in a transmission device which can be employed even when one-to-one correspondence is not established for slots on a transmission device and normally mounted IF boards determines when the transmission device is activated, for each of transmission channel interfaces, whether or not a plurality of types of packages having different transmission speeds are mounted. When a plurality of types of packages having different transmission speeds coexist at one of the transmission channel interfaces, it is concluded that all the packages in the transmission channel interface are erroneously mounted.