Abstract: A frequency generator (100) takes a signal source (clock or carrier) (101) and generates a edge encoded direct digital modulated differential output signal (110). The differential signal (110) is applied to a frequency extension quadrature generator (FEQG) (112). The FEQG (112) includes a fractional differential wavelength delay locked loop (DLL) (280) and a frequency multiplier (240). The DLL (280) generates a control voltage (214) with which to control delays of the edge encoded modulation signal (110). A frequency extended quadrature function is applied to the periodic steady state input signal with edge encoded modulation (110), to provide the output signal set 113.

Abstract: A system for transmitting data includes a transmitter module, a receiver module and a channel provided with a flow control link between the transmitter and receiver modules. The channel provides a first control signal from the transmitter module to the receiver module, and a second control signal from the receiver module to the transmitter module for initiating data transmission. The transmitter or receiver module includes a synchronizer for synchronizing the first and second control signals.

Abstract: Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal.

Abstract: A phase/frequency detector module allows operation as either a phase locked loop or a frequency locked loop. As a phased locked loop (PLL), the phase detector module is configured to decode phase differences between a reference signal and a voltage controlled oscillator (VCO) signal into phase correction signals that are updated at the rate of the VCO signal. An accumulation of the phase correction signals is implemented to form an accumulated phase error signal, which is then sampled at a lower rate than the VCO signal to accommodate slower components of the PLL, such as a digital to analog converter (DAC). As a frequency locked loop (FLL), the phase detector module is configured with frequency counters, so that frequency error may instead be detected. Any reduction of gain caused by the frequency counters is inherently equalized by the phase detector module.

Abstract: To improve the performance of DSL modems, a DSL duplexing ratio for a new communication is selected according to the communications needs of an application. A required upstream and downstream bit rate for application communications is determined. From the ratio of these bit rates, a desired duplexing ratio is calculated. The operation of the modem is then adapted to choose a duplexing ratio that approximates the desired duplexing ratio for the application. To optimize modem operation, the size and position of the upstream and downstream bandwidths used for transmission are intelligently selected when the bit rate necessary for making the transmission is less than the total available bandwidth provided by the chosen duplexing ratio. By intelligently selecting a minimum number of subcarriers for Digital Multi-tone (DMT) signal transmission, a reduction in line driver power consumption is effectuated.

Abstract: An encryptor/decryptor which receives a continuous parallel data stream either in a single-ended TTL or a Low Voltage Differential Signaling format. The encryptor/decryptor selectively encrypts or decrypts the incoming data stream, using an LVDS encryptor/decryptor and then outputs the data stream in either a LVDS or TTL parallel format.

Abstract: A repeater and method for an ATSC terrestrial digital TV broadcasting service.

Abstract: A method and an apparatus for frequency synthesizing are provided for a wireless communication system. In a frequency synthesizer, a phase lock loop (PLL) circuit generates a first elemental frequency based on a reference frequency and a unity frequency. A first division module then divides the first elemental frequency to generate a second elemental frequency. A second division module divides the second elemental frequency a multiple of times to generate the unity frequency and a plurality of intermediate frequencies each having an exponential ratio to the unity frequency by a power of two. A second mixer is provided to mix one of the intermediate frequencies with the unity frequency to generate a step frequency, and a first mixer mixes the step frequency with one of the first and second elemental frequencies to generate an output frequency having a variety covering all frequency bands in an Ultra-Wide-Band (UWB) spectrum.

Abstract: A method and system for synchronizing an input signal for a power system. The method comprises: extracting from the input signal, three substantially equidistant samples from a fundamental component of the input signal; determining a frequency (f1), an amplitude (A1), and a phase-difference (?Diff) of the input signal from the three equidistant samples and a tracking signal corresponding to a steady-state of the fundamental component of the input signal characterized by a frequency (fTS) and an amplitude (ATS) with a phase-difference that is the phase angle between the tracking signal and the input signal; and generating and outputting a frequency, amplitude, and phase-difference signals corresponding to the determined frequency (f1), amplitude (A1), and phase-difference (?Diff) of the input signal to one or more components of the power system.

Abstract: Provided is a frequency synchronizing apparatus and method that can synchronize frequencies between receiving signals and transmitting signals by extracting a carrier error and sampling timing error information in a synchronization process of the receiving signal from a main transmitter or another repeater and reflecting them in the transmitting signal in an on-channel repeater. The apparatus includes a carrier recovery means for compensating a carrier frequency error of a receiving signal; a timing recovery means for compensating a sampling timing error of the receiving signal; a carrier error reflecting means for reflecting the carrier frequency error extracted from the carrier recovery means to a transmitting signal; and a timing error reflecting means for reflecting the sampling timing error extracted from the timing recovery means to the transmitting signal. The present invention is used to form an on-channel repeating network in any transmission system including a digital television broadcasting system.

Abstract: Aspects of a method and system for bandwidth calibration for a phase locked loop are presented. Aspects of the method may include generating one or more carrier signals based on one or more corresponding calibration signals. A pre-distortion function may be computed based on the generated one or more carrier signals for the phase locked loop circuit. An output radio frequency (RF) synthesized signal generated by the phase locked loop circuit may be modified based on the computed pre-distortion function and a subsequent output RF synthesized signal generated based on the modified output RF synthesized signal.

Abstract: A system including a memory (storing a set of data records), a digital phase-locked loop (PLL) and digital circuitry. Each of the data records is allocated to one packet stream in a set of packet streams. The digital circuitry is configured to: invoke a read operation from the memory in response to a received stream indicator and received channel indicator corresponding to a current timestamp-bearing packet; generate an output timestamp for the current packet equal to an expected timestamp provided by the memory as part of the read operation; and generate error data based on argument data including a received input timestamp, a received slot delay value, a previous source frequency estimate and an expected timestamp provided as part of the read operation. The digital PLL is configured to compute an updated source frequency estimate based on information including the error data and the previous source frequency estimate.

Abstract: A phase tracking system includes a source of an input signal representing a received symbol. A phase rotator has a first input terminal which is responsive to the input signal, a second input terminal which is responsive to a phase correction signal, and an output terminal which produces a phase adjusted output signal. A decision element generates an ideal signal representing the received symbol in response to the phase adjusted output signal. A phase adjuster, which has full phase wrap-around capability, generates the phase correction signal in response to the phase difference between the phase adjusted output signal and the ideal signal.

Abstract: A testing circuit measures a center frequency of a clock signal outputted by a clock generator. The clock generator has a frequency modulator capable of (1) performing a frequency sampling accurately for the duration of modulation frequency and reducing the duration for frequency measurements, and (2) implementing proper testing of the down-spread controlling feature as one of the SSCG modulation functions by accurately determining the center frequency of the clock signal. The testing circuit measures a center frequency of a clock signal outputted by a clock generator by converting an analog modulation signal into a digital signal and outputting the digital signal, counting the period of the clock signal to obtain a count according to the digital signal outputted by the clock generator, and comparing the count with the predetermined specification values related to the center frequency of the clock signal to obtain and output a comparison result.

Abstract: A method of eliminating a runaway condition in a PLL includes the steps of: determining whether the PLL is locked to an input reference signal; when the PLL is not locked to the input reference signal, determining whether a frequency of an output signal generated by the PLL exceeds a prescribed maximum frequency; and when the frequency of the output signal generated by the PLL exceeds the prescribed maximum frequency, resetting the PLL to thereby eliminate the runaway condition.

Abstract: A quarter-rate phase detector can include: four latches controllable to latch, at different times according to quadrature clock signals, respectively, data received by the phase detector so as to form latched signals; an error circuit to combine corresponding ones of the latched signals, respectively, resulting in a plurality of intermediate signals; and a multiplexing unit to selectively output the intermediate signals as a phase error signal. A related method can have similar features.

Abstract: A phase locked loop (PLL) circuit provides ac devices, such as power inverters and power measurement devices, with a reliable means for synchronizing to ac electrical systems. In an exemplary embodiment, the PLL circuit is configured for operation with single-phase electrical systems and offers substantial noise immunity by basing its locking operations on measured fundamental components, i.e., measured x-y phasors, of the electrical system voltage. Further, with its phasor-based locking operations and with its timer/counter-based operation, the PLL circuit can be implemented partly or wholly in digital processing logic.

Abstract: A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.

Abstract: A self-tuning 3rd order type III phase-locked loop (PLL) is disclosed. In one aspect, the PLL provides frequency control that is implemented in three (3) parallel paths. The PLL provides frequency response tracking using a number of elements including a triple control voltage-controlled oscillator (VCO), a frequency-to-current (F2I) converter, and a switched capacitor loop filter. In addition to compensation for feedback ratio variation, near constant F2I gain over process variations and switched capacitor filters synchronized to a reference signal, near constant VCO gain over process variations allows the open loop frequency response to be tailored to track the reference signal. A high-speed locking technique is employed which significantly reduces acquisition time in low bandwidth cases. This PLL may be fabricated in a 0.18 ?m CMOS logic process.

Abstract: A frequency-to-current converter includes a digitally selectable capacitor, a sampling capacitor, an integrator circuit and an output transconductor. The sampling capacitor is operatively coupled via a first switch to the digitally selectable capacitor. The first switch is operated by a first clock pulse from a clock generator responsive to a reference clock. The integrator circuit has an output operatively coupled via a second switch to the sampling capacitor. The integrator circuit has an output operatively coupled to a control terminal of the transistor. The second switch is operated by a second, non-overlapping clock pulse from the clock generator. A current output by the frequency-to-current converter in response to the continuous question of first and second switches is linearly proportional to the frequency of the reference clock and the capacitance of the digitally selectable capacitor.

Abstract: A dual-use PLL frequency synthesizer for use in a transceiver is capable of operating as a local oscillation generator in a receiving mode and as a transmitter in a transmitting mode. The PLL frequency synthesizer includes a digital processor, a Digital-to-Analog Converter (DAC), a low pass filter and a phase locked loop. The digital processor generates a digital signal, in which the digital signal is a modulated digital signal in the transmitting mode, and the digital signal is a reference digital signal in the receiving mode. The DAC converts the digital signal to an analog signal, and the low pass filter filters the analog signal to produce a filtered analog signal. The phase locked loop up-converts the filtered analog signal to an RF signal. In the transmitting mode, the RF signal is a modulated RF signal, and in the receiving mode, the RF signal is a reference RF signal.

Abstract: A clock recovery circuit for digital data transmission includes a delay lock loop having a first loop which generates a phase difference signal which is indicative of a quantized phase difference between a data signal and a clock signal; and a second loop which generates a phase difference signal which is a smooth, continuous function of the phase difference between the data signal and the clock signal, such as a phase difference signal which is proportional to the phase difference. The delay lock loop may include two phase shifters in series, and one or both of these may include a phase interpolator.

Abstract: A loss of signal beat detector makes use of multiplication of a local clock signal and a recovered clock signal to obtain frequency deltas used to indicate loss signal. Through a hardware implementation, a high speed detection is offered, allowing changeover from the recovered clocking signal to the local clock signal when loss of signal is detected to prevent the transmission of a timing transient to downstream nodes.

Abstract: A phase comparator is used to test a device under test comprising an input/output (I/O) circuit by applying a signal to the device under test; extracting a phase signal from the phase comparator; and determining parametric information pertaining to the I/O circuit of the device under test from the phase signal.

Abstract: A method includes receiving a serial data signal including a preamble and an embedded clock signal having an embedded clock signal frequency, and processing the preamble using logic to determine the embedded clock signal frequency. An apparatus includes a counter unit, a state machine, and a logic unit. The counter unit includes a data port, a clock port and a plurality of counters. In operation, the data port receives a serial data signal and the clock port receives a clock signal having a clock signal frequency. The serial data signal includes a preamble and an embedded clock signal having an embedded clock signal frequency. The state machine identifies at least one of the plurality of counters to count between transitions in the preamble in response to the clock signal. The logic unit is coupled to the plurality of counters and determines the embedded clock signal frequency.

Abstract: A time information transmission-reception integrated circuit includes: a reception control circuit for detecting a signal obtained by receiving and amplifying an external radio wave, and generating a clock data signal, based on a carrier signal the phase of which is synchronized with the signal; and a transmission control circuit for generating an amplitude modulation signal obtained by modulating the amplitude of the carrier signal by the transmission time code, by a modulator, and transmitting a relaying radio wave from an antenna, the phase of the relaying radio wave synchronized with the phase of the external radio wave, by correcting the phase shift of the amplitude modulation signal by a phase shifter. Thereby, the phase shift between the external radio wave and the relaying radio wave is cancelled.

Abstract: A clock adjustment apparatus delays a clock signal and adjusts a phase of the signal, thereby increasing or decreasing a delay amount of the clock signal in accordance with a phase relation between a data signal and an adjusted clock signal. The adjusted clock signal is used for receiving the data signal.

Abstract: A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration phase locked loop synthesizer device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path.

Abstract: Jitter is measured by receiving a first reference signal at a first phase-locked loop (PLL) circuit and generating at an output of the first phase-locked loop circuit an output signal based at least in part on the first reference signal, the output signal including a jitter component to be measured. A signal corresponding to the output signal and a signal corresponding to the first reference signal are compared in a phase detector of a second phase-locked loop circuit. A value corresponding to an output of the comparison is stored that includes information indicative of the measured jitter component.

Abstract: Noise detection is performed by using the output of the phase comparator that the PLL comprises. The phase comparator outputs a signal that is based on the phase difference between the output of the voltage controlled oscillator and the reference signal. The phase difference reflects the effect of noise on the PLL and, in addition to the characteristics of the noise itself, such as the wave height value of the noise and the frequency component thereof, reflects the tolerance of the PLL to noise, whereby the level of risk that the system can actually be caused to malfunction can be judged.

Abstract: Systems and methods are provided for reducing pathological conditions in a serial video interface. A sequence of parallel data words that are to be transformed by a data-scrambling algorithm comprise an input signal. The bit order of one or more of the words in the sequence of parallel data words is reversed and the sequence of parallel data words, now including one or more bit-reversed words, is transmitted. The signal resulting from application of a data-scrambling algorithm to the sequence of parallel data words, including one or more bit-reversed words, has a reduced likelihood of including a pathological condition.

Abstract: Circuits, architectures, systems and methods for facilitating data communications and/or reducing latency in data communications. The architecture includes a clock recovery loop receiving data from a host device and providing a recovered clock signal, a filter circuit receiving recovered clock signal information and providing a control signal that adjusts the transmitter clock in response to recovered clock signal information and the two clock signals, and a transmitter receiving the control signal and transmitting data to a destination device in accordance with the transmitter clock. The circuitry generally includes a clock alignment block receiving first and second periodic signals and providing a control signal in response thereto, a filter for first periodic signal information, and a logic circuit configured to combine the control signal and the filtered information, thereby providing an adjustment signal for the second periodic signal.

Abstract: An apparatus of phase-frequency detector for adjusting wobble clock signal and wobble signal in the same phase, comprising: a first logic gate, receiving a first protection signal and a second protection signal and outputting a third protection signal according to a logic operation; a first flip-flop, coupled to the first logic gate, outputting the third protection signal as a first output signal when the wobble clock trigger; a second flip-flop, coupled to the first logic gate, outputting the third protection signal as a second output signal when the wobble signal trigger; a second logic gate, coupled to the first and the second flip-flop, outputting a fourth protection signal according to a logic operation; a third logic gate, coupled to the second logic gate, receiving the third and the fourth protection signal, and outputting a fifth protection signal according to a logic operation; and a control signal generator, receiving the wobble clock, the input signal, and the fifth protection signal and determinin

Abstract: A signal generating apparatus for generating a synthesized signal according to an input signal is provided. The signal generating apparatus includes a phase-locked loop device and a control unit. The phase-locked loop device has a phase/frequency detector for generating a detected signal according to a reference oscillating signal and a feedback signal, a control signal generator for generating a control signal according to the detected signal, a voltage controlled oscillator for generating the synthesized signal according to the control signal, and a divider for dividing the synthesized signal according to a dividing factor to generate the feedback signal. The control unit is for controlling the control signal generator to adjust the control signal in a calibration mode to thereby adjust a frequency of the synthesized signal. The phase/frequency detector does not output the detected signal to the control signal generator in the calibration mode.

Abstract: Systems and methods for aligning the phase of a PLL with an incoming data signal. In one embodiment, when a data signal is received in a PLL, a phase perturbation signal is generated and injected into the PLL. The PLL then performs a phase alignment procedure to lock on to the received data signal. The phase perturbation signal is a damped sinusoidal oscillation that is injected into the PLL when each of a plurality of data packets is received. The perturbation signal has an amplitude sufficient to bump the PLL out of a quasi-stable state around 180 degrees out of phase with the incoming data signal, but is damped to less than a degree of phase shift within 30 ns of being injected.

Abstract: A method and system provide a stable reference clock for use in a communication system. A phase-locked loop (PLL) receives an input clock signal with potentially unacceptable levels of jitter and wander. The PLL provides a synchronized output clock with significantly reduced jitter and wander. The PLL nominally uses a digital-to-analog converter (DAC) to control a voltage-controlled oscillator (VCO). Applying a loop filter function to the phase difference between the input clock and the output clock generates control values for the DAC. Loop filter adaptation is based on control value averages, which enhances stability and frequency locking performance. Frequency lock detection is based on the consistency of the DAC control values, rather than on a predetermined target value, making the PLL a self-calibrating system. The long-term average of the control value in the locked state may be stored for later use as an initial DAC setting.

Abstract: There is provided a flexible transmission device capable of automatically setting an optimal point for a signal decision making with high accuracy, so that highly reliable high-quality signal regeneration control is achieved. A clock timing extraction circuit dynamically sets a frequency-dividing ratio based on the transmission rate of an input signal to perform a phase synchronization control so that there is a fixed phase difference between the input signal and an oscillation output, whereby clock timing based on the transmission rate can be extracted. A regeneration control circuit sequentially sweeps a voltage threshold level and the phase of the extracted cock with respect to the input signal and determines whether the levels of adjacent monitor points match, whereby a decision point within the valid zone of the eye pattern can be automatically measured and used as the optimal point for regeneration control.

Abstract: The present invention relates to a dynamically adjusted phase-locked loop (PLL). The level of capacitance of the loop filter and the level of current of the charge pump of the phase-locked loop are adjusted in accordance with an analogue method.

Abstract: A phase locked loop (PLL) circuit (1) comprising a loop input (11); a phase detector section (2) for detecting a phase difference between an input signal and a reference signal. The phase detector section (2) has a detector input connected to the loop input, a reference input and a detector output for outputting a signal related to the phase difference. A controlled oscillator (4) is connected with an input to the detector output and an oscillator output is connected to a loop output (12). The PLL has a feedback circuit which connects the oscillator output to the reference input, wherein the feedback circuit includes a device (7;71-74) having a transfer function with at least one zero.

Abstract: A phase-locked-loop device includes a clock generator for generating a reference clock based on a binarized playback signal and a frequency of run-length data and for generating N-phase clocks using the reference clock, a pulse-length measuring device for measuring a pulse length of the binarized playback signal using the N-phase clocks to output pulse-length data, and a run-length-data extracting device for counting the pulse-length data based on a virtual channel clock to extract run-length data. Pulse-length data is generated using the N-phase clocks (e.g., 16-phase clocks). The pulse-length data is counted based on the virtual channel clock to extract run-length data. Thus, it is not needed to generate a high-frequency clock, and the operating frequency is maintained sufficiently low.

Abstract: A device configured to recover and repeat source synchronous data. The device is configured to receive source synchronous data via a first interface and recover the received data utilizing a first clock signal which is generated to be approximately ninety degrees out of phase with the received clock signal. A second clock signal is generated to be in phase with the received source synchronous clock signal. The second clock signal is the utilized to select a newly generated clock signal and latched data for transmission in a source synchronous manner. The device is further configured to shift the phase of the generated first clock signal to be approximately ninety degrees out of phase with the received data signal.

Abstract: In a frequency modulator, a VCO oscillates at a frequency according to a voltage applied to an input terminal. A divider divides an output signal of the VCO. A phase comparator compares the output of the divider with a reference clock signal and outputs a voltage corresponding to a phase difference. A loop filter is provided on a path leading from an output terminal of the phase comparator to the input terminal of the VCO, and the loop filter removes a high-frequency component of an output voltage of the phase comparator. A terminal for inputting a modulation signal is provided in the loop filter, separately from a terminal connected with the path leading from the output terminal of the phase comparator to the input terminal of the VCO.

Abstract: A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.

Abstract: An apparatus eliminates a differential phase shift, ??(f), between a double sideband suppressed carrier modulated angular rate information signal and its sinusoidal demodulation reference signal in a gyroscope angular rate sensing circuit including a signal reference source. The apparatus includes a demodulator, a phase shifter in a demodulation reference signal path, the demodulation reference signal path being between the signal reference source and the demodulator. The phase shifter is configured to adjust a phase of the sinusoidal demodulation reference signal. A phase locked loop (PLL) includes a phase detector, a servo equalizer, and a dual-frequency, numerically controlled oscillator. The PLL is configured to provide a demodulation signal based on the phase shifted demodulation reference signal, and a phase shift command source is configured to provide an input to the phase shifter to command an appropriate phase adjustment.

Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Abstract: A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM.

Abstract: A terminal includes at least one wireless communication application module (1) and a plurality of further application modules (4, 5, 6, 8). Multiple radio frequency clock signals are generated for the different modules having respective clock frequency characteristics and including at least first and second clock frequencies that are not integral multiples nor sub-multiples of each other nor of a third frequency. The clock generation comprises reference frequency means (14), fractional-N phase-locked loop frequency synthesizer means (15) responsive to the reference frequency means, and different automatic frequency control means for adjusting clock frequencies relative to received signals. The reference frequency means (14) is arranged to supply a common reference frequency signal to a plurality of the fractional-N phase-locked loop frequency synthesizer means (17, 18, 19, 25, 26, 41,42) that supply the first and second clock frequencies respectively for the application modules.

Abstract: An apparatus and corresponding method for preventing data loss in network devices is disclosed. The present invention monitors an incoming data stream to a network device, or devices, and in the event that an error condition is detected, predetermined error data is inserted into the data stream, wherein the predetermined error data is provided at the same data rate as the recovered data rate internal to the network device. Thus, the network device will not have to adjust to a different data rate and potentially lose data during the adjustment period.

Abstract: A method and apparatus for accurately estimating the carrier frequency offset and the carrier phase offset of a digitally modulated signal using a signal processing algorithm to initialize the state variables of a Phase-Locked Loop (PLL) is disclosed. A sequence of phase values is estimated from a received sequence of symbols and the angular effect due to the modulation format is removed from the sequence of phase values. A curve-fit algorithm based in one embodiment on the RLS algorithm is then applied to a sequence of unwrapped phase values to estimate the carrier frequency offset and the carrier phase offset.

Abstract: There is provided a PLO device which performs high-accuracy, high-quality clock recovery. A shifted data generation part generates shifted data, and a first phase comparison part outputs first difference data. A first filter removes an alternating-current component from the first difference data and outputs a first detection voltage. A delay part delays input data for a time corresponding to half of one time slot with the use of an analog delay element and outputs delayed data. A second phase comparison part compares the phases of the input data and delayed data with each other and outputs second difference data. A second filter removes an alternating-current component from the second difference data and outputs a second detection voltage. An arithmetic section divides the first detection voltage by the second detection voltage to obtain a control voltage. A clock oscillation section outputs recovered clock based on the control voltage.