Abstract: A method and apparatus for frame synchronization in a display circuit is achieved by first measuring a difference between a first frame period and a second frame period. When the difference exceeds a threshold, the first frame period is adjusted by replacing the clock corresponding to the first frame period with one of a slow frame rate and a fast frame rate. The slow and fast frame rates closely approximate an ideal frame rate that would synchronize the two frame periods. By switching between the slow and fast frame rates, the average frame rate approaches the ideal frame rate over time, and the two frame periods are effectively synchronized.

Abstract: A phase error measurement circuit for measuring phase error between two clocks on an integrated circuit is provided. The measurement circuit includes first and second clock signal inputs, a phase lead detector, a phase lag detector and a phase error measurement output. The phase lead detector includes a phase lead latch having a data input, which is coupled to the first clock signal input, a latch control input, which is coupled to the second clock signal input and a data output. The phase lag detector includes a phase lag latch having a data input, which is coupled to the second clock signal input, a latch control input, which is coupled to the first clock signal input and a data output. The phase error measurement output is formed by the data outputs of the phase lead latch and the phase lag latch.

Abstract: A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

Abstract: A transceiver for implementing an adaptive vector modulation method is disclosed. In response to a binary stream assembled into groups of bits forming symbol indices, a transmitter of the transceiver generates one or more complex values symbols that are normalized over channel coefficients associated with one or more propagation channels between one or more transmitter antennas and one or more receiver antennas. The transmitter controls a transmission of the complex values symbol(s) from the transmitter antenna(s) to a selected receiver antenna. The selection of the receiver antenna is based upon a metric proportional to the average injection power or a vector norm corresponding to each receiver antenna of the receiver antenna(s).

Abstract: Repetitive sampling of a data signal is performed. A clock reference is generated. The clock reference has a known period relationship with the data signal. The clock reference and the data signal are simultaneously sampled. The sampled information from the clock reference is used to determine in what phase of the clock reference sampled values of the data signal occur.

Abstract: Systems and methods are described for carrier-frequency synchronization for improved AM and TV broadcast reception. A method includes synchronizing a carrier frequency of a broadcast signal with a remote reference frequency. An apparatus includes a reference signal receiver; a phase comparator coupled to the reference signal receiver; a voltage controlled oscillator coupled to the phase comparator; and a radio frequency output coupled to the voltage controlled oscillator.

Abstract: A method of simple network synchronization in a bus extension system with expanded capabilities wherein a plurality of independently-operable multimedia multiplexing devices are connected to the same network in parallel. The method of network synchronization for multiplexing devices connected by parallel through an extension bus is provided wherein one of two or more multiplexing devices is used as a clock master and other remaining multiplexing devices as slave devices and wherein the multiplexing device acting as the clock master is operated in synchronization with a clock received from a network while the multiplexing devices acting as the slave devices receive a clock from a clock transmission line of the extension bus which is outputted after the clock master has established synchronization with the network clock and regenerate a clock leading the received clock in phase.

Abstract: A single chip RF communication system and method is provided including a transmitter and a receiver. The RF communication system in accordance with the present invention includes an antenna for receiving transmitting RF signals, a PLL for generating multi-phase clock signals having a frequency different from a carrier frequency in response to the multi-phase clock signals and a reference signal having the carrier frequency, a demodulation-mixing unit for mixing the received RF signals with the multi-phase clock signals having the frequency different from the carrier frequency to output the RF signals having a frequency reduced by the carrier frequency and an A/D converting unit for converting the RF signals from the mixing unit into digital signals.

Abstract: The frequency divider output a2 is provided to the D input of a first D flip-flop and an input clock a1 to a first frequency divider is inversed by an inverter and is then provided to the C input of the first D flip-flop. The first frequency divider output b2 is provided to the D input of a second D flip-flop, and an input clock b1 to a second frequency divider is inversed by another inverter and then sent to the input C of the second D flip-flop. The Q output of the first D flip-flop and the Q output of the second D flip-flop are sent to a phase comparator as the output signal a3 and the output signal b3, respectively. In this way, the frequency divider outputs a2 and b2 are taken into the first and second D flip-flops at a point half behind the input clocks a1 and b2 and are provided to the phase comparator as the output signals a3 and b3.

Abstract: A frequency synthesizer circuit comprises a controller, a synthesizer and a voltage controlled oscillator are used to generate an oscillating signal in response to external commands. The synthesizer provides a lock detect signal to the controller when the synthesizer detects that the oscillating signal has reached a desired frequency following application of a load signal. A first timer, a second timer, and a counter are adapted to receive the load signal and the lock detect signal. The first timer provides a first measurement corresponding to an amount of time between the load signal and a first receipt of the lock detect signal. The second timer provides a second measurement corresponding to an amount of time between the load signal and a final receipt of the lock detect signal. The counter provides a count value corresponding to a total number of times that the lock detect signal is received inclusive of the first receipt and the final receipt of the lock detect signal.

Abstract: A burst-mode digital receiver which minimizes any reduction in the minimum input level as compared with a continuous-signal digital receiver includes a unipolar code-to-bipolar code converter for converging unipolar code pulses of an inputted burst signal into bipolar code pulses, an identifying circuit for identifying logic levels of "1" and "0" with an identifying level at a center of a pulse duration of bipolar code pulses outputted from the unipolar code-to-bipolar code converter, and a burst on/off detecting circuit for continuously outputting a signal until the inputted burst signal is finished when a pulse amplitude of the inputted burst signal exceeds a constant value. The burst-mode digital receiver produces an output signal when an AND gate connected to the output terminal of the identifying circuit is turned on at the time the output signal from the burst on/off detecting circuit is turned on.

Abstract: A digital PLL apparatus includes a synchronization integrating circuit, an angle calculating circuit, and a digital PLL circuit. The synchronization integrating circuit determines a symbol timing by obtaining the maximum amplitude point of a correlation level during reception of a preamble. The angle calculating circuit outputs a phase .theta.c by performing an angle calculation every symbol timing determined by the synchronization integrating circuit. The digital PLL circuit receives the phase .theta.c from the angle calculating circuit and operates a phase locked loop, thereby obtaining an output phase.

Abstract: On converting an input data signal having a first transmission rate into an output data signal having a second transmission rate different from the first transmission rate, the input data signal is memorized as a memorized input data signal a first memory. A read clock generating circuit generates a read clock signal to read the memorized input data signal as a read data signal out of the first memory. A read control circuit controls the read clock generating circuit to stop generation of the read clock signal in order to make the read data signal have an overhead bit slot at a predetermined period. A rate control circuit produces a rate control signal having a predetermined pattern and an inhibit signal in accordance with the rate control signal. The read clock generating circuit stops generation of the read clock signal in response to the inhibit signal. A multiplexing circuit multiplexes an information signal to the read data signal on the basis of the rate control signal to produce the output data signal.

Abstract: A circuit arrangement for generating the clock signal of a predetermined frequency f(UART) for a smart card interface, the interface being used for transferring data from a smart card to a device e.g. a mobile telephone at a predetermined data rate f(D). Using a phase-locked loop (PLL) and a number of programmable counters (N1-N4), the output of the circuit i.e. the smart card interface clock signal can have a frequency f(UART) which is a multiple of the data rate. In particular, the counters (N1-N4) and phase-locked loop (PLL) can be chosen so that f(UART) is sixteen times f(D) which allows a Universal Asynchronous Receiver Transmitter circuit to be used in the interface.

Abstract: In a bit clock generation circuitry, a T/2 pulse generator includes a monostable multivibrator triggered by an edge of an input PCM data signal and controlled by a time constant adjusting signal so as to generate a pulse signal having its pulse width adjusted in accordance with the time constant adjusting signal. In response to a pulse signal generated by the monostable multivibrator, a D-type flipflop latches the input PCM data signal for generating a delayed data signal delayed from the input PCM data signal by T/2. An exclusive-OR means receives the input PCM data signal and the delayed data signal for generating a T/2 pulse signal.