Abstract: Various aspects of the present disclosure provide for methods, apparatus, and computer software for multiple access to a channel carrying a common uplink burst transmitted by users that utilize two different modes. Specifically, a coupled mode provides for range extension for users at a cell edge, while a decoupled mode provides for user data transmissions within the common uplink burst. Multiple access between these different modes may be provided in a non-orthogonal scheme by moderating the amount of interference between the respective modes. Further, multiple access between these different modes may be provided in an orthogonal scheme by utilizing interleaved frequency division multiple access (IFDMA).

Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.

Abstract: A signal processing device including a first signal processing chain having a first output signal; a second signal processing chain comprising a second output signal with a higher accuracy than the first output signal; a controller configured to switch, based on a desired accuracy, whether to switch between the first and second signal processing chains as a path for an original input signal; and a modifier configured to modify the original input signal, the first output signal, or the second output signal to generate a modified input, a modified first output, or a modified second output signal when the controller switches between the first and second signal processing chains.

Abstract: Provided are a method and an apparatus for canceling interference, to resolve a problem that performance of interference cancellation is poor because accuracy of equalizer coefficients obtained by a CMTS through calculation is not sufficiently high. A specific solution is as follows: (101) A CMTS calculates L equalizer coefficients of an L-tap filter according to a preamble sequence by using an adaptive algorithm, and performs adaptive equalization on a received signal by using the L equalizer coefficients, where L is a positive integer greater than 24; and (102) the CMTS selects K equalizer coefficients from the L equalizer coefficients, and sends a ranging response message carrying the K equalizer coefficients to a cable modem CM, so that the CM performs pre-equalization on a to-be-sent signal according to the received K equalizer coefficients, where K is a positive integer less than or equal to L.

Abstract: A processor extracts a reference signal of a scanner included in an adaptive optics SLO apparatus output while the scanner performs reciprocating scanning once on a region of an eye, generates sampling data strings of reciprocating scanning based on an electric signal obtained by a photoelectric conversion unit included in the adaptive optics SLO apparatus using the reference signal as a sampling reference position, and compares, among the sampling data strings of the reciprocating scanning, a sampling data string of forward scanning with a sampling data string of backward scanning so as to evaluate the correlation between the sampling data strings, and compensates a sampling reference position based on a result of the evaluation. An image construction unit assembles image data to construct an image of the region of the eye based on the sampling data strings of the reciprocating scanning in accordance with the compensated sampling reference position.

Abstract: Disclosed is a reception apparatus that has solved a problem that fluctuations cannot be followed immediately after a commencement of turbo equalization in a high-speed fading environment. A reception apparatus includes a soft interference canceller, an MMSE equalizer, a likelihood calculator, a de-interleaver, an SISO decoder, an information bit hard decision unit, a subtracter, an interleaver, a soft estimation value calculator, a zero storage unit, a known signal memory unit, a transmission path estimator, and a plurality of switches. At the time of equalization, the transmission path estimator uses, as a reference signal, a known signal stored in the known signal memory unit or an output of the MMSE equalizer. Meanwhile, at the time of a first equalization, the soft interference canceller is given a ‘0’ value from the zero storage unit as a reference signal.

Abstract: Techniques for reducing the complexity and power requirements of precompensation units, as well as equalizers, devices, and systems employing such techniques. In an illustrative method for providing high speed equalization, the method comprises: obtaining a channel response that presents trailing intersymbol interference in a signal having a sequence of symbols from a symbol set; determining a distribution of threshold values for a precompensation unit corresponding to said channel response with said symbol set; deriving a reduced set of threshold values from said distribution; and implementing a decision feedback equalizer with a reduced-complexity precompensation unit employing the reduced set of threshold values.

Abstract: An apparatus for processing data includes a decision feedback equalizer configured to sample an analog signal to yield digital data and a DC offset adaptation circuit. The decision feedback equalizer is configured to sample the equalized signal using at least one data latch at a first data latch threshold value and at a second data latch threshold value. The DC off set adaptation circuit is configured to calculate a DC off set in the analog signal based on the first data latch threshold value and on the second data latch threshold value.

Abstract: The present disclosure provides adaptive cascaded equalization circuits for frequency spectrum compensation. The cascaded equalization are formed in circuit configurations to achieve configurable roll-up frequency responses to compensate for the loss of signal channels in the wire-line or optical communications, particularly but not exclusively, for the loss of signal trace in the wire-line communications, and photodetectors used in the optical communications. These cascaded equalization circuits include two or more stages of equalizers. The peaking frequencies of each stage are set to be different from each other, so that the overall frequency response characteristic has a unique frequency response with a roll-up slope. The equalization function is automatically tuned by an adaptive feedback control loop.

Abstract: The subject matter described herein relates to methods, systems, and computer readable media for adaptive calibration of test systems to interconnects. In some examples, a control circuit performs a method for adaptive calibration including determining, for each configurable calibration parameter of a number of configurable calibration parameters for a receiver for processing a received signal from an interconnect coupled to the receiver, a range of valid values for the configurable calibration parameter. The method further includes for each configurable calibration parameter: sweeping the configurable calibration parameter across a subset of values from the range of valid values for the configurable calibration parameter; and testing the received signal from the interconnect for each value in the subset of values and storing a result of the testing for the value. The method further includes determining a set of calibrated values for the configurable calibration parameters based on the results of the testing.

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

Abstract: The present disclosure provides a method implemented in a wireless communication device for estimating a frequency offset between a carrier frequency of a received signal and a frequency of a local oscillator as well as the wireless communication device. The method comprises determining a plurality of phase change candidates for a phase change between a data symbol and a first reference symbol in the signal. The method further comprises generating a collection of constellation symbols from the data symbol and rotating the collection of constellation symbols by the plurality of phase change candidates. Then, one of the phase change candidates corresponding to one of the rotated collections of constellation symbols is selected in such a manner that said one of the rotated collections of constellation symbols matches a set of constellation points best. Next, the frequency offset is determined based on the selected phase change candidate.

Abstract: A method for estimating cable length in an Ethernet system and a receiver thereof are applicable to an Ethernet system. The method for estimating cable length includes obtaining a channel tap from channel information of a feedback equalizer in the Ethernet system and estimating a cable length according to the channel tap, a first coefficient and a constant.

Abstract: A method for estimating performance of a serial communication channel using processing circuits. The channel is configured to transmit a binary input stream from a transmitting end to an output stream at a receiving end. The method includes modeling by the processing circuits the channel at the receiving end as a first finite impulse response (FIR) system. The modeling includes estimating a cursor pulse response of the first FIR system by analyzing the output stream received at the receiving end, and estimating one or more pre-cursor or post-cursor pulse responses of the first FIR system from the received output stream using the estimated cursor pulse response. The method further includes determining by the processing circuits a performance metric by using the estimated one or more pre-cursor or post-cursor pulse responses.

Abstract: Embodiments of the present invention may provide the capability for reducing power consumption in a speculative decision feedback equalizer by powering up the speculative path that is going to take the next decision based on the previous decision, and holding other paths in a reset low-power condition. For example, a Speculative Decision Feedback Equalizer may comprise a plurality of speculative paths, circuitry to provide power to a speculative path that will take the next decision based on the current decision, and circuitry to keep at least one other speculative path in a reset state with low or reduced power consumption.

Abstract: A wideband RF tuner with blocker signal detector for detection of blocking signals and for fast recovery from noise limited region.

Abstract: This document describes techniques for performing non-coherent demodulation of a differentially modulated signal in a drift robust manner. A differentially modulated signal, including a plurality of symbols, may be received. Non-coherent domodulation of the differentially modulated signal may be performed. The non-coherent demodulation may include performing noise prediction using a high-pass filtered estimated error signal associated with the differentially modulated signal. In some embodiments, frequency offset estimation to reduce frequency offset of the differentially modulated signal may also be performed as part of the non-coherent demodulation.

Abstract: Apparatus and method for digital signal constellation transformation are provided herein. In certain configurations, an integrated circuit includes an analog front-end that converts an analog signal vector representing an optical signal into a digital signal vector, and a digital signal processing circuit that processes the digital signal vector to recover data from the optical signal. The digital signal processing circuit generates signal data representing a signal constellation of the digital signal vector. The digital signal processing circuit includes an adaptive gain equalizer that compensates the signal data for distortion of the signal constellation arising from biasing errors of optical modulators used to transmit the optical signal.

Abstract: A decision feedback equalizer of an electric signal transmission apparatus has an average peak value determiner that receives an output of an adder and a threshold value set by a program. An average peak value of the output of the adder), compares a magnitude relation of the detected average peak value and the threshold value, increases the reference value of the output of a reference value generation circuit from an initial value set by the program and causes resolutions of DACs to become coarse from the initial value, when the average peak value is larger than the threshold value, and decreases the reference value of the output of the reference value generation circuit from the initial value set by the program and causes the resolutions of the DACs to become fine from the initial value, when the average peak value is smaller than the threshold value.

Abstract: An equalizing apparatus includes a feedforward filter, a soft slicer and a feedback filter. The feedforward filter processes an input signal. The soft slicer performs a soft decision according to an input signal of the feedforward filter and a feedback signal of the feedback filter to generate a decision result signal. The feedback filter generates the feedback signal according to the decision result signal.

Abstract: An electronic device for a wireless communication system is described. The electronic device comprises: a receiver configured to receive a modulated signal on a communication channel; and a processor, coupled to the receiver and configured to: process the received modulated signal; identify a communication channel characteristic based on the processed received modulated signal; select an equalizer having a first set of equalization coefficients based on the identified communication channel characteristic, wherein the first set of equalization coefficients is selected from a plurality of equalization coefficients, each of the plurality of equalization coefficients being associated with different communication channel characteristics; equalize the processed received modulated signal on the communication channel using the selected equalizer; and detect the equalized received modulated signal.

Abstract: The embodiments are directed to methods and systems for sending and receiving signals between one or more peripheral devices connected to a dongle system and an operating system. The methods and systems can detect when a dongle system has been connected to a mobile computing device. The methods and systems can receive an input to use the dongle system with a local operating system or a remote operating system. The methods and systems can also establish a communication channel between the local operating system and the remote operating system, and exchange signals between the dongle system and the remote operating system using one or more virtual filters.

Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Abstract: The present invention is directed to communication systems. More specifically, embodiments of the present invention provide a technique and system thereof for performing eye modulation. Eye modulation is performed at the transmission side of a PAM communication system to compensate for distortion and non-linearity and generate an output waveform. Spacing among eye levels is adjusted by performing symmetric modulation using ? parameter and asymmetric modulation using ? parameter. A correction module measures the output waveform and sends feedback signals to a control module to adjust the ? parameter and the ? parameter. There are other embodiments as well.

Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Abstract: This disclosure relates to baseline restoration methods and apparatuses and medical detecting equipment thereof. The baseline restoration method comprises: determining whether there is a high-amplitude baseline in an input signal by previous k output signals (Y1, . . . , Yk) of a filter, where k is a natural number and k?1; setting the previous m output signals (Y1, . . . , Ym) of the filter as Y? when there is a high-amplitude baseline in the input signal, where Y? is a desired output signal of the filter; and using a current input signal X0, the previous n input signals (X1, . . . , Xn), and the previous m output signals (Y1, . . . , Ym) of said filter to obtain a current output signal Y0 of said filter.

Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Abstract: For analog-to-digital converters (ADCs) which utilize a feedback digital-to-analog converter (DAC) for conversion, the final analog output can be affected or distorted by errors of the feedback DAC. A digital measurement technique can be implemented to determine switching mismatch error for the feedback DAC in a continuous-time delta-sigma modulator (CTDSM) or in a continuous-time pipeline modulator. The methodology forces each DAC unit elements (UEs) to switch a certain amount times and then use the modulator itself to measure the errors caused by those switching activities respectively. The obtained errors can be stored in a look-up table and fully corrected in digital domain or analog domain.

Abstract: A method of receiving data including receiving, on one or more carrier waveforms, signals representing a plurality of data elements of an original data frame wherein each of the data elements are represented by cyclically time shifted and cyclically frequency shifted versions of a known set of waveforms. The method further includes generating, based upon the signals, a received data frame and generating an equalized data frame by performing an equalization operation using elements of the received data frame, the equalization operation correcting for distortion introduced into the signals during propagation of the carrier waveforms through a channel.

Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Abstract: Digital receiver systems and clock recovery techniques for use in digital receiver systems are provided to implement asynchronous baud-rate clock recovery systems for high data rate serial receivers multilevel line modulation. A two-stage postcursor ISI equalization system is provided to efficiently emulate a 4-level DFE (decision feedback equalization) system, for example, while converting a 4-level equalized signal to s 2-level equalized signal. For example, a two stage postcursor ISI equalization system includes a DFE stage which operates on a most significant component of a given 4-level data symbol, followed by a DFFE (decision-feedforward equalizer) stage which operates on a least significant component of the given 4-level data symbol. In parallel with the DFFE stage, an estimate of the least significant component is subtracted from the equalized 4-level data symbol to convert the 4-level data symbol to a 2-level symbol.

Abstract: Circuits, devices, methods for decision feedback equalization are described. A decision feedback circuit can include a plurality of decision feedback equalizer (DFE) branches, each DFE branch including: a pre-computation stage for generating a set of tap-adjusted inputs, each tap-adjusted input corresponding to a possible value of a previous output for the same DFE branch; and a decision feedback stage including a multiplexer circuit for selecting at least one output from the set of tap-adjusted inputs based on tap-adjusted inputs from other DFE branches. For at least a first DFE branch of the plurality of DFE branches, at least one selection line for the multiplexer circuit in the decision feedback stage of at least the first DFE branch of the plurality of DFE branches is an intermediate value from a multiplexer circuit for a second DFE branch of the plurality of DFE branches.

Abstract: Systems and methods related to improved coherent demodulation and, in particular, improved channel equalization that accounts for variation in an effective channel estimation error with transmitted symbols are disclosed. In one embodiment, a wireless node includes a receiver front-end, a channel estimator, and an equalizer. The receiver front-end is adapted to output samples of a received signal. The channel estimator is adapted to estimate a channel between a transmitter of the received signal and the wireless node based on the samples of the received signal. The equalizer is adapted to process the samples of the received signal according to a modified equalization scheme that compensates for variation in an effective channel estimation error with transmitted symbols to thereby provide corresponding bit or symbol decisions. In this manner, channel equalization is improved, particularly for a wireless system that utilizes a modulation scheme with varying amplitude.

Abstract: Described is an apparatus which comprises a decision feedback equalizer (DFE) having a first DFE tap path and non-first DFE tap paths, wherein the DFE includes a variable delay circuit in a signal path of the non-first DFE tap paths. In some embodiment, an apparatus is provided which comprises: a summer; a slicer to receive input from the summer; a first feedback loop to cancel a first post-cursor, the first feedback loop forming a loop by coupling the slicer to the summer; and a second feedback loop to cancel a second post-cursor, the second feedback loop forming a loop by coupling an input of the first feedback loop to the summer, wherein the second feedback loop having a programmable delay at its input.

Abstract: Described is an apparatus which comprises: samplers operable to perform linear equalization training and to perform function of an un-rolled decision feedback equalizer (DFE); and logic to select output of offset samplers, from among the samplers, when two adjacent bits of an input signal are the same. Described is an equalization scheme which comprises a linear equalizer (LE) operable to match a first post-cursor residual ISI tap to a first pre-cursor residual ISI tap for a non-lone bit transition of the input signal.

Abstract: A system includes a decision feedback equalizer (DFE). The DFE includes a first summing node, a first synchronization latch, a second synchronization latch, a first feedback latch, and a first feedback shift register. The first summing node is coupled to a data input of the DFE. The first synchronization latch receives data from the first summing node. The second synchronization latch and the first feedback latch receive data from the first synchronization latch. The first feedback shift register is coupled to an output of the second synchronization latch or the first feedback latch. The first feedback shift register includes sequentially coupled shift latches. A first of the shift latches data received from the second synchronization latch or the first feedback latch and provides data to the first summing node. First alternate ones of the shift latches are configured to provide feedback data to the first summing node.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well.

Abstract: A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to communicate a first set of data to the link partner component. The first component may comprise at least one receiver to receive a first set of equalization data. The first component may further comprise coefficient storage coupled to the receiver to store the equalization data. In addition, coefficient logic coupled to the coefficient storage to generate a first set of coefficients based on the first set of equalization data. The first component is to send the first set of coefficients to the link partner component.

Abstract: A WAP including: an MU grouping module; a constrained station identifier: a precode matrix calculator and compressor, and a spatial mapper. The MU grouping module selects a downlink MU group of stations and a number of downlink streams. The constrained station identifier identifies any of the stations in the MU group that are constrained stations and a limit on the number of training streams supported for the most constrained station. The precode matrix calculator calculates a precode matrix “Q” for spatially separating the aggregate number of MU-MIMO downlink streams. The precode matrix compressor responds to the identification of any constrained stations in the MU group, by compressing the precede matrix Q into a compressed precode matrix “C(Q)”. The spatial mapper spatially maps a training portion of each packet with a selected one of C(Q) and Q as a precode matrix; based on whether or not a constrained station is identified within the MU group.

Abstract: A demodulator apparatus includes a memory and a processor coupled to the memory. The processor executes a process including: applying lattice reduction to a channel response matrix; applying linear detection to a reception signal in lattice-reduced basis using a lattice-reduced channel response matrix; calculating an expectation of a symbol in the lattice-reduced basis; inversely transforming the expectation of the symbol from the lattice-reduced basis into an original basis; and calculating soft-decision data by performing interference cancellation method in inversely transformed expectation of the symbol in the original basis.

Abstract: A decision-feedback equalizer for use in a receiving unit for receiving an incoming data stream and for providing a stream of bit data outputs, including at least one decision-feedback equalizer block comprising a plurality of speculation units. Each speculation unit includes a dynamic preamplifier for asynchronously amplifying a voltage difference depending on an input voltage of the incoming data stream and a given threshold voltage; and an arrangement for selectively generating a transconductor current which depends on the amplified voltage difference. Also included is one dynamic regenerator for associating an output data bit to the selectively generated transconductor current.

Abstract: Disclosed are a communication apparatus and a communication method capable of improving transmitting/receiving frequency efficiency of a satellite signal per bandwidth or spectral efficiency (S.E) per bandwidth by removing and improving a distortion or inter-symbol interference for applying a minimum-mean square error (MMSE) equalizer required to detect a frame synchronization and a modulation code rate in a satellite service for satellite broadcasting or communication under the variable coding and modulation (VCM) or adaptive coding and modulation (ACM) environment.

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources.

Abstract: A method of coding/decoding of a digital audio signal comprising a succession of consecutive blocks of data, on the basis of a predictive filter. A modified predictive filter is used for the coding of at least one current block, the modified filter being constructed by the combination of: a rear filter calculated for a past block, preceding the current block, and enrichment parameters for the rear filter, which are determined as a function of the signal in the current block and comprising the coefficients of a modifying filter.

Abstract: Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between a transmitting device and a receiving device operating at high speed with low power utilization. Communication is performed using group signaling over sets of four wires using a vector signaling code, where each wire of a set carries a low-swing signal that may take on one of four signal values. Topologies and designs of wire sets are disclosed with preferred characteristics for group signaling communications.

Abstract: A system may receive filter coefficients defining a digital filter. The system may select a signal processing quality criterion which describes a transformation that can be derived from an image and further describes the reconstruction of the image that can be derived from the transformation. The system may determine a degree of optimization that quantifies the signal processing quality criterion with the received filter coefficients. The system may vary the filter coefficients to obtain varied filter coefficients. The system may establish the degree of optimization with the varied filter coefficients. The system may compare the determined degree of optimization with the established degree of optimization.

Abstract: A decision-feedback equalizer for use in a receiver unit for receiving an incoming data stream and for providing a stream of bit data outputs includes a plurality of asynchronous comparators and a fastest decision detector unit operatively coupled with the asynchronous comparators. Each of the asynchronous comparators is configured to receive an input signal and to directly provide a comparison result output in an asynchronous manner. The fastest decision detector unit is configured for receiving at least a subset of the respective comparison result outputs of the asynchronous comparators and for forwarding the comparison result of one of the asynchronous comparators towards the output of the decision-feedback equalizer. The fastest decision detector unit is configured to select a given one of the asynchronous comparators as one which firstly provided its comparison result output.

Abstract: A decision feedback equalizer (DFE) includes first through sixth flip-flops, and first and second summer circuits. The first through fourth flip-flops sample an analog input signal received at the first and second summer circuits, detect the logic level of a data bit in the analog input signal and generate the first through fourth compensated signals. The first multiplexer outputs at least one of the first and second compensated signals as a first feedback signal, based on a fourth feedback signal generated by the sixth flip-flop. The second multiplexer outputs at least one of the third and fourth compensated signals as a second feedback signal, based on a third feedback signal generated by the fifth flip-flop. The first and second feedback signals are multiplied by a weight coefficient and fed back to the first and second summer circuit, respectively, to compensate an error in the analog input signal.

Abstract: The present invention is directed to communication systems. More specifically, embodiments of the present invention provide a technique and system thereof for performing eye modulation. Eye modulation is performed at the transmission side of a PAM communication system to compensate for distortion and non-linearity and generate an output waveform. Spacing among eye levels is adjusted by performing symmetric modulation using ? parameter and asymmetric modulation using ? parameter. A correction module measures the output waveform and sends feedback signals to a control module to adjust the ? parameter and the ? parameter. There are other embodiments as well.

Abstract: A method and apparatus for performing residual phase noise compensation is described. A coarse carrier compensation of a received modulated signal is performed to obtain a coarse carrier compensated signal and a trellis-based residual carrier recovery is performed to estimate a residual phase noise of the coarse carrier compensated signal. The coarse carrier compensated signal is compensated based on the estimated residual phase noise.