Abstract: In some embodiments of the present invention, there is a system and method of synchronizing a QAM demodulator by determining a phase offset error value between an actual phase shift of a received symbol and an estimated phase shift value.

Abstract: Communication equipment having an available bandwidth less than 100 Mbps may be regarded as IEEE1394 communication equipment in which buses (21, 31) are connected together via a bridge (40). The bridge (40) includes portals (40A, 40B), and the portals (40A, 40B) communicate with each other through infrared rays. RAMs (43A, 43B) include bandwidth available registers for writing a remaining amount of an available bandwidth, which may be used in an isochronous communication within the bridge (40). ROMs (44A, 44B) store an available bandwidth, which may be used in a isochronous communication in respective infrared communication units (45A, 45B), as an initial value (BWR). When the bridge (40) is initialized, the initial value (BWR) is written in the bandwidth available registers. Thus, even when an available bandwidth between the infrared communication units (45A, 45B) is less than 100 Mbps, the bridge (40) may be regarded and operated as communication equipment in which the available bandwidth is 100 Mbps.

Abstract: A digital communication receiver includes a blind equalizer using the Constant Modulus Algorithm (CMA) to compensate for channel transmission distortion in digital communication systems. Improved CMA performance is obtained by using a partial trellis decoder to predict 1 bit or 2 bits of the corresponding 3-bit transmitted symbol. The predicted bits from the partial trellis decoder are used to reduce the effective number of symbols in the source alphabet, which reduces steady state jitter of the CMA algorithm. Specifically, the received input signal to the CMA error calculation is shifted up or down by a computed delta (&Dgr;), in accordance with the predicted bit(s). In addition, a different constant gamma (&ggr;), for the CMA error calculation is selected in accordance with the predicted bit(s).

Abstract: Analog modems are enabled to better learn the slicing levels employed at the interface to a digital transmission network by reducing the effects of the various noise sources. Initially a training sequence is received to preliminarily adjust the analog modem's equalizer. Thereafter, a special training sequence, protected against intersymbol interference, is employed to collect samples of each slicing level, to ascertain the least mean squared value of each slicing level from the received samples and to obtain the channel's impulse response at each slicing level. Depending on the means squared error (MSE) between the input and the output of the slicer, the slicer tables continue to be updated, and the feed-forward and feed-backward equalizer filters are selectively adjusted in accordance with the channel impulse response ascertained at each of the slicing levels.

Abstract: A data-decoding apparatus having bit-detecting section 4. In the apparatus, an RF signal is reproduced from a recording medium and converted to digital data. If the RF signal has a level (amplitude) equal to a comparator level, the bit-detecting section 4 outputs channel-bit data having logic level “0” or “1” in accordance with whether the sum of the amplitudes of the two RF signals respectively preceding and following that RF signal is higher or lower than the comparator level.

Abstract: A method of determining a frame rate of a data frame in a communication system by using apriori knowledge of data frame. In one embodiment, a signal is received at the communication device. Then a data frame portion of the signal is isolated. Next, a potential frame rate is chosen and the data frame is formatted accordingly. Decoding, at the chosen potential frame rate, occurs on the data frame. Then, a tail bit portion of the data frame is isolated. Afterward, a logic level of the decoded tail bit data is compared against the apriori knowledge of a transmitted logic level for the tail bit portion of the data frame. In addition, comparisons are also made between other data metrics and their expected values. Finally, a level of confidence is communicated to the communication device based upon a result of the comparisons.

Abstract: The invention relates to a method and a device for estimating the DC offset portion of a signal, especially of a signal containing parts with sinusoidal shaping, for example a signal which results from demodulation of a frequency modulated receive signal.

Abstract: For restraining jitter amount of a transmission clock signal (16) generated by a digital PLL (8), a data transmission apparatus comprises a {fraction (1/24)} clock generator (6) for dividing frequency of a receiving clock signal (4), a clock multiplier (7) for generating a reference frequency signal (18) by multiplying frequency of the output of the {fraction (1/24)} clock generator (6), and a control unit (28) for controlling a frequency multiplying ratio of the clock multiplier (7) and controlling a frequency dividing ratio of a frequency divider provided in the digital PLL (8). According to jitter amount detected by a jitter detection signal generator (19), the frequency of the reference clock signal (18) is selected among {fraction (1/12)}, ⅛ and ⅙ of the frequency of the receiving clock signal.

Abstract: A digital transmission system (1) comprises: a transmitter (2), a receiver (3), and a transmission channel (4) coupled there between. Both the transmitter (2) and the receiver (3) are provided with an encoder (5) and a decoder (6) respectively, wherein a multilevel input signal is coded such, that a DC-balanced digital channel code is transmitted. The coders (5, 6) are embodied to match levels of the DC-free multilevel input signal and code words of the DC-balanced digital channel code such, that disparities of the selected code words are symmetrically grouped around zero disparity. This results in a DC-free digital channel code signal having a limited transmission band width, which signal can be conveyed with minimal hardware over the usually AC-coupled transmission channels.

Abstract: A circuit for developing correction signals for on-line controlling a precorrection arrangement in an HDTV 8VSB digital signal transmitter. The transmitted signal is sampled, sorted, smoothed and sliced to determine the symbol amplitude levels of the transmitted multilevel symbols. The centers of the sliced clusters of sampled symbol levels are used to determine the symbol amplitude levels. Correction signals for compensating the precorrection arrangement are developed based upon the determined symbol levels and the known symbol levels.

Abstract: A CDMA signal processing circuit (300) includes a summer circuit (302) that receives a plurality of CDMA signals from a plurality of channels (304). The summer circuit (302) combines the plurality of CDMA signals according to a power magnitude value and power direction value associated with each CDMA signal. The summer circuit (302) generates a summed signal (306) that is applied to a clipping circuit (308). The clipping circuit (308) removes a portion of the summed signal (306) outside a desired threshold range and generates a clipped signal (310) therefrom. Digital to analog processing circuits (312 and 314) convert the clipped signal (310) into a half width encoded format. Digital to analog processing circuits (312 and 314) transform the half width encoded clipped signal into analog I and Q signals, respectively. The analog I and Q signals are applied to corresponding filters (316 and 318) prior to transmission.

Abstract: A closed feedback loop controls the slicing, or detecting, of an incoming data signal. Detected signal information about the positive and negative peaks of the incoming data signal is processed to generate positive and negative peak reference signals which serve as reference signal levels for establishing the thresholds at which signal slicing takes place.

Abstract: A data transmission device which improves data transmission efficiency is disclosed. A data transmission device includes a decoder converting a first binary data to a ternary data, a ternary data generator coupled to the decoder and generating three logic levels corresponding to a power source voltage, an intermediate voltage, and a ground voltage, the intermediate voltage having a voltage level between the power source voltage and the ground voltage, a ternary data detector coupled to the ternary data generator and converting the three logic levels from the ternary data generator to pairs of second binary data, and an encoder coupled to the data detector and restoring the pairs of second binary data to the first binary data.

Abstract: An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Abstract: In the transmission of ATM cells, there is often the requirement to: This measurement is usually implemented within a fixed time interval but this can be problematical insofar as this type of measurement leaves the type of connection out of consideration. The invention alleviates this situation in that the traffic characteristic of the ATM cells functions as the criterion for when a measurement is to be implemented.

Abstract: A method of detecting signals propagated on a carrier medium includes the step of determining a noise threshold level, relative to a noise floor on a carrier medium, such as for example POTS wiring. A peak threshold level is then determined relative to peaks of a data signal. A data threshold level is then calculated utilizing the noise threshold level and the peak threshold level. For example, the noise threshold level and the peak threshold level may be averaged to calculate the data threshold level. A data signal pulse is then detected on traversal of the data threshold level by the data signal.

Abstract: A comparator detects rising transitions of an input waveform and another comparator detects falling transitions. Each comparator detects their respective transition with a different threshold voltage. The outputs of these comparators are multiplexed into the clock input of a flip-flop. The flip-flop's inverted output is connected through a time delay to the input of the flip-flop to form a toggling configuration. The output of the time delay is also connected to the select input of a multiplexer that controls the multiplexer to multiplex the outputs of the two comparators into the clock input of the flip-flop. The threshold voltages chosen for the two comparators are chosen to be in the center of the incident edges of the distorted signal of a source-terminated transmission line. The time delay is chosen to be longer than the difference between the arrival of the incident wave and the arrival of the first reflected wave.

Abstract: A radio receiver circuit (200) is used for receiving a multi-level signal (201) that includes a plurality of symbols, wherein each level is representative of a symbol of data. Baseband samples are generated for each symbol, whereby each baseband sample has a phase and a signal level. The radio receiver circuit (200) measures the received signal environment. A digital circuit (212) selects a scan duration from a scan duration table (251) based on the measured signal environment and a combination of signal types used for classification of the received signal. The digital circuit tallies, by category, occurrences of the baseband samples, whereby each category is representative of one of a plurality of phases, and one of a plurality of signal level ranges.

Abstract: A preemptive processor for a tactical collision avoidance system (TCAS) selects mode S squitter messages from closer airplanes on a priority basis. The receiver has a higher sensitivity level to receive squitter messages at greater ranges. The high-level squitter messages preempt the lower-level squitter messages. The preemptive processor can be implemented as part of a application-specific integrated circuit (ASIC).

Abstract: A closed feedback loop controls the adaptive equalization of an incoming data signal received via a cable. Detected signal information about the positive and negative peaks of the incoming data signal during different windows in time is processed to generate a set of adaptive equalization control signals which identify differences, if any, between the positive and negative peaks of the present data signal and those which are desired. These equalization control signals control an input signal equalization circuit which adaptively adjusts the waveshape of the present data signal to bring it into conformance with the desired waveshape.

Abstract: The present invention discloses a much higher speed interface apparatus which comprises a data driving means for decoding two-bit data signals using them as inputs to output four-level data signals; a reference voltage generating means for generating three-level reference voltages to discriminate the voltage levels of the four-level data signals; and a receiver means for comparing the four-level data signals and the three-level reference voltage signals using them as inputs and for encoding the resulting signals to output two data signals.

Abstract: Digital amplitude values of multilevel signals of repeated transmissions are stored in respective locations of a memory which respectively correspond to the transmissions, and a set of amplitude values are simultaneously read from the memory locations and compared with decision threshold bands which respectively represent data symbols. A decision is made in favor of the data symbol of a decision threshold band if majority of the set of amplitude values are lying within the decision threshold band, or in favor of the data symbol of a decision threshold band if only one of the set of amplitude values is lying within or nearest to the decision threshold band and other amplitude values of the set are not nearer to any of the decision threshold bands than the only one amplitude value is near to the decision threshold band.

Abstract: At least two level detectors compare a multilevel signal to respective prescribed voltage levels to produce corresponding streams of bits. These bit streams are repeatedly delayed in respective digital delay lines, and bits from the digital delay lines are output in parallel to multilevel decoder logic. The multilevel decoder logic converts the parallel bits into a plurality of corresponding two-level decoded bits and performs error detections for an invalid transition in the multilevel signal. The decoded bits may be descrambled and block decoded.

Abstract: In a selective call radio receiver for receiving a radio communication signal to produce a communication datum of a multiplicity, such as 256, of levels and an intermittent succession of synchronization patterns, a combination of a pattern detector, a sample memory, and a threshold calculator detects a predetermined number, such as three, of detected threshold levels in each synchronization pattern. A threshold memory stores first to N-th past sets of stored threshold levels, N being equal to two or greater. Based on a current set of the detected threshold levels and the past sets, a threshold comparator generates optimum threshold levels for use in a discriminator for judging the communication datum as a multilevel, such as four-level, receiver output signal.

Abstract: In a transmission system digital symbols are transmitted by a transmitter via a channel to a receiver. The receiver comprises a first detector and a second detector with different decision levels. In the case of an unreliable input signal of the detectors, the sequences of detected symbols at the outputs of the detectors may differ. By checking the sequences of digital symbols on code rule violations, the most likely sequence of detected symbols can be selected by a selector and passed to the output.

Abstract: An analog waveshaping circuit is capable of performing waveshaping of an AC analog signal in which the positive and negative peak levels with respect to a reference level are not the same, while considering a DC offset component of the reference level of the analog waveform, so that the positive and negative levels with respect to the reference level are made equal.

Abstract: A dual reference voltage input receiver comprises a latch, comparison logic for determining the voltage level of a data signal relative to that of first and second reference voltage levels, and selection logic for determining which of the reference voltage levels is operative for a given data interval, e.g. clock cycle. The latch couples the determined voltage level of the data signal to a subsequent stage and to the selection logic for determining the operative reference voltage level in the next data interval. In one embodiment of the invention, the comparison logic includes first and second comparators for comparing the data signal with first and second reference voltages, and the selection logic is a MUX having its data inputs coupled to the comparators' outputs and its selection input coupled to the data output of the latch.

Abstract: A data receiving apparatus, a demodulator circuit and an integrated circuit that are simplified in the general constitution and enable the consumed power to be reduced. After decomposed into both the comparison result (S7) between an optional threshold controlled corresponding to the DC offset of the demodulated signal (S3) and the absolute value of the amplitude of the demodulated signal (S3) and the detected result (S8) of detecting the polarity of the demodulated signal (S3), transmitted data (S5) represented by the amplitude of a demodulated signal (S3) containing the amplitude component corresponding to the transmitted data (S5) are outputted and the transmitted data (S5) are regenerated by using these comparison result (S7) and detection result (S8).

Abstract: The disclosed data processor develops a data signal which has a plurality of multi-level symbols. The data processor, in response to each of the symbols, determines the lowest path metric characterizing the data signal, and selects one of a plurality of sets of slice values in response to the lowest path metric. A slicer responds to the selected set of slice values by slicing the multi-level symbols. There may be only two sets of slice values in the plurality of sets of slice values, wherein each of the only two sets has three slice levels. Alternatively, there may be only five sets of slice values in the plurality of sets of slice values, wherein each of the only five sets has five slice levels. As a still further alternative, there may be only two sets of slice values in the plurality of sets of slice values, wherein each of the only two sets has a minimum of six slice levels.

Abstract: The level of a symbol information in a symbol-sync part transmitted for the purpose of synchronizing a receiver of a digital radio communications system reflects the state of the concurrent transmission. With this factor taken in account, a symbol determining method is provided which comprises the steps of receiving a symbol information extracted from a symbol-sync part of a received signal obtained by demodulating a received wave and digitizing it; generating thresholds for use to determine the value of the received symbol based on the reception level of the symbol information; determining the value of the received symbol in the data part of the received data based on the thresholds; and reproducing the symbol. Therefore, even if a received symbol is deteriorated due to a degradation, etc. of transmission line, a symbol determination can be done with no degradation of the signal reception due to a narrowing of noise margin, etc.

Abstract: A bus to bus bridge deadlock prevention system detects and resolves a deadlock condition in a bus to bus bridge. In a PCI protocol application of the present invention, the system detects a retry of a request by a master device. The request is masked for a delay period before the request is allowed to attempt to pass through a PCI to PCI bridge. If the request results in a further retry, the delay period length is changed and the request is masked for the different delay period. Successive retry requests are masked for different delay periods until the deadlock condition is resolved. The system adapts to the deadlock condition by repeatedly changing the delay period until the deadlock condition is resolved and the bridged busses resume normal operation.

Abstract: An apparatus and method adaptable to desired offsets for determining an undesired offset of a signal having a maximum and a minimum state that includes: providing a peak and trough estimate of, respectively, the maximum and minimum amplitude state; averaging such estimates to provide a reference level that is proportional to the undesired offset; and controlling the peak and trough estimates whenever a comparison of the signal and the reference level is, respectively, indicative of the maximum and minimum amplitude states to thus assure adaptation to the desired offset of the signal.

Abstract: A DC restoration circuit to correct for baseline wandering in a data receiver is provided. A voltage correction circuit is connected to the received data line to adjust the voltage level of the received data dynamically. The voltage correction circuit is controlled by a feedback circuit which includes a voltage detection circuit configured to detect the peak voltage levels or envelope of the received data. This detected level is then compared to a reference level, and the result of the comparison is used as a control signal for the voltage correction circuit.

Abstract: A blind-equalization method and apparatus are disclosed for equalization of a channel of an HDTV receiver. The HDTV receiver comprises a rejection filter corresponding to a precoder for which precoding is implemented at a television transmitter for combating co-channel interference, wherein the television transmitter transmits a digital television signal. The HDTV receiver further comprises an equalizer having an input and an output. The equalization method comprises the steps of initiating an equalization with a blind slicing mode. The method further comprises changing the equalization to a training sequence mode upon an occurrence of a no flutter condition. While in the training sequence mode, if a flutter condition occurs, then the equalization is returned to the blind slicing mode. A determination of the occurrence of the flutter condition is based upon an estimate of a negative derivative of the Signal-to-Noise Ratio (SNR) at the output of the equalizer, dS.sub.

Abstract: A radio receiver circuit (100) is used for receiving a multi-level signal from a radio communication system. The multi-level signal includes a plurality of symbols, wherein each level is representative of a symbol of data. The receiver circuit (100) includes a demodulator circuit (106) and a digital circuit (112). The demodulator circuit (106) is used for receiving the multi-level signal and for generating baseband samples for each symbol, whereby each sample has a phase and a signal level. The digital circuit (112) is coupled to the demodulator circuit (106), and is adapted to tally, by category, occurrences of the baseband samples, whereby each category is representative of one of a plurality of phases, and one of a plurality of signal level ranges. The digital circuit (112) is further adapted to correlate the categories to at least one predetermined template, and to classify the multi-level signal according to the correlation results.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Abstract: The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.

Abstract: A received and demodulated multi-level signal (32) is corrected for D.C. offset by a feedback loop (34) which applies a correction signal (38) to the multi-level signal (32). Initial coarse correction is provided by feeding the corrected signal (42) into the feedback loop where a low pass filter (36) averages the corrected signal over time and detects departure from zero of this time-averaged signal. After initial coarse correction, finer correction of D.C. offset is provided in a data-aided mode in which detected data values (46) are fed into the feedback loop (34). The method achieves D.C. offset correction without the need to know anything about the data pattern of the received signal (32).

Abstract: A CDMA signal processing circuit (300) includes a summer circuit (302) that receives a plurality of CDMA signals from a plurality of channels (304). The summer circuit (302) combines the plurality of CDMA signals according to a power magnitude value and power direction value associated with each CDMA signal. The summer circuit (302) generates a summed signal (306) that is applied to a clipping circuit (308). The clipping circuit (308) removes a portion of the summed signal (306) outside a desired threshold range and generates a clipped signal (310) therefrom. Digital to analog processing circuits (312 and 314) convert the clipped signal (310) into a half width encoded format. Digital to analog processing circuits (312 and 314) transform the half width encoded clipped signal into analog I and Q signals, respectively. The analog I and Q signals are applied to corresponding filters (316 and 318) prior to transmission.

Abstract: An apparatus and method for receiving line encoded bursts of information removes unwanted background light and has a maximum inter-packet idle time of only one bit between bursts. The invention permits the use of AC coupling in a receiver and results in outputting data with constant pulse widths irrespective of optical signal power levels, etc. . . In one embodiment, a receiver has a wide dynamic range, is highly stable, may be used over all frequencies of interest without developing high speed electronics or optical components, and has no sensitivity penalty as compared to existing burst mode/packet mode receivers. Because the receiver completely removes common signals, base line wander problems are also removed. The inventive apparatus and method is superior to existing burst mode/packet mode receivers in the presence of unwanted background light and long runs of "1"s and "0"s.

Abstract: According to the present invention, an improved CDMA receiver for receiving spread-spectrum-modulated signals is provided. In the improved receiver, a multicarrier signal processor is positioned. The multicarrier signal processor includes a controller for analyzing an incoming multicarrier signal. At least one signal modifier communicates with the controller, such that the controller directs signal modifier to attenuate at least one carrier signal which is not spread-spectrum-modulated. More particularly, the present invention provides an apparatus for attenuating carrier signals in a multicarrier signal which includes at least one spread-spectrum-modulated signal and other carrier signals. The apparatus comprises a receiver for receiving a multicarrier signal which includes at least one spread-spectrum-modulated signal and other carrier signals.

Abstract: In a digital transmission system including a transmitter (2) coupled via a channel (4) to a receiver (6) a detection signal r.sub.k is compared with a number of reference values to determine the destination symbols a.sub.k. Since the size of the received signal r.sub.k is not known in advance, the ratio between the detection signal and the reference values is to be determined by an adapting circuit (16) on the basis of the received signal and the decisions made. The problem may then occur that as a result of an initially erroneous value of the ratio between detection signal and reference values not a correct adaptation is made. By recognizing such a situation because specific values of the symbols a.sub.k are lacking, in such a situation said ratio can be brought to such a value by the correction circuit (18) that all the values of a.sub.k again occur.

Abstract: Symbol recovery for multi-level digital signals has traditionally been difficult because of the nature of the eye pattern output by the discriminator (103), and especially its response to a noisy or impeded signal environment. This method and apparatus for recovery thresholds adjusts (411 and 417) to the current state of the discriminator (103) output of the received signal, based on an attenuated (301) version of that signal. Using a fast adjust mode and slow adjust mode, the threshold generating circuitry (331 and 361) adapts to the signal based on data from the received signal fed into lock detectors (329 and 359) which determine the mode to use.

Abstract: In optical transmission systems it is desirable to increase the bit rate of digital signals to, e.g., 40 Gb/s and more. In such systems there is an upper bit-rate limit above which conventional directly modulated lasers and their drive electronics cannot be employed. An optical transmission system is disclosed in whose optical transmitter (1) an electric multilevel signal (V) composed of two electric digital signals (V.sub.1, V.sub.2) modulates a semiconductor laser (4), so that an optical multilevel signal (V) is transmitted. The optical receiver (2) contains a decision circuit (7) which recovers the digital signals (V.sub.1, V.sub.2).

Abstract: A transmission-reception circuit, including a transmitter circuit and a receiver circuit connected to each end of a transmission line, for transmitting and receiving a signal to another receiver circuit and from another transmitter circuit at the other end across the transmission line, wherein in order to enable logical decision on a receiving signal to be made accurately and secure high reliability in a fully duplex simultaneous two-way communication, power supply lines are laid at opposite ends of the transmission line and threshold voltages for logical decision on a signal received by the receiver circuit are supplied from a power unit used for the transmitter circuit and the receiver circuit at the other end of the transmission line.

Abstract: A data communication circuit comprising a slave device (3), a master device (2) and a two-wire bus (6) wherein the master device (2) creates a potential difference (V(t)) between the two wires so as to provide power to the slave device (3). The slave device (3) comprises a pulse decoder (20) for detecting the pulses and producing a synchronisation signal (Clk) upon the detection of each pulse. The master device (2) also comprises a pulse control circuit (40) for causing the pulse creating circuit to create a series of data pulses having the same state when the digital information is read from the slave device (3). In addition, the slave device (3) further comprises a circuit (43,58) for changing the state of selected ones of the data pulses in the series in response to the digital information to be read.

Abstract: A method of encoding data for transmission over a communication link. A cumulative polarity of previously-transmitted frames is maintained. A frame is prepared for transmission by combining a data word with a plurality of additional bits. The additional bits provide a master transition. A phantom bit is encoded in the additional bits. If the polarity of the frame is the same as the cumulative polarity, the data bits or in some instances all the bits are inverted so as to maintain balance. Control words and fill words are provided and are distinguished from data words by encoding the additional bits. Control words carry additional data or control instructions and are distinguished from fill words by the number of transitions. The phantom bit either conveys additional data or is used for such purposes as error checking.

Abstract: In a radio communication apparatus comprising a demodulator (12) for demodulating a multilevel modulated signal (10) into a time sequence of multilevel symbols which have symbol levels to define a variable pattern by a level difference between the symbol levels of at least two successive adjacent ones of the multilevel symbols, a coincidence detecting section (16) detects coincidence between the variable pattern and a predetermined pattern and calculates judgement levels when the variable pattern coincides with the predetermined pattern with a tolerance. A multilevel-to-binary converter (14) converts the time sequence of multilevel symbols into a binary signal of binary values by judging the symbol levels on the basis of the judgement levels. Preferably, a variation following level calculating section (30) calculates variation following levels for use as the judgement levels by using the symbol levels, the binary values, and the judgement levels.