Abstract: Receive operations at a receiver may be improved by performing one or more estimations before receiving data. For example, the time between the end of the header transmission and the start of the data transmission may be used to send patterns to be used for an estimation. In some implementations, sequences of pilot repetitions may be used to adapt the operation of a receiver. In some implementations, short training fields may be used to adapt the operation of a receiver.

Abstract: According to one embodiment, a memory system comprises an encoder that encodes by a graph code and a data holding unit that holds data to be used in encoding. A check matrix of the graph code includes first to sixth submatrices, and the encoder produces a first vector obtained by multiplying an information word and the first submatrix, produces a second vector obtained by multiplying the information word and the third submatrix, produces a third vector obtained by multiplying the first vector and the fifth submatrix inverted in sign, produces a fourth vector obtained by adding the third vector and the second vector, produces a first parity obtained by multiplying the fourth vector and the data, produces a fifth vector obtained by multiplying the first parity and the second submatrix inverted in sign, and produces a second parity obtained by adding the fifth vector and the first vector.

Abstract: A 1553 data communication system having a primary data bus, a redundant data bus and a non-1553 data communication overlay system is provided. The non-1553 data communication overlay system comprises a non-1553 bus controller terminal and a non-1553 remote terminal. Each non-1553 terminal includes a non-1553 transmitter block connected to the primary bus and the redundant bus for sending non-1553 signals, a non-1553 receiver block for receiving non-1553 signals and a non-1553 receive path selection block. The non-1553 receive path selection block selectively establishes a receive path between the primary data bus or the redundant data bus and the non-1553 receiver block according to predefined receive path selection criteria. A 1553 data communication method is also provided.

Abstract: A method for modulation of a signal with first binary data is provided in which the first binary data include a sequence of first binary numbers, wherein each first binary number includes either a first binary numerical value or a second binary numerical value. The method includes generating ternary data that includes a sequence of ternary numbers, where each ternary number comprises a first, second, or third ternary numerical value. The method also includes modulating a phase of the signal with the ternary data, where the phase of the signal can assume M different phase states, where M>2. The first, second, and third ternary numerical values correspond to first, second, and third state transitions between the M phase states. In the first state transition, a phase state is maintained, while in the second state transition and third state transition a change in the phase state is produced.

Abstract: The present disclosure is directed to an FM demodulator having an extended threshold breakdown point. The FM demodulator uses an arcsin demodulator in combination with a frequency compressive loop to produce a demodulated output signal. The FM demodulator includes three filters that use a coefficient ? to determine how the filters behave. The FM demodulator extends the threshold breakdown point of the signal-to-noise ratio of the FM signal beyond traditional levels, allowing the FM demodulator to work at long distances from the broadcasting antenna.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L?m of each candidate vector holding one of a plurality of possible values of the symbol L?m, with m is an integer greater than or equal to 1, and elements L?m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L?m may be selected.

Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.

Abstract: One embodiment of the present invention relates to an apparatus for preventing remodulation in a transmission chain. A first offset generation circuit selectively introduces a first frequency offset into in-phase (I) and quadrature phase (Q) equivalent baseband signals. A second offset generation circuit selectively introduces a second frequency offset into an oscillator output signal. The frequency of the offset oscillator output signal is divided by a divider to form offset local oscillator signals, which are provided to up-conversion mixers that modulate the offset equivalent baseband signals onto the offset local oscillator signals to generate a composite modulated output signal. The first and second frequency offsets are chosen to have values that cancel during modulation. However, because the second frequency offset shifts the offset oscillator output signal's frequency to a value that is no longer a harmonic of the composite modulated output signal's frequency, remodulation is prevented.

Abstract: Disclosed is a polybinary-signal generator in which correlative coding is applied to a plurality of fractional-bit-rate signals instead of being applied to a corresponding multiplexed full-bit-rate signal. The resulting coded fractional-bit-rate signals are variously delayed with respect to one another and then summed to generate a polybinary output signal. One beneficial feature of this architecture is that most circuit components of the polybinary-signal generator operate at the fractional bit rate, which helps to alleviate at least some of the technical difficulties associated with the design of radio-frequency circuits intended for relatively high bit rates. Another beneficial feature of this architecture is that the polybinary-signal generator also serves as a signal multiplexer.

Abstract: A multimedia information receiving apparatus receives multimedia information which is transmitted by a broadcast system and receives multimedia information which is simultaneously transmitted by another transmission system such as IP communications, and generates one received information by selecting elements having a few errors from elements of demodulated broadcast system information and elements of demodulated other transmission system information and then arranging the selected elements.

Abstract: A pipelined decision feedback unit (DFU) is disclosed for use in reduced-state Viterbi detectors with local feedback. The disclosed pipelined decision feedback unit improves the maximum data rate that may be achieved by the reduced state Viterbi detector by the pipelined computation of partial intersymbol interference-based estimates. A pipelined decision feedback unit is thus disclosed that computes a plurality of partial intersymbol interference based estimates, wherein at least one partial intersymbol interference-based estimate is based on a selected partial intersymbol interference-based estimate; and selects the selected partial intersymbol interference-based estimate from among partial intersymbol interference-based estimates for path extensions into a state.

Abstract: A receiver may be operable to receive an inter-symbol correlated (ISC) signal, and generate a plurality of soft decisions as to information carried in the ISC signal. The soft decisions may be generated using a reduced-state sequence estimation (RSSE) process. The RSSE process may be such that the number of symbol survivors retained after each iteration of the RSSE process is less than the maximum likelihood state space. The plurality of soft decisions may comprise a plurality of log likelihood ratios (LLRs). Each of the plurality of LLRs may correspond to a respective one of a plurality of subwords of a forward error correction (FEC) codeword.

Abstract: Provided is a data transmission device and a symbol generation method of the same. A data processing unit of a data transmission device according to an embodiment of the present invention accesses a memory device for reading another data block while symbols for one data block are generated.

Abstract: A method and system for a sequence estimation in a receiver, such as for use when receiving a sample of a received inter-symbol correlated (ISC) signal corresponding to a transmitted vector of L symbols, with L being a integer greater than 1, and with symbol L being a most-recent symbol and symbol 1 being least recent symbol of the vector. A plurality of candidate vectors may be generated, wherein element L-m of each candidate vector holding one of a plurality of possible values of the symbol L-m, with m is an integer greater than or equal to 1, and elements L-m+1 through L of each candidate vectors holding determined filler values. A plurality of metrics may be generated based on the plurality of candidate vectors, and based on the generated plurality of metrics, a best one of the possible values of the symbol L-m may be selected.

Abstract: A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.

Abstract: A memory system with a simultaneous bi-directional link includes a controller, a memory device and a set of signal lines coupled to the controller and the memory device. Simultaneous communication between the controller and the memory device on the set of signal lines uses a first band of frequencies, and between the memory device and the controller on the set of signal lines uses a second band of frequencies. The controller is configured to dynamically adjust the first band of frequencies based on a predetermined data rate between the controller and the memory device and to dynamically adjust the second band of frequencies based on a predetermined data rate between the memory device and the controller.

Abstract: A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

Abstract: An exemplary method is disclosed to accurately estimate the center frequency of a narrow-band interference (NBI). The exemplary method uses multi-stage autocorrelation-function (ACF) to estimate an NBI frequency. The exemplary method allows an accurate estimation of the center frequency of NBI in an Ultra-Wideband system. A narrow band interference (NBI) estimator based on such a method allows a low complexity hardware implementation. The exemplary method estimates the frequency in multiple stages. Each stage performs an ACF operation on the received signals. The first stage gives an initial estimation and the following stages refine the estimation. The results of all stages are combined to produce the final estimation. An apparatus based on such a multi-stage narrow band interference frequency detector is also disclosed to improve the accuracy by combining various filters with the detector.

Abstract: A code division multiplex signal transmitter includes an operational circuit, a modulator unit and a multiplexer. The operational circuit adds up input transmission data on channels to produce resultant added data and modulates pieces of bit transmission data which are indicative of the values of the respective bits of the added data, when expressed in binary form, the pieces of bit transmission data being equal in number to the M bit positions of the added data expressed in binary form. The modulator unit includes modulators corresponding in number to the M bit positions of the added data in the binary form. A k-th modulator, where k is an integer of 1 to M, inclusive, modulates a k-th piece of bit transmission data to produce a k-th bit modulated signal whose amplitude level is 2k-1. The multiplexer multiplexes first to M-th bit modulated signals to produce a code division multiplex signal.

Abstract: An apparatus and method for assigning subchannels of a transmitter in a communication system. The method includes dividing an entire frequency band into m subcarrier groups; mapping each of the m subcarrier groups to a subcarrier group index, wherein a subchannel includes n subcarriers selected from each of the m subcarrier groups corresponding to a subcarrier group index sequence; determining that a first data is needed to transmit in a first timing point; and assigning a first subchannel in the first timing point using a first subcarrier group index sequence. The first subcarrier group index sequence is different from a second subcarrier group index sequence used for assigning a second subchannel in a second timing point.

Abstract: A multi-slicing horizontal synchronization signal generating apparatus and method is provided. The apparatus includes a slicer, a numerically controlled oscillator (NCO), a first phase detector, a second phase detector and a calibration circuit. The slicer performs edge detection on a video signal having a first horizontal synchronization, and generates a first detection signal and a second detection signal according to a first voltage level and a second voltage level, respectively. The NCO generates a second horizontal synchronization signal. The first phase detector detects a first phase difference between the first detection signal and the second horizontal synchronization signal, and the second detector detects the second phase difference between the second detection signal and a reference time point. The calibration circuit generates a calibration signal according to the first phase difference and the second phase difference.

Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.

Abstract: An estimator of the noiseless output of a noisy partial response channel is described. The estimator operates recursively. In each iteration, the estimator processes a window of the N most recently received noisy channel outputs to compare output level metrics for all possible channel output level, and selects a noiseless output level with maximal posterior probability.

Abstract: A partial response signaling system includes a transmitter circuit configured to equalize input data in response to a control signal and to transmit a partial response signal through a transmission medium; and a receiver circuit configured to recover an output data from the partial response signal and to generate the control signal based on the partial response signal and an expected signal to output the control signal to the transmitter circuit.

Abstract: A non-linear post-processor for estimating at least one source of signal-dependent noise is disclosed. The post processor may receive a set of preliminary decisions from a sub-optimal detector along with the sampled data signal. The post-processor may then compute the transition jitter and white noise associated with each preliminary decision in the set and assign a cost metric to each decision based on the total signal noise. The post-processor may output the decision with the lowest cost metric as the final decision of the detector.

Abstract: An upstream signal power in a communication system is optimized. At least one system parameter is determined and a bits and gains table is modified. For example, a maximum received power parameter for the transmitting device is used by the receiving device to calculate a power backoff parameter. The power backoff parameter is used to calculate the bits and gains table which is then used by the transmitting device. The new SNR may be estimated. This estimation may distinguish between noise sources that vary with the signal level received and those that do not.

Abstract: In a method of data transmission according to one embodiment of the invention, data transitions on adjacent conductors are separated in time. In a method of data transmission according to another embodiment of the invention, signals on adjacent conductive paths pass through different alternating sequences of inversions and regenerations. In a method of data transmission according to a further embodiment of the invention, data transitions having the same clock dependence are separated in space.

Abstract: In the present multilevel signal receiver, an output signal of a comparator which judges a high-level of a multilevel signal and a signal obtained by inverting an output signal of a comparator which judges a low-level of the multilevel signal are input to an edge-triggered RS-FF, and an output signal of the edge-triggered RS-FF is fed back to the comparator on the high-level side via a LPF, so that a high-level threshold voltage is regulated. At the same time, a signal obtained by inverting the output signal of the comparator on the high-level side and the output signal of the comparator on the low-level side are input to an edge-triggered RS-FF, and an output signal of the edge-triggered RS-FF is fed back to the comparator on the low-level side via a LPF, so that a low-level threshold voltage is regulated.

Abstract: A repeatable read-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values that represent RRO data. The asynchronous sample values are read from a recording medium and generated by an A/D converter at a symbol rate, and the interpolators generate interpolated samples at at least one time in between the asynchronous sample value times. Each interpolated sample corresponding to some phase relative to that of the sample values generated by the A/D converter. The RRO detector receives 1) the asynchronous samples at symbol rate and 2) the interpolated samples to efficiently detect the encoded RRO data. An RRO address mark indicates when detection of encoded RRO data starts, and is employed to select those samples suitable for RRO data detection. Detection of the RRO address mark employs peak detection among filtered asynchronous and interpolated samples. The process of peak detection adjusts the current best phase for sample selection.

Abstract: The apparatus for transmitting and receiving data according to the invention contains a transmitter (1) for serial data transmission and a receiver (3) for receiving a transmitted data signal (g(t)). The receiver (3) in turn comprises a first sample latch (11) for sampling the received data signal (g(t)) with a first clock (f2) and for generating a first sample value (an). The receiver (3) also comprises a second sample latch (13) for sampling a first shifted received data signal (g(t)+V1) with a second clock (f1) and for generating a second sample value (yn). The receiver (3) further comprises a third sample latch (14) for sampling a second shifted received data signal (g(t)?V1) with the second clock (f1) and for generating a third sample value (zn). Finally the receiver (3) comprises a logic unit (15) for recovering data (dn) out of said first, second and third sample values (an, yn, zn).

Abstract: The invention relates to an apparatus of transmitter and receiver for Multiple Input/Multiple Output MultiCarrier-Code Division Multiple Access (MIMO MC-CDMA) systems. At the transmitter, modified orthogonal transmit diversity (MOTD) encoders are used for increasing space and time transmission diversity. A P-way combiner is used to connect the MOTD encoders and P multi-carrier modulators. Each modulator is connected to a set of antennas. At the receiver, each multi-carrier demodulator has an amplitude/phase compensator to compensate distortion at every sub-carrier. Similarly, a combiner is used to connect the demodulators and the MOTD decoders. Upon the invention, the space, time, and frequency diversity can be explored.

Abstract: A magnetic recording/reproducing apparatus includes a partial-response equalization circuit having frequency characteristic of cutting off low-frequency signal components inclusive of DC components; and a maximum-likelihood decoder, in which a reproduced signal outputted from the reproducing head is processed by the partial-response equalization circuit and then inputted into the maximum-likelihood decoder to be data-reproduced, thereby reducing a noise and distortion on the reproduced signal and reducing a data detection error rate.

Abstract: A transmitter of digital data includes a modulator with an input for a carrier signal and an input for a first stream of control symbols. The modulator modulates the carrier signal with a second stream of symbols produced by the modulator. Each symbol of the second stream has a value that corresponds to a sum of the present control symbol and the last K first symbols of the first stream. The integer K is greater than one.

Abstract: A repeatable read-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values that represent RRO data. The asynchronous sample values are read from a recording medium and generated by an A/D converter at a symbol rate, and the interpolators generate interpolated samples at at least one time in between the asynchronous sample value times. Each interpolated sample corresponding to some phase relative to that of the sample values generated by the A/D converter. The RRO detector receives 1) the asynchronous samples at symbol rate and 2) the interpolated samples to efficiently detect the encoded RRO data. An RRO address mark indicates when detection of encoded RRO data starts, and is employed to select those samples suitable for RRO data detection. Detection of the RRO address mark employs peak detection among filtered asynchronous and interpolated samples. The process of peak detection adjusts the current best phase for sample selection.

Abstract: A method of transmitting convolutionally encoded data with separate, independent and looped encoding over at least one data portion. The data is distributed over one or more cycles, and a plurality of cycles can be grouped into packets for discontinuous transmission if necessary. Weighted decoding is effected independently and cycle by cycle: it starts at a robust location, with a relatively high likelihood, and terminates at a weak location, with a weak likelihood, ignoring the concept of time. This limits the size of the packets of errors and prevents the propagation of packets of errors due to scrambling. Independent encoding and decoding of data can be effected without exchanging parameters between cycles and the parameters of each cycle (size, redundancy, constraint length) can be separate. Different degrees of protection and time-delay are permitted as a function of the nature of the data to be transmitted (voice, digital data, signaling, etc.).

Abstract: A premodulation precoding method precodes a data sequence in a Gaussian minimum shift keying (GMSK) modulator to improve the bit error rate performance of a coherent Viterbi receivers generating estimates of the communicated data sequence without the use of differential decoding while preserving the spectrum of 2-ary and 4-ary GMSK signals over a wide range of bandwidth time products.

Abstract: A transmitter of digital data includes a modulator with an input for a carrier signal and an input for a first stream of control symbols. The modulator modulates the carrier signal with a second stream of symbols produced by the modulator. Each symbol of the second stream has a value that corresponds to a sum of the present control symbol and the last K first symbols of the first stream. The integer K is greater than one.

Abstract: A method and system of reducing inter symbol interference (ISI) in a multibit symbol modulation scheme. Adjacent symbol pulses are forces to have opposite polarities. Additional phase slots are added to the symbol to modulate any bits lost because amplitude modulation cannot be used. The width of the phase slots is reduced as a result of reduced DC drift and, therefore, ISI.

Abstract: A method of decoding a digital signal includes processing the digital using a delay operation in accordance with a frequency characteristic of 1+D, where D is an output signal of the delay element. The processed digital signal is then converted to a three level conversion signal (0, positive, negative). The conversion signal is then processed in accordance with a frequency of 1/(1+D) to generate a decoded signal. The conversion signal is also checked to determine if there is a conversion error. If a conversion error is detected, propagation of the error is restricted, such that a correct decoded signal is provided.

Abstract: A Viterbi trellis is provided which allows for implementation of either an EPRML type channel or an E2PRML type channel using a single trellis structure. According to a specific embodiment, a trellis is provided which can support a 0 mod 2 EPRML (M2EPRML) channel and a modified E2PRML (ME2PRML) channel.

Abstract: A method and apparatus for providing a precoder filter having peak-to-average ratio (PAR) controller that also serves as a high-pass, low-pass, or band-pass filter. The described invention is includes a modulo device connected in series with the PAR controller and a precoder filter connected in a feedback arrangement. The input to the apparatus is a sequence of data symbols and the output is a spectrally shaped precoded signal having a controlled peak-to-average ratio.

Abstract: The operation of a line card in the local exchange of a point-to-point switched telephone network is modified to increase the data rate of voiceband modem transmission by increasing the sampling rate and providing controlled intersymbol interference using partial response techniques.

Abstract: Apparatus for deriving from an input information signal (IIS) amplitude values usable as reference levels for finite state machine states. The apparatus includes: conversion apparatus for deriving a digital signal from the IIS; detection apparatus for repeatedly detecting a state from sequences of n subsequent bits in the digital signal; sample value apparatus for deriving sample values from the IIS, one sample value for each sequence of n bits; processing apparatus for processing the sample values belonging to sequences of n bits of the same state, and for carrying out this processing step for all states, to obtain a processed signal value for each state; output apparatus for supplying the processed signal values for each state as the amplitude values; and apparatus to use the amplitude values for the possible states, obtained from a first portion of the IIS, for detecting bits from a second portion of the IIS.

Abstract: A digital signal processing circuit having a memory for storing a digital signal obtained from a playback channel; a controller for writing the digital signal in the memory at a first rate and reading out the digital signal from the memory at a second rate lower than the first rate; and a processor for executing a desired process relative to the digital signal thus read out from the memory. The digital signal is written in the memory at a first rate by the controller and is read out therefrom at a second rate lower than the first rate. And then a desired signal process is executed relative to the digital signal read out from the memory. Therefore the required digital processing rate becomes lower than the transmission rate of the playback channel, whereby the transmission rate can be raised despite the condition that the time required for the desired signal process such as demodulation is rendered longer.

Abstract: The PR(1, 1) equalizer 1 receives signals which are provided from a playback head which detects data in which the number of continuous non-inverse bits is at least “2”. The PR(1, 1) equalizer 1 then converts the signals into seven levels of data and ten levels of data, provides them to the four states of Viterbi decoder 2. In Viterbi decoding, an weight is applied to a metric which is obtained from the seven levels of data or the ten levels of data.

Abstract: A system and method for reading data to and writing data from multi-level (M-ary) partial response channels uses a trellis coder to encode an input bit stream sequence into a stream of multi-level data symbols. The data symbols are written to the partial response channel using any of a number of techniques. Preferably, the trellis coder anticipates the modulation transfer function of the partial response channel in encoding the data. Because the partial response channel has its own transfer function, the relationship between the data read from the channel and the actual input data bits is a function not only of the data encoder but also of the partial response channel. Therefore, a decoder specification used to implement the decoder takes into account the effect of the trellis encoder as well as the effect of the partial response channel.

Abstract: A new class of fixed partial response targets are disclosed for use in a PRML magnetic medium read channel. The preferred embodiment exhibits an equalization response characterized by the polynomial 7+4*D−4*D2−5*D3−2*D4, where D represents the unit delay operator. This read channel target provides improved matching to the inherent magnetic channel over the known canonical class of targets (1−D)(1+D){circumflex over ( )}N, and thereby reduces equalization losses. The improved spectral matching reduces amplification of noise in the channel, thereby reducing bit-error-rates. The new class of targets also exhibits a spectral null at DC, reducing problems for offset cancellation circuitry and making the disk drive less sensitive to thermal asperities. It also exhibits a spectral depression rather than a spectral null at the Nyquist frequency, making quasi-catastrophic error sequences virtually impossible.

Abstract: A synchronous interface is provided for an asynchronous channel, for example, a read channel for a variable velocity magnetic tape, the channel providing asynchronous samples of an input signal from a fixed clock. The input signal, for example, comprises PRML data, written based upon synchronous write clock boundaries. The synchronous interface of the invention presents estimated synchronous samples at estimated write clock boundaries to allow decoding of the input signal. A phase estimator is coupled to the asynchronous channel for estimating the timing offset of the input signal synchronous write clock boundaries from the asynchronous samples. A sample estimator is coupled to the asynchronous channel and to the phase estimator for estimating, from two sequential asynchronous samples bounding an input signal synchronous write clock boundary, the input signal amplitudes at the estimated timing offset from the asynchronous samples.

Abstract: Parallel processing in the form of two PR4 Viterbi Detectors connected in parallel operates to increase the maximum channel speed of a given data channel of a magnetic media. According to a target equation defined as Read(D)=(1−D2)2Written(D), in which D is the delay of a data of the channel, a first Viterbi Detector processes even data samples of the channel that have been equalized according to the target equation and a second Viterbi Detector connected in parallel processes odd data samples of the channel that have likewise been equalized according to the target equation. The use of two parallel-connected Viterbi Detectors in this fashion allows data to be processed at half-rate rather than full-rate, thereby increasing the overall channel speed.

Abstract: The present invention is a communication system for communicatinginformation over greater distances than otherwise possible on bidirectional media subject tointerference, by reducing the interference while assuring spectral compatibility with other communication services. The system of the present invention provides symmetric data service to end users by using asymmetric signaling. In one embodiment, the present invention utilizes partially overlapped, non-symmetric baud rates and spectrally shaped transceiver filters to achieve both spectral compatibility and extended range.