Abstract: A method of transmitting information in a WLAN (Wireless Local Area Network) network and corresponding WLAN communication devices and integrated circuit chips are provided. A correction signal is used for compensating for a dc offset in a data signal containing at least part of the information to be transmitted. The correction signal is varied by making it taking different values. For each of the different values, a strength of an indicator signal indicative of the dc offset is determined. Based upon the determined strength, an optimum value of the correction signal is identified at which the dc offset is minimized. The value of the correction signal is set to the optimum value. Further, a method of transmitting information in a WLAN network is provided, including compensating for a first and second dc offset in a first and second data signal, respectively, using a first and second feedback loop, respectively.

Abstract: A sigma delta converter configured for DC offset correction is presented. The sigma delta modulator has integrator circuitry including an integrator input and an integrator output. An input signal received at the integrator input has an input AC voltage component and a DC offset component. Capacitors are connected to the integrator input, and a first set of switches is connected to the pair of capacitors. The first set of switches transfer a first charge to the pair of capacitors during a first phase, and a second set of switches transfer the first charge and a second charge to the integrator input.

Abstract: According to one exemplary embodiment, a method and system for determining and removing DC offset in an AC signal includes receiving an AC signal having a first-channel and a second-channel, e.g. an I-channel and a Q-channel, receiving a plurality of first-channel and second-channel samples, storing a negative first-channel sample corresponding to a first sign change in the plurality of second-channel samples, and storing a positive first-channel sample corresponding to a second sign change in the plurality of second-channel samples. The method further includes determining an average value of the negative first-channel sample and the positive first-channel sample, where the average value is the DC offset in the first-channel. The method can further include subtracting the determined DC offset from samples received in the first-channel (or the second-channel) prior to demodulation. The method and system can be implemented in, for example, a Bluetooth receiver.

Abstract: Methods and systems for blocker and/or leakage signal rejection by DC bias cancellation are disclosed and may include undersampling a received signal including a desired signal and an undesired signal. A biasing current in the wireless system may be utilized to reduce a measured DC signal generated by the undersampling of the received signal. The received signal may be undersampled at a frequency of or an integer sub-harmonic of the undesired signal, which may include a leakage signal and/or a blocker signal. The DC biasing current may be controlled utilizing successive approximation, control logic and a digital to analog converter. The output DC voltage may correspond to said undesired signal, and the received signal may be undersampled utilizing a mixer.

Abstract: A direct conversion receiver uses an algorithm implemented by a DSP to cancel residual DC offsets during demodulation of a GMSK modulated signal. The algorithm exploits the characteristics of GMSK modulation by determining the. modulation extremes within sampled I/Q signals and calculates the DC offset as the mean of the extremes. This offset is used to weight a declining exponential function which is subtracted from the original signal samples to achieve compensation.

Abstract: The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period.

Abstract: A receiver assembly for use in an optical telecommunications network is provided that automatically generates a reference level for the incoming signal burst based on its preamble without the need to pre-process the entire signal burst. The entire signal burst is fed directly from the TIA into the input of the limiting amplifier. A differential amplifier, tapped from the data and data bar outputs of the limiting amplifier, samples the signal stream to capture the preamble portion of each signal burst. The preamble portion of the signal burst is then passed, post amplification, into a sample and hold circuit. The sample and hold circuit samples the amplitude of this preamble portion of the signal and then holds the sampled level for use as a reference level for the processing of following payload signal.

Abstract: A scheme for deducing a DC offset in a received signal burst acquired through a particular channel, wherein the received signal burst corresponds to a transmitted signal burst. An impulse response estimate of the channel is used to model how a known or recovered part of the transmitted burst would have been affected by passage through said channel in place of the corresponding part of the transmitted signal burst. The modeled part of the transmitted burst is then compared with the corresponding part of the received signal burst to deduce a DC offset present in the received signal burst.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A method and apparatus are provided to generate calibration signals to multiple stages in a receiver channel. The multiple stages are calibrated using multiple calibration circuits, where a controller controls each calibration circuit. The controller is coupled to the output of the final stage in the receiver channel through a single comparison unit. The output from the single comparison unit is used by the controller to calibrate each of the multiple stages.

Abstract: A transceiver suitable for larger scale of integration employs direct conversion reception for reducing the number of filters. Also, the number of VCOs is reduced by utilizing dividers to supply a receiver and a transmitter with locally oscillated signals at an RF band. Dividers each having a fixed division ratio are used for generating locally oscillated signals for the receiver, while a divider having a switchable division ratio are used for generating the locally oscillated signal for the transmitter. In addition, a variable gain amplifier for baseband signal is provided with a DC offset voltage detector and a DC offset canceling circuit for supporting high speed data communications to accomplish fast cancellation of a DC offset by eliminating intervention of a filter within a feedback loop for offset cancellation.

Abstract: A receiver includes a memory for storing DC offset amounts in accordance with a DC offset component remaining in a received signal; a first DC offset component-removing unit configured so as to generate a first DC offset amount from the DC offset amounts stored in the memory and to remove the first DC offset amount from the received signal; an amplifier for amplifying a signal output from the first DC offset component-removing unit; and a second DC offset component-removing unit configured so as to generate a second DC offset amount from the DC offset amounts stored in the memory in view of a gain of the amplifier and remove the second DC offset amount from the signal amplified by the amplifier.

Abstract: In a lattice-reduction-aided receiver based wireless communications system, outputs are determined on the basis of a received signal, the received signal being modulated onto a plurality of sub-carriers.

Abstract: A division ratio of a first frequency divider that generates a local signal and a division ratio of a second frequency divider that generates a RF interfering signal are different, and a first frequency synthesizer that generates the local signal and a second frequency synthesizer that generates the RF interfering signal employ an identical reference signal. The second frequency synthesizer that generates the RF interfering signal is not provided with a frequency switching function.

Abstract: A radio frequency receiver (102) includes at least one amplifier (108, 114 and 122) for amplifying a signal received by the radio frequency receiver, an automatic gain control system (158) for controlling a gain of the at least one amplifier, and a direct current offset correction filter (142) for reducing any direct current component of the signal amplified by the at least one amplifier. The direct current offset correction filter has a bandwidth that is dynamically controlled by a change in the gain of the at least one amplifier. The radio frequency receiver also includes a digital automatic gain control unit (150) having a bandwidth that is dynamically controlled by the change in the gain of the at least one amplifier.

Abstract: The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission system. Several classes of example embodiments, utilizing digitally controllable voltage or current sources, are presented. The classes differ based upon such factors as coupling capacitor arrangement and use of termination resistors. Specific embodiments, within each class, differ based upon such factors as whether voltage or current sources are used and the characteristics of such sources. Once the DC offset of a differential signal has been changed, the effect of such change on a performance metric can be measured. Example applications include the ability to determine a differential signal level that results in BER having a particular level and determination of differential signal margin.

Abstract: A receiver unit includes a prefilter that receives as one of the inputs a channel impulse response (CIR) estimation data set and removes unnecessary data information from the CIR estimation data set and filters input signal so to form a first output data set. An equalizer core receives the first output data set and based on computed CIR length and SNR value of the first output data set so as to determine which portion of the first output data set are assigned to at least one of at least two low complexity equalization modules used for processing.

Abstract: Certain aspects of a method and system for independent in-phase (I) and quadrature (Q) loop amplitude control for quadrature generators may include determining an amplitude voltage associated with an in-phase (I) component and a quadrature (Q) component of a generated signal. A DC reference voltage associated with the I component and the Q component may be determined. The determined amplitude voltage may be compared with the determined reference voltage to generate a control signal. The amplitude mismatch between the I component and the Q component may be compensated by controlling a biasing current of one or more programmable buffers associated with one or both of the I component and the Q component, based on the generated control signal.

Abstract: Aspects of a method and system for multimode DC offset compensation are presented. Aspects of the system may include accumulating a selected number of signal samples, determining an average of the accumulated signal samples, and keeping a running total of the average for use feedback signal generation. The signal samples may be, for example, samples of WCDMA signals. By keeping track of the signal offset error, the signal offset error, or residual DC, may be determined. For example the signal offset error may comprise a DC component and/or a sinusoidal component. The number of signal samples to accumulate for the average may be based on the signal offset error. For example, a threshold may be determined as part of design of an embodiment of the invention.

Abstract: A feedback signal generated as a function of a peak amplitude detected in an input signal provides bias to reduce DC offset. A peak in the input signal is compared with a selected signal level to align an output signal relative to a reference signal level. The output signal is generated by comparing the reference signal level and the biased input signal. Single ended signals are compared with a reference level and differential input signals are compared with each other to reduce jitter.

Abstract: A second intercept point (IP2) calibrator and a method for calibrating IP2 are disclosed. The IP2 calibrator and the method for calibrating IP2 remove any direct current (DC) offset by comparing a common-mode reference voltage with the common-mode voltage measured between a first output terminal and a second output terminal of a mixer, and calibrates the IP2 of the mixer by comparing the common-mode voltage with a calibration reference voltage. The calibration reference voltage is independent of the common-mode reference voltage and may be a quantized variable voltage generated according to digital control code.

Abstract: A data receiving device, for receiving digital data via a differential signal transmission path made up of two or more channels including one channel of a reference clock, includes a digital data receiver configured to receive various data channel signals transmitted from the transmitter side to the differential signal transmission path, a reference clock receiver configured to receive a reference clock transmitted from the transmitter side to the differential signal transmission path, and a transmission loss rate determining unit configured to determine between degree of magnitudes of transmission loss with the reference clock, based on waveform deterioration resulting from the reference clock receiving at the reference clock receiving unit having passed through the differential signal transmission path.

Abstract: A slicer circuit is disclosed. The slicer circuit has the feature that a counting-circuit is employed to count the number of continuous times of signals in a same level continuous outputted from the comparator thereof, and when the number of continuous times reaches a preset value, a control signal is output to make a resistance circuit consisting of dynamic devices open, so as to largely delay the up-shift or down-shift speed of an input DC reference level and enable the slicer circuit to continue to judge the input signal correctly according to the input DC reference level.

Abstract: An apparatus for removing a DC offset during frequency direct conversion in a reception device of a wireless communication system. In the apparatus, an adder receives a digital baseband signal comprising a DC component, receives an estimated DC offset value, and calculates a difference between the digital baseband signal with the DC component and the estimated DC offset value. A DC offset calculator receives gain mode information of an analog element of the reception device, and calculates the estimated DC offset value according to the gain mode.

Abstract: In RF transceivers, a method and system for using phase shift key (PSK) sync word for fine tuning frequency adjustment are provided. One aspect of the invention provides for adjusting a local oscillator frequency in a radio frequency (RF) receiver when a residual DC offset remains after a coarse frequency offset adjustment if performed. The fine adjustment may be necessary because of the synchronization required with a PSK-based modulated portion of a Bluetooth packet. A residual phase shift detected in a sync sequence portion of the Bluetooth packet may be utilized to determine a residual or fine frequency adjustment. This approach may allow an RF receiver to operate, in some instances, without the need for an equalizer. In this regard, the power consumed by the RF receiver may be minimized and/or the overall cost of the RF receiver may be reduced.

Abstract: An Ultra Wide Band (UWB) transmitting and receiving device that includes a Digital Signal Processor (DSP) for implementing a DC offset cancellation algorithm, an adder for adding a baseband transmission signal from the transmitter and a calibration signal produced by the algorithm of the DSP, a modulator for modulating the signal from the adder, a transmitter amplifier for amplifying the modulated signal, a coupler for applying the output of the transmitter to the receiver, and a switch for selectively connecting the output of the coupler to the input of the receiver.

Abstract: A method to perform DC compensation on a Radio Frequency (RF) burst transmitted between a servicing base station and a wireless terminal in a cellular wireless communication system that first receives the RF burst modulated according to either a first or second modulation format. Samples from the RF burst, or taken from the training sequence, are produced and averaged to produce a DC offset estimate. The DC offset estimate is then subtracted from each of the samples. The modulation format of RF burst may then be identified from the samples. Depending on the identified modulation format, the DC offset estimate may be re-added to the samples when a particular modulation format is identified as the modulation format of the RF burst. This decision is made based on how well various components within the wireless terminal perform DC offset compensation.

Abstract: A digital baseband (DBB) radio frequency (RF) receiver used for receiving and processing a wireless communication signal. The DBB RF receiver includes a demodulator, an analog to digital converter (ADC) and a digital cross-talk compensation module. The demodulator outputs analog real and imaginary signal components on real and imaginary signal paths, respectively, in response to receiving the communication signal. The ADC receives the analog real and imaginary signal components and outputs respective digital real and imaginary signal components. The digital cross-talk compensation module receives the digital real and imaginary signal components, estimates the cross-talk interference caused by each of the signal components, and outputs digital real and imaginary cross-talk compensated signal components.

Abstract: An OFDM receiver has a DC offset estimator configured for determining a DC offset, in I and Q components of a received OFDM signal having been output by an analog front end, based on filtering prescribed subcarrier components from a preamble segment of the I and Q components. The OFDM receiver removes the determined DC offset from the I and Q components, resulting in respective corrected I and Q components having minimal DC offset.

Abstract: A multi-carrier receiver capable of receiving one or multiple frequency channels simultaneously is described. In one design, the multi-carrier receiver includes a single radio frequency (RF) receive chain, an analog-to-digital converter (ADC), and at least one processor. The RF receive chain processes a received RF signal and provides an analog baseband signal comprising multiple signals on multiple frequency channels. The ADC digitizes the analog baseband signal. The processor(s) digitally processes the samples from the ADC to obtain an input sample stream. This digital processing may include digital filtering, DC offset cancellation, I/Q mismatch compensation, coarse scaling, etc. The processor(s) digitally downconverts the input sample stream for each frequency channel to obtain a downconverted sample stream for that frequency channel. The processor(s) then digitally processes each downconverted sample stream to obtain a corresponding output sample stream.

Abstract: An apparatus for coarse compensation of a direct current (DC) offset in a direct to baseband receiver architecture utilizes a serial analog to digital converter (ADC), such as a Delta-Sigma converter, to convert the received signal to digital form. The output of the ADC is sampled for a predetermined number of samples and a counter coupled to the ADC is incremented each time the sample generated by the ADC is a logic one. The counter is not incremented if the sample from the ADC is a logic zero. After the predetermined number of samples is obtained, the counter value is indicative of the DC offset in the received signal. The counter value may be converted by a code converter to a correction value for easy operation of a digital to analog converter (DAC). If the number of samples from the ADC is a power of two, the code converted may be readily implemented by simply inverting the most significant bit (MSB) from the counter to thereby generate a twos complement version of the counter value.

Abstract: An analog front end device with temperature compensation is provided. The analog front end device comprises a bandgap voltage reference circuit, a clock generator, a temperature compensation circuit, one to three identical converting circuits and a Sync-on-Green circuit. The temperature compensation circuit is adapted to sense the temperature variations of the analog front end device and dynamically compensate the bandgap voltage reference circuit, the clock generator and the Sync-on-Green circuit as the temperature varies, which thereby controls the thermal drift in the analog front end device.

Abstract: A method of simultaneously determining a DC offset and a channel impulse response from a received signal in a mobile communication system. The received signal comprising a set of training sequence bits that have been modulated prior to transmission. The modulated signals experience a certain phase shift and are rotated by a certain angle. The received signal may also comprise a DC offset component that needs to be removed By manipulation of the received signal samples with the knowledge of the original training sequence and method of modulation used, it is possible to simultaneously estimate the communication channel's impulse response and the DC offset by finding the Least Squares solution to a linear equation, such that the energy of the noise term introduced into the communication channel may be kept to a minimum. An improved technique utilising a priori information is also described.

Abstract: A DC offset removal apparatus and a DC offset removal method that can highly accurately detect and remove a DC offset within a burst and that have a relatively small processing load. DC offset compensating processing section 101 includes maximum value searching section 104 that calculates maximum value estimation value MAX of received signals; minimum value searching section 105 that calculates minimum value estimation value MIN of the received signals; average value calculating section 106 that calculates average value AVE of the received signals; DC offset detecting section 107 that calculates a DC offset value based on the calculated maximum value estimation value MAX, minimum value estimation value MIN and average value AVE; and DC offset removal section 108 that removes the calculated DC offset value from the received signal. When |AVE?(MAX+MIN)/2|?K, AVE+{(MAX+MIN)/2?AVE}×W is used as the DC offset value, and, when |AVE?(MAX+MIN)/2|<K, AVE is used as the DC offset value.

Abstract: A method of performing DC estimation and correction in the presence of an automatic gain control function introduces no long-term delay of the signal. When the automatic gain control function indicates that it has altered the gain or when an initial DC estimate is required after switch-on, a new DC estimate is begun. Input samples received at the signal-sampling rate are stored in a first-in first-out buffer, while waiting for sufficient samples to have been received to perform the DC estimate. Once sufficient samples have been received to calculate a DC estimate, the data that has been stored in the FIFO is read out and processed by subsequent signal processing functions at a higher rate than the data-sampling rate. Due to the higher rate of read-out, the FIFO is rapidly emptied so that the subsequent signal processing functions “catch up” with the input data stream leading to no long-term latency.

Abstract: A method for estimating an SNR-related parameter, such as ES/N0, from one or more symbols. The number of symbols within a predetermined number of symbols that fall within one or more collection areas is counted. The count is then associated with a value of the SNR-related parameter. This association may be performed through one or more lookup tables. In one application, a scaling factor is derived from the count. The scaling factor may be used to scale symbols before they are quantized and inputted into a trellis decoder such as a log-MAP decoder.

Abstract: An apparatus, method, and system for providing dc offset reduction in a communications channel include two or more feedback loops to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.

Abstract: In a method to compensate for a step DC disturbance (1) in a baseband signal in a homodyne radio receiver, the time profile of the step DC disturbance within a burst is determined. In order to produce a step-corrected baseband signal, the determined time profile (2) is then calculated from the digitized baseband signal.

Abstract: A wireless receiver includes a local oscillator, a mixer, a band pass filter, a DC offset determination module, a DC offset correction module, a subtraction module, and a down converter. The local oscillator produces a local oscillation that a mixer uses to down convert the RF information signal to produce a Very Low Intermediate Frequency (VLIF) information signal at a VLIF and having a DC offset. The band pass filter band pass filters the VLIF information signal. The DC offset determination module produces a DC offset indication for the VLIF information signal. The DC offset correction module generates a DC offset correction based upon the DC offset indication. The subtraction module subtracts the DC offset correction from the VLIF information signal to substantially remove a DC offset of the post-filtered VLIF information signal. The down converter down converts the VLIF information signal to a baseband information signal.

Abstract: A method for processing an input burst signal comprising a first step for identifying an additive DC component and generating an output signal, which is representative for an estimated value of said DC component. The method further comprises a second step for detecting a predetermined signal portion from a plurality of possible signal portions included in the input burst signal and generating a control signal indicating the presence of the predetermined signal portion in the input burst signal. The method is characterized in that the first step and the second step are performed in parallel i.e. in a commonly defined time interval from a starting time of the burst.

Abstract: Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.

Abstract: An apparatus, method, and system for providing dc offset reduction in a communications channel include a feedback loop to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.

Abstract: A base band circuit of a receiver and a low cut-off frequency control means can quickly converge transition state due to gain fluctuation with setting a low cut-off frequency of a high-pass filter as low as possible. The base band circuit of a receiver has a variable amplifier variably amplifying a base band signal depending upon a gain control signal, a high-pass filter provided in a path of the base band signal, and a controller detecting variation magnitude of the gain control signal and controlling variation of a low cut-off frequency of the high-pass filter means depending upon the detected variation magnitude.

Abstract: A receiver for eliminating D.C. noise from a signal received from a communication channel includes an input circuit configured to receive an input signal. The receiver includes an error circuit configured to generate an error signal in accordance with the input signal from the input circuit. The receiver includes a first noise canceler responsive to the error circuit. The first noise canceler is configured to generate a first noise cancellation signal in response to the error signal from the error circuit. The receiver includes a second noise canceler responsive to the error circuit and the first noise canceler. The second noise canceler is configured to generate a second noise cancellation signal from the error signal from the error circuit and the first noise cancellation signal from the first noise canceler. The input circuit is responsive to the second noise cancellation signal from the second noise canceler.

Abstract: A radio frequency receiver includes an amplifier and a detector that produces a bias control signal based on a signal environment. A bias level of the amplifier is set according to the bias control signal. Bias levels other receiver circuits may have similarly adjusted bias levels, including buffers, IF oscillators, mixers, and converters. The invention can be used to increase range of linearity, intermodulation immunity and reduce power consumption by reducing the bias level under typical conditions and relying on the bias control to increase bias levels under adverse signal conditions. The invention has advantages where power is at a premium, particularly when a device is in standby mode, including mobile, portable and hand held pagers and wireless telephones and Internet connections. If standby mode operation in non-maximum signal environments dominates the usage of the receiver, then the invention can substantially increase battery life.

Abstract: A DC-offset correction circuit (I1, Q1) for a low-IF or zero-IF receiver, comprises a DC-offset control loop (O1, O2) embodied by: a summing device (9-1, 9-2) having a signal path input (10-1, 10-2), a DC control input (11-1, 11-2), and a summing output (12-1, 12-2); and an offset determining means (15-1, 15-2) coupled between the summing output (12-1, 12-2) and the DC control input of the summing device (9-1, 9-2). The DC-offset correction circuit (I1, Q1) further comprises a DC blocking circuit (17-1, 17-2) coupled to the summing output (12-1, 12-2) of the summing device (9-1, 9-2) and having a DC blocking output (18-1, 18-2) for providing an offset corrected output signal. The DC-offset control loop (O1, O2) and the DC blocking circuit (17-1, 17-2) advantageously interact in correcting DC offset.

Abstract: An amplification system for reducing DC offset in an input signal uses a low pass filter to isolate a DC component of the input signal. The system then subtracts the DC component from the input signal. In one embodiment, the system includes first and second amplifiers in addition to the low pass filter. The first amplifier amplifies the input signal to generate a first amplified signal at a differential output port of the amplification system. The second amplifier amplifies a low pass filtered version of the input signal to generate a second amplified signal at the differential output port of the amplification system. The outputs of the first and second amplifiers are connected to the differential output port of the amplification system in such a way that the first and second signals combine 180 degrees out of phase at the output port.

Abstract: A read channel component of a magnetic recording system employs equalization of a signal received from the magnetic recording channel, the equalization being modified depending upon the presence or absence of DC shifts in the signal. Equalization corrects for DC shifts, if present, prior to detection and decoding of servo data, such as servo address mark (SAM) and Gray code data. In a first implementation, a DC shift detector detects the presence or absence of DC shifts and modifies equalization in a predetermined manner. In a second implementation, filtering is applied to the signal to enhance equalization in the presence of DC shift, and both filtered and unfiltered signals employed for detection of the servo data.

Abstract: A system and method for compensating for DC offset and/or clock drift on a wireless-enabled device is described. One embodiment includes a radio module, an A/D converter connected to the radio module, a DC tracking loop connected to the A/D converter, and a multi-hypothesis bit synchronizer.

Abstract: A method and apparatus for avoiding and or recovering from the latch-up condition in a quantized feedback DC restorer circuit for use in a digital data communication system receiver. An automatic gain control (AGC) circuit controls the level of the received data by comparing the AGC output with a quantized output signal from the DC restorer. A carrier detect circuit detects the presence of data transitions in the quantized output signal, and in the absence of such transitions continuously ramps up the gain of the AGC until such transitions are detected. The carrier detect circuit can be further used to disable, either entirely or partially, the positive feedback path of the DC restorer in the absence of transition in the quantized output signal. The present invention further provides an inherent muting function of the DC restorer output signal in the absence of valid data transitions.