Abstract: A direct conversion receiver comprising mixers for mixing a received radio frequency signal and a local oscillation signal in frequency, a signal processing unit for converting the output signal of the mixers into a baseband signal, a delta-sigma modulator for detecting offset voltage from the output signal of the signal processing unit, a holding circuit for supplying offset canceling voltage for canceling the offset voltage, and a switch of supplying the output signal of the mixers to the delta-sigma modulator during a given period and supplying the offset canceling voltage sent from the holding circuit to the output side of the mixers.

Abstract: A closed feedback loop controls the baseline correction of a data signal. Detected signal information about the baseline and positive and negative peaks of the incoming data signal is processed to generate a baseline correction signal which identifies the difference, if any, between the present data signal baseline and that which is desired. This baseline correction signal is summed with the original data signal to bring its baseline into conformance with the desired baseline.

Abstract: In a method for deciding the level of an input signal, positive and negative signals are provided in response to the input signal. A peak of the positive signal is detected to provide a positive-peak value. A peak of the negative signal is detected to provide a negative-peak value. The positive signal and the negative-peak value are combined to provide a first combination signal. The negative signal and the positive-peak value are combined to provide a second combination signal. The first and second combination signals are compared to provide an output signal of zero or one.

Abstract: This device includes a main signal path in which a capacitor is included upstream of an analog/digital converter in which a conversion is triggered by a clock. According to the invention, the output of the analog/digital converter is connected to inputs of several threshold detectors which have positive detection thresholds in a progression proportional to consecutive powers of two, and several other threshold detectors which have negative detection thresholds which also progress proportionally to consecutive powers of two, which threshold detectors control current generators whose currents are added together into the capacitor.

Abstract: In a method for compensating D.C. offset in a direct conversion receiver by a signal (IF.sub.-- I, IF.sub.-- Q) received and demodulated in one of the channels of the reception frequency band of a radio communication system, a correction signal (Q.sub.control) is produced from the signals in the channels of the reception frequency band. The correction signal (Q.sub.control) is combined with the demodulated signal. The apparatus for implementing the method comprises means (12, 17, 18, 19) for producing the correction signal, and means (15, 16) for combining the correction signal with the received and demodulated signal.

Abstract: A DC coupled burst mode optical receiver circuit having improved sensitivity and improved dynamic range. The output of the receiver's photodiode is single endedly amplified by a main preamplifier and the main preamplifier's output is then converted, using an operational amplifier, e.g., with a gain of 1, to a differential signal which swings symmetrically around a threshold level. More specifically, the output of the main preamplifier is connected to one input of the operational amplifier. The output of a tracking preamplifier, which is identical to the main preamplifier, is coupled to the other input of the operational amplifier. The output of the tracking preamplifier is used to match the DC voltage of the main preamplifier, e.g., by being noise-free and by tracking changes in supply voltage, temperature, and the like. It is used to set the DC reference voltage for the standard operational amplifier functions.

Abstract: An error correction circuit compensates for baseline wander which can occur when a data signal is passed through a DC isolation stage. The data signal, and its inverse are compared with a common reference level, and the error signal modifies the charge on a capacitor which forms part of a pair of negative feedback loop to control the baseline level.

Abstract: The invention is a receiver front end for a data communications system having adaptive correction for intersymbol interference, DC offset, baseline wander, and flat loss and related method. Each of the compensation circuits is adaptive and is controlled by adaptation logic via a digital feedback loop including a digital integrator for providing perfect or near-perfect integration of the adaptation algorithm feedback error signal. The architecture further utilizes multiple comparators, including continuous-time and clocked comparators, for separately detecting various aspects of the received data signals that are used to determine the signal degradation characteristics needed to generate error signals for the adaptation feedback loops.

Abstract: An autozero method and system that cancels offset for use in an AMI or like system and that operates while data is being transmitted and does not require a retraining sequence. The system applies the offset correction feedback in a unique way inside the traditional feedback loop. The system also provides a unique method of introducing offset correction into an analog feedback loop prior to the last gain stage such that the offset cancellation point is inside the feedback loop. This allows a straight forward implementation which does not have to compensate for the offset change due to the gain of the last stage. A digital control system allows the AGC and the autozero to be active in the same feedback loop and to interact with no adverse affects during the transmission of data.

Abstract: Known is a zero intermediate frequency receiver or zero-IF receiver in which DC-offset correction is done in the I- and Q-paths, after mixing down of the received RF-signal or of an IF-signal. Such a DC-offset correction is not sufficient for high gain I- and Q-paths, particularly not in pagers for receiving long messages. Furthermore, no optimal power saving is achieved if such a receiver alternately operates in receive mode and sleep mode. A zero intermediate frequency receiver is proposed in which DC-offset correction is distributed over the high gain I- and Q-path. Preferably, blocking means are provided between DC-offset correction circuits and low pass filters in the I- and Q-path to prevent that an output signal of an upstream DC-offset correction circuit in the path excites a downstream low pass filter in the path during DC-offset correction. Herewith, considerable power savings are achieved.

Abstract: A circuit for determining and evaluating a data signal with a disturbing direct voltage portion has a signal processor with which the direct voltage portion is determined and then subtracted from the signal. A non-linear control is provided that changes a time constant of the circuit in dependence on the signal curve.

Abstract: A receiver circuit, particularly an integrated, zero IF receiver circuit in which a direct conversion IF stage is separated from an antenna by a further fequency conversion stage which is AC coupled to the direct conversion IF stage. A single crystal oscillator generates a frequency which is multiplied prior to being applied as a local oscillator signal to the further frequency conversion stage and is used to produce another frequency, which is divided to block harmonics, prior to being applied as quadrature related local oscillator signals to the direct conversion IF stage. The direct coversion IF stage includes several dc nulling for compensating for dc offsets.

Abstract: There is disclosed in a frequency hopping digital communications system having a transmitter for transmitting a data signal via a noisy transmission path, and a receiver responsive to the transmitted signal for receiving the same, a method for removing bias in the data signal at the receiver comprising the steps of: forming a sample amplitude histogram from the received data signal samples for a given hop frequency; correlating the amplitude histogram against a stored reference amplitude histogram to obtain a correlated output signal having a peak correlation position; determining the position difference between the peak correlation position and the correlation center position to provide an offset signal corresponding to the difference and indicative of an estimated bias offset value; and applying the estimated bias offset value to the received signal samples in response to the offset signal to obtain an output signal indicative of an unbiased received data signal.

Abstract: There is provided a detection process for a digital radio which receives a multistate baseband signal comprising removing the low frequency information content of the baseband signal and subsequently restoring the low frequency information content to provide a conditioned baseband signal for detection so as to provide automatic frequency control for the radio on a manner avoiding loss of the low frequency information content of the baseband signal.

Abstract: A DC restoration circuit to correct for baseline wandering in a data receiver is provided. A voltage correction circuit is connected to the received data line to adjust the voltage level of the received data dynamically. The voltage correction circuit is controlled by a feedback circuit which includes a voltage detection circuit configured to detect the peak voltage levels or envelope of the received data. This detected level is then compared to a reference level, and the result of the comparison is used as a control signal for the voltage correction circuit.

Abstract: Methods and apparatus for detecting, estimating, and compensating for unwanted d.c. offsets in sampled signals in a direct conversion receiver are described. These methods and devices can be used for varying d.c. offsets, ramps, and steps to realize a direct-conversion receiver for modem cellular communication systems that does not suffer performance degradation due to strong interferers.

Abstract: A new data communication system is described which enables data transmission over existing telephone lines at rates higher than possible with existing methods, including conventional modems. By using a novel asymmetric configuration of the two communication endpoints, the currently-accepted maximum theoretical limits on the data rate are no longer applicable. One endpoint is connected directly to a digital telephone network, whereas the other endpoint uses a conventional telephone connection. This reduces the transmission problem to compensation for a single telephone line interface and a single analog local loop. Means of providing this compensation and the required clock synchronization were also created, enabling a practical implementation of the system. The new system can achieve rates up to 64,000 bits-per-second and has broad utility in several active areas including wide-band audio transmission, video transmission, networking, facsimile transmission, and remote computer access.

Abstract: A data received is provided with DC restoration circuitry for correcting the DC level of received multi-level data signals. A DC shift detection circuit detects whether the received DC level multi-level signals has shifted due to a predominance of one of the data levels in the data stream. A correction circuit responds to the shift detection circuit by applying a corrective bias to an isolation transformer. Alternatively, the correction circuit applies a corrective bias to the received signals within the receiver circuit.

Abstract: The present invention relates to a circuit for restoring bits transmitted by an asynchronous signal, including a comparator of the signal level with a reference level; a sampling circuit supplying several samples of the comparator output for each time interval corresponding to a bit; a circuit for determining a succession of windows, each of which corresponds to a bit; an acquisition circuit receiving the samples and supplying, for each window, the number of samples having a first logic value, the number of sample transitions, and the value of a border sample of an adjacent window; and an estimation circuit for correcting the reference level and the alignment of the windows on the bits according to the outputs of the acquisition circuit.

Abstract: A signalling system adapted for digital signals includes a signal transmitter, a signal receiver and a connection which connects the transmitter to the receiver. The transmitter includes an output buffer which has at least one transistor connected to the lowest level of a signal supply voltage, such as to "0" potential or earth potential. Driving or steering of the transistor in response to a received control signal causes the transistor to switch from a state of high impedance to a state of low impedance which exhibits resistive or at least predominantly resistive properties, such as to form an information-carrying output signal. A first of two series-connected transistors is connected to the lowest level of the signal supply voltage, for instance "0" or earth potential, and the other transistor is connected to the signal supply voltage. A connection conductor on which the information-carrying signal is transmitted is connected between the transistors.

Abstract: A received and demodulated multi-level signal (32) is corrected for D.C. offset by a feedback loop (34) which applies a correction signal (38) to the multi-level signal (32). Initial coarse correction is provided by feeding the corrected signal (42) into the feedback loop where a low pass filter (36) averages the corrected signal over time and detects departure from zero of this time-averaged signal. After initial coarse correction, finer correction of D.C. offset is provided in a data-aided mode in which detected data values (46) are fed into the feedback loop (34). The method achieves D.C. offset correction without the need to know anything about the data pattern of the received signal (32).

Abstract: DC offset cancellation and timing recovery is provided in a homodyne receiver. The homodyne receiver demodulates an RF signal to produce a baseband signal. An initial offset correction module determines an initial DC offset of the baseband signal. An initial offset correction is applied to the baseband signal to provide an initial corrected baseband signal. Wherein, a dynamic DC offset correction module determines a dynamic DC offset. A dynamic DC offset correction is applied to the initial corrected baseband signal providing a dynamic corrected baseband signal. A timing signal is acquired from the baseband signal for synchronizing the receiver to a transmitter. A method for correcting DC offset of a baseband signal in a homodyne receiver is also described.

Abstract: The present invention relates to a radio receiver adapted for use in a time division multiple access (TDMA) system. The radio receiver includes DC compensator circuits configured to decrease the time required to cancel DC offset before received data bursts by DC coupling a radio frequency (RF) demodulator to a baseband channel. The radio receiver may also employ AC capacitive coupling having time modification so as to increase the AC coupled setting time and provide a low pole in a RF-to-Baseband interface.

Abstract: The levels of received time-division multiple access (TDMA) signals may vary widely from section to section. In DC-coupled amplifier circuits, the received signals are distorted by offset voltages. Conventional correcting or balancing methods use control mechanisms which do not allow for level variations or offset drift and tend to result in miscompensation of individual signal sections. Other methods depend on time intervals defined in the received signal and having a known average value. It is the object of the invention to provide a correcting method and a circuit arrangement for carrying out the same which achieve a self-adjusting, not widely varying (floating) correction value, thus avoiding miscompensation. This is accomplished by selecting the individual time slots in a comparator with the aid of limit value.

Abstract: A digital receiver includes a tuner and a demodulator that obtains a modulated signal carried in a received analog signal. A digital-to-analog converter operates at a preselected fixed sampling rate on the modulated signal to produce a first sequence of digitized samples. The first sequence of digitized samples is processed by a digital rotator to frequency-and phase-correct the first sequence of digitized samples. A controllable digital filter processes the first sequence to produce a filter output including a second sequence of digitized samples at a symbol rate. The second sequence is processed to ascertain a symbol rate of the modulated signal. The controllable filter coefficients are automatically varied to accommodate changes in the symbol rate of the modulated signal, so that the sampling rate of the digital-to-analog converter need not change.

Abstract: A portion of a FSK signal is encoded with a central frequency (f.sub.0) and the FSK signal is transmitted. A receiver captures the transmitted FSK signal, and demodulates the FSK signal to provide and analog data signal. The analog data signal is DC coupled to a first input of a comparator. The comparator generates a logic level binary output corresponding to the FSK signal. A second input of the comparator is coupled to a bias circuit. Preferably the bias circuit is provided by a digital to analog convertor (DAC). A control circuit detects the predetermined portion of the FSK signal in which the center of frequency is being transmitted. During the predetermined portion the control circuit samples the binary logic level output of the comparator, converts the binary logic level output to a digital error word, and uses the digital error word to control the DAC.

Abstract: Bus coupler operates with a transformer and a comparator which is connected downstream in the signal-processing branch. The comparator threshold is raised as a function of the signal in the case of larger signals relative to small signals.

Abstract: An automatic offset control circuit comprises a differential output preamplifier having an offset adjustment function, further comprising an average detector, a peak detector, and a differential input amplifier. The average detector generates a reference voltage representing an average value of a positive output and a negative output of the preamplifier. The peak detector outputs a peak voltage representing a peak of the negative output of the preamplifier. The differential input amplifier compares the peak voltage with the reference voltage to output an offset adjustment signal to the preamplifier. The offset adjustment signal is obtained based on a difference between the reference voltage and the peak voltage. A bottom detector may be used instead of the peak detector, provided a bottom value is detected using the positive output of the preamplifier.

Abstract: A low signal detection circuit for use in an electronic tolling system which wakes up a receiver circuit associated with the tolling system based upon the type of signal received. An RF signal transmitted by the electronic tolling system is Manchester encoded and will therefore have a frequency within predetermined values. The system will detect the incoming RF signals or count the rising and falling edges of the baseband signal and apply the counts to a threshold circuit which will compare the number of counts to a predetermined value. If the number of counts falls within a predetermined range, then a signal indicating the presence of a valid RF signal will be output from the wake-up circuit. A power management circuit receives a clock signal from an oscillator circuit and provides a power signal which will wake up the detection circuitry for only a minimum predetermined period of time.