Abstract: A data synchronizer is provided for synchronizing data across two different clock domains in a manner that avoids additive jitter. The data synchronizer includes a synchronizer inputting a sampling clock and a data clock, and outputting an edge pulse. A synchronizer jitter lockout circuit inputs the edge pulse and the sampling clock and outputs a data sampling enable signal which never coincides with a data transition.

Abstract: An access terminal (102) reacquires a system frame number (SFN) when a difference between a continuous counter elapsed time (220) and a calculated elapsed time (222) exceeds a threshold. The continuous counter elapsed time (220) is generated by a continuous counter (122) remaining active during a sleep state of the access terminal (102) and the calculated elapsed time (222) is based on a SFN derived from a counter value generated by a discontinuous counter (124) that is deactivated during the sleep state. In one aspect, the continuous counter (122) may be clocked by a continuous clock (118) during a sleep mode and the discontinuous counter (124) may be clocked by a faster clock (120) that is deactivated during the sleep mode. During reactivation after the sleep mode, the discontinuous counter (120) is set, at the counter set time, to a reset counter value (126) corresponding to an SFN indicated by the continuous counter (122).

Abstract: A packet stream multiplexer may include one or more control loops (e.g., digital phase locked loops) for tracking the source clock frequency associated with a packet stream. A first control loop may slowly drive an error between a received timestamp and an estimated timestamp to zero. A second control loop may more quickly drive a first derivative of the error to zero. The second control loop may include a set of digital filters ordered according to tracking speed. The output of the slowest filter is initially selected for updating the source clock frequency estimate. As time progresses, the faster filters are selected in succession. The estimated source clock frequency is used to restamp packets of the packet stream as they are sent out onto an output channel.

Abstract: Systems and methods of retraining a receiver provide for determining a minimum transition density for a derived clock data link to the receiver. A retraining flit is generated based on the minimum transition density. In one approach, the retraining flit is generated by defining control data and payload data for the retraining flit. Error detection data is determined for the retraining flit based on the control and the payload data. The control data, the payload data and the error detection data have sufficient transitions to meet the minimum transition density.

Abstract: Half duplex, Frequency Hopped-Spread Spectrum wireless transceivers (102), operating without a central controller, maintain time synchronization with the frequency hopping sequence for a period after transmission of a half duplex signal ceases. The wireless transceiver (102) operates their receivers (308) according to the RF frequency hopping sequence and schedule (200). The wireless transceiver (102) is then able to send a short transmission request to signal that it will start transmitting on the Frequency Hopping schedule (200) of the previously ceased transmission. A wireless transceiver (102) that was either the original transmitter or the original receiver is able to transmit this transmission request. A subset of time slots within the hopping schedule (200) can be optionally assigned to the original transmitter and original receiver to obviate collisions of the transmit request transmissions from both device at the same time.

Abstract: A radio transmission system including many radio transmitters using frequency hopping carriers to intermittently transmit very short messages indicative of status of stimuli associated with the transmitters. The transmitters transmit transmissions independently of a receiver receiving the transmissions and independent of each other. In operation, radio transmitters transmit messages at varying frequencies at time intervals that can be varied as well. The frequency and time intervals are varied according to patterns that can be determined individually for each transmitter. A receiver holds data indicative of the future transmission frequency and time for each transmitter and updates the data based on the time and the content of the received messages. In addition, a simple method is provided to generate a very large number of orthogonal frequency-time hopping sequences that are individual for each transmitter and based on the transmitter ID.

Abstract: The method of this invention for preparing a profile in W-CDMA which, using a timer value and norm value, helps a mobile unit to synchronize its signals with those of a base station, comprising providing a profile data preparing portion which cumulatively adds a new norm value to a previous cumulative value fetched from a profile memory to cause the result to be stored as a current cumulative value in a profile memory and repeat the same cumulative addition each time a new norm value is fed to said portion; furnishing the profile data preparing portion with an overflow detection ability to detect the overflow of the profile memory; and choosing, when the overflow of the profile memory is detected, a maximum writable value of the profile memory, and causing the profile memory to store said maximum writable value as a current cumulative value.

Abstract: A two-wire communication protocol between a controller device and a controlled device, wherein both devices are coupled by a clock line and a data line. The controller device sends control signals comprising N bits, N being greater than or equal to two, to the controlled device via the data line. Each bit of said control signals is latched onto the controlled device on consecutive edges of a clock signal sent by the controller device to the controlled device on the clock line.

Abstract: New version packet data devices support a backwards-compatible signal format. New version devices operate within a first frequency band while old version devices operate within a second frequency band. The first frequency band differs from but overlaps with the second frequency band. The new version devices may operate on a first carrier frequency (within the first frequency band) while old version devices may operate at a second carrier frequency (within the second frequency band). The new version devices and/or the old version devices may also support carrier-less modulations. Preamble, header, and trailer portions of a new version signal include a plurality of spectral copies of a baseband modulated signal. One or more of these spectral copies of the baseband modulated signal is/are indistinguishable from corresponding components of an old version signal. The payload of the new version signal may be formed in the same manner or may be formed in have a wider bandwidth, higher data rate format.

Abstract: A bit synchronization circuit composed of a multiphase data sampling unit for converting each received burst data sets to multiphase data trains, a phase determination unit for generating a control signal indicating an optimum phase data train, an output data selector for selectively passing optimum phase data train indicated by the control signal, and a data synchronization unit for converting the optimum phase data train to a data train in synchronization with a reference clock. The phase determination unit repeatedly detecting the optimum phase data train during the same burst data set is received. When optimum phase varies, the output data selector dynamically switches the optimum phase data train to be supplied to the data synchronization unit.

Abstract: In a method for measuring jitter, a signal under test is inputted to generate signal transition locations. A signal transition location is latched using a sampling clock signal, and the signal transition location is converted to a delay value. The delay value is converted to an edge position output, and a value of the edge position output is detected.

Abstract: A method of determining the delay between two corresponding noise-like signals comprises determining events at which the level of a first of the signal crosses a predetermined threshold, using each event to sample a second signal, combining the samples to produce an output value and determining the delay from the output value. Preferably, each sample is weighted according to one or more characteristics of the event used to define the sample. The magnitude of the output value could be an indication of the delay, or there could be several output values each for a respective differently-delayed version of the second signal, in which case these could be evaluated to select which corresponds to the actual delay.

Abstract: A communication system is provided in which normal communications can be ensured even upon a loss of synchronization on a part of transmission paths configuring a network. The system is to perform data communications within a network configured by a plurality of devices. A synchronization detecting section detects a loss of synchronization for data transmission between devices connected to each other via the network. Upon detection by the synchronization detecting section of the loss of synchronization, a control information retaining section and a switching section included in the first device cause a connection with the second device to be cut off, and then again cause a connection with the device. Upon connection caused by the switching section between the devices, a connection processing section 16 performs a connecting process for enabling data communications between these devices.

Abstract: A method and apparatus is provided for use in an inband signaling system for quickly resynchronizing devices in the system after synchronization is lost. Synchronization is quickly established by continuing to apply a synchronization technique even while the devices are synchronized, as opposed to starting the synchronization technique only after synchronization is lost.

Abstract: Techniques for pre-correction of transmit signals are disclosed. In one aspect, a transmit antenna array configurable to generate multiple transmit beams is deployed. The parameters for configuring the antenna array are computed in response to channel estimates and a noise floor estimate made at the receiver. Information is transmitted in accordance with the multiple transmit beams, delayed as necessary, such that the multipaths may arrive time-aligned an in-phase at the receiver. In another aspect, pre-RAKE pre-correction is deployed by calculating Wiener weights. In yet another aspect, space-time diversity is deployed for calculating tap values for FIR filters used in transmission on the transmit antenna array. In yet another aspect, space only pre-correction is deployed. Various other aspects are also disclosed. These aspects have the benefit of reducing the interference experienced at a receiver, resulting in increased capacity, increased data throughput, and other system benefits.

Abstract: An OFDM receiver includes an offset compensator (14) compensating for a frequency offset in a received OFDM signal. The offset compensator (14) includes a memory (51) storing two reference signals corresponding to arbitrary portions in the start symbol of the OFDM signal. A cross correlation value between the received OFDM signal and each of the two reference signals is calculated by a cross correlator (52, 53). Each peak position is detected by a peak detector (54). A frequency offset estimate value of the received OFDM signal is estimated by a frequency offset estimation circuit (55) based on the cross correlation value at each detected peak position. A phase rotation circuit (37) compensates for the frequency offset of the received OFDM signal based on the estimated frequency offset estimate value.

Abstract: A method for effecting synchronous pulse generation for use in variable speed serial communications is provided. The method includes the steps of obtaining a communication link speed; generating a difference signal representing a signal level difference between at least two data stream signals; providing a clock signal; providing a counter; defining a sample count value of the counter using the communication link speed; incrementing the counter in relation to the clock signal; and determining whether a current count value of the counter corresponds to the sample count value. If the current count value corresponds to the sample count value, then the method performs a step of generating a synchronous pulse.

Abstract: A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.

Abstract: An apparatus and a method of aligning data bits serially received at a channel input. A number of data bits including a first data bit are stored in a buffer that has a first buffer bit and a buffer size greater than the number of data bits. The data bits in the buffer are shifted to improve alignment of the first data bit and the first buffer bit. The shifted data bits are tested for alignment. If the testing of the data bits indicates correct alignment, then the aligned data bits are transmitted from the buffer to a host for use. If the testing of the data bits indicates misalignment, then the data bits are passed to an error handling process.

Abstract: A changeover arrangement for the clock signals of parallel transmission connections of an assured data transmission link, wherein a clock signal is sent for the transmission paths by parallel outdoor units (OU) located in succession to a common indoor unit (IU), the clock signal is received by a corresponding set of second outdoor units, where phase locked loop signals are used to achieve the lock to the signal, and subsequent to which a second IU receives information of the mode of the phase lock. In addition, when errors are caused in the employed connection, the receiving unit selects a transmission path that has fewer errors based on mode information obtained from the outdoor unit.

Abstract: A communication system 1 includes interrogators 10, 11 and transponders 20, 21, 22. The interrogator 10 transmits a carrier wave, FC1, to the transponders 20, 21, 22, and the transponders 20, 21, 22 return respective reflected waves, f1, f2, and f3, to the interrogator 10. The transponders 20, 21, 22 modulate the received carrier waves FC1 using respective subcarrier waves that have been modulated using respective information signals, and return the thus modulated carrier waves as the reflected waves f1, f2, and f3 to the interrogator 10.

Abstract: The demodulation unit demodulates a received signal. The detection circuit detects the final data contained in a received data stream supplied from the demodulation unit. When detecting the final data, the detection circuit outputs the final data notification signal. The standby period timer sets the standby time in accordance with the final data notification signal output from the detection circuit.

Abstract: A data modulation method and a data modulation device and a communication device are disclosed. The present invention relates to the synchronization and training preamble. The reference symbol optimized in order to contain the structure of “IA-A-IA-A-A-IA-A-IA-IA” is allocated to sub-carriers of the OFDM symbol. More specifically, by designing the structure of the preamble of the time domain, distinction from the other communication system can be certainly conducted holding the correctness of the clock synchronization. Also, we have adopted the series having low peak average ratio and dynamic range of sync symbol using the OFDM. Since the generation and the detection processings can be conducted in utilizing the generation device and the detection device of the sync preamble used in the convention system, this system has an advantage in increasing the common use of the LSI chip. We have made the sync series divided into 2 parts A and B before to one B region and made this to have simple construction.

Abstract: A method for effecting synchronous pulse generation for use in serial communications is provided. The method includes the steps of generating a difference signal representing a signal level difference between at least two data stream signals; providing a clock signal; providing a counter; defining a sample count value of the counter; incrementing the counter in relation to the clock signal; and determining whether a current count value of the counter corresponds to the sample count value. If the current count value corresponds to the sample count value, then the method performs a step of generating a synchronous pulse.

Abstract: A data structure, method and protocol wherein synchronization data indicative of a data frame delineation point is inserted within an inter-packet gap (IPG) proximate a data frame during transmission. Optionally, a cyclical redundancy check (CRC) length indicative data, pointer data, and other data is inserted within the IPG to further insure appropriate delineation of data frames within a data stream.

Abstract: A method for synchronizing communications in a wireless communications network wherein time synchronization is performed between a clock master and a clock slave. To achieve synchronization between the clock master and the clock slave, several time synchronization passes are initiated by the clock slave to the clock master. For every pass, each clock slave component generates and transmits a first timing cell containing a transmission time based on the clock slave's component clock, to the clock master. Upon receipt of the first timing cell, the clock master generates and transmits to the clock slave component a second timing cell containing the time the clock master received the first timing cell and the time the clock master transmitted the second timing cell. Upon receipt of the second timing cell, the clock slave component will obtain its reception time and calculate a transmission delay based on the reception time and the timing information contained in the timing cells.

Abstract: The present invention relates to a method of synchronisation between communication networks exchanging information by frame of informations, each communication network having clock and the number of clock pulses is monitored by a counter. The synchronisation is made by reading information representing the counted clock pulses of the clock of the first network at the appearance of a reference event, inserting at least said information or calculated information on the basis of said information into the frame of information as the synchronisation information, transferring said frame of information from the first to the second network, reading information representing the number of counted clock pulse of the clock of the second network at the appearance of reference event, reading synchronisation information inserted in received frame of information from the first network, calculating a difference between information and synchronising the second network.

Abstract: The clock switch device of the present invention includes: a clock detector for receiving a plurality of clocks and clock selection data designating a clock to be selected, detecting whether or not the clock designated by the clock selection data among the plurality of clocks changes in signal level, and outputting the result as a detection signal; a control register for holding and outputting the clock selection data when the detection signal indicates that the clock designated by the clock selection data changes in signal level; and a selector for receiving the plurality of clocks and selecting a clock corresponding to the output of the control register among the plurality of clocks.

Abstract: A circuit for glitch-free changing of clocks having different phases. The circuit comprises a phase detector for receiving a data stream and a system clock, and generating a phase-up signal and a phase-down signal; a flag signal generator for receiving the phase-up signal and the phase-down signal, and then generating M flag signals, wherein the select signal corresponding to the enabled flag signal is enabled; an output stage for receiving the M select signals and the M clocks, and then outputting the system clock.

Abstract: The number of pins on an integrated circuit chip is reduced by encoding control signals into a differential clock. The differential clock has two clock lines with complementary signals that together represent a clock. Control signals inside a clock-transmitting chip are input to an encoder which determines which control signal is being asserted or de-asserted. The encoder drives a clock-control signal that either forces both differential clock lines low or stops the differential clock from pulsing. A clock-receiving chip detects the both-low or stopped differential clock and determines which control signal was asserted or de-asserted. A phase-locked loop (PLL) in the receiver keeps an internal clock running even when the differential clock is missing pulses. A sequence of M1 missing clock pulses, followed by N1 clock pulses, followed by M2 missing pulses encodes the control signal, where M1, N1, and M2 are whole numbers.

Abstract: The present invention relates to an improved method of de-jittering MPEG-2 and MPEG-4 data that is transmitted over a network. First, a network system jitter associated with periodic reference data packets is estimated. Then, the estimated system jitter is used to adjust clock-stamped reference values in the data packets before they are provided to the PLL for clock synchronization. The invented de-jittering method improves the PLL's ability to synchronize the MPEG data and provides for a better quality playback.

Abstract: A system and method for detecting a synchronization (sync) signal in a communication signal are disclosed. A received communication signal is stored in a memory and portions thereof are read from the memory and monitored to detect the sync signal. When a detected sync signal is determined to be invalid, previously read portions of the received communication signal, preferably beginning at a portion of the received signal immediately after a start of the detected sync signal, are again read and monitored to detect the sync signal. Such reading and monitoring of previously read portions of a received signal provide for recovery from so-called false triggering based on invalid sync signals.

Abstract: A method of determining cross channel interference in an Discrete Multitone (DMT) implementation of a Digital Subscriber Line (DSL) system. The cross channel interference is determined utilizing a residual impulse spectrum after implementation of a Time Equalization (TEQ) algorithm. In one application the cross channel interference value is used in a bit allocation algorithm to improve such that more bits are allocated to the channels with low interference and fewer bits are allocated to those channels having high interference. In this application the bit allocation algorithm is run twice, once before the interference measurement and once after.

Abstract: In a CDR (clock data recovery) deserializer, a clock divider receives a recovered clock signal (SCLK) and generates a divided clock signal (RPCLK). The frequency of the divided clock signal is lowered with each cycle of the divided clock signal being generated for each count of cycles of the recovered clock signal up to a predetermined ratio number. A serial-to-parallel shift register shifts in recovered serial data bits with each cycle of the recovered clock signal and outputs the predetermined ratio number of the shifted recovered serial data bits at a predetermined transition of every cycle of the divided clock signal. A SYNC (synchronization) detect logic asserts a VRS (diVider ReSet) signal coupled to the clock divider for controlling the clock divider to generate the predetermined transition for a cycle of the divided clock signal when the VRS signal is asserted.

Abstract: A scalable clock recovery system. In one embodiment the system comprises a clock master unit, a clock distribution network, and a plurality of clock recovery units. The master clock unit generates a plurality of master clock signals, which are received by the clock recovery units. The clock recovery units use multiple stages of mixing to generate a recovered clock. The recovered clock can be used to recover data from a serial data stream.

Abstract: A resampler, method of resampling a signal and a bit pump and transceiver employing the same. In one embodiment, the resampler includes an interpolation stage, coupled to an input of the resampler, that receives a one-bit input signal representing at least a portion of a receive signal propagating along a receive path of the bit pump and generates a plurality of intermediate samples from at least two input samples associated with the one-bit input signal. The resampler also includes a selection stage, coupled to the interpolation stage, that selects one of the plurality of intermediate samples thereby providing an output sample that corresponds to a phase of an oscillator associated with the bit pump.

Abstract: An apparatus and a method of controlling image display in an image display apparatus having a panel and wherein an image output is synchronized to a frame synchronization signal of an input signal. The method includes determining whether or not an input synchronization signal is an abnormal synchronization signal, processing the abnormal synchronization signal if the input synchronization is the abnormal synchronization signal, and removing damaged frame data if the abnormal synchronization signal is processed.

Abstract: A circuit generating an output phase signal with an optionally variable phase shift relative to a reference phase. It includes an oscillator (10) outputting phase signals at n outputs, each of which differs in phase by ?=360°/n. These phase signals are applied selectively via multiplexers to a phase interpolator, at the output of which the signal changed in phase relative to a reference phase. The output phase signal is generated in a charging circuit in which a capacitor can be varied by signaling current sources ON/OFF with the aid of phase switches in accordance with the phasing to be produced for the output signal. To avoid jitter in the transition from one phase to another separating switches are inserted in the connection between the current sources and the charging circuit, these separating switches being controlled so that they are never open at the same time.

Abstract: A system for implementing time stamp related features in a real time stamp distribution system is discussed. The distribution system derives a real time stamp (RTS) at a master timekeeping network element and distributes the RTS to associated network elements by way of a number of distribution techniques. Under certain network conditions, the real time stamp may not reach one or more of the network elements at the valid real time. In the present system, the network elements are able to derive a local time based on timing information recorded at the network element. Thus the system can detect an error in the time stamp delivered to a network element and can correct the time stamp utilizing a local time stamp feature.

Abstract: In a clock-pulse supply unit, a first receiver unit is used to tap a central system clock pulse from the back panel. A time delay occurs in the first receiver unit. In order to compensate this time delay, a second receiver unit is used which is identical in construction to the first receiver unit and has the same time delay as the first receiver unit. A redundant clock pulse is supplied to the second receiver unit and thereby undergoes the same time delay as the central system clock pulse in the first receiver unit. The central system clock pulse and the redundant clock pulse can then be accurately compared with one another in a phase detector. The redundant clock pulse is then synchronized to the central clock pulse. The switchover from a slave clock pulse to the redundant clock pulse is effected only when synchronization is completed.

Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.

Abstract: The invention describes a method and a system for fast and economic synchronization of multiframe structures, such as PDH multiframe binary signals, by detecting a periodic binary signature in a binary signal using one final state machine (FSM) comprising a logical scheme interconnected with a memory block having a plurality of independent memory cells with serial numbers for cyclically connecting thereof to the logical scheme; the signature is detected by applying the signal to the FSM while synchronously switching the cells to the FSM. The arrangement is such that when the predetermined periodic binary signature occurs in the signal, one of the cells will reach its predetermined terminal state.

Abstract: A wireless receiver for receiving an incoming signal having spatial and temporal diversity. The receiver uses noise-based prescaling of multiple receiver chain signals for optimally combining the receiver chain signals in a composite equalized signal and uses noise-based time-varying postscaling the equalized signal. The receiver determines noise-based scale factors by comparing signal symbols to dispersed replica symbols of a training sequence for the incoming signal.

Abstract: Methods and apparatus implementing techniques for prevention of metastability in a bistable circuit. The techniques include detecting a change in a data signal, sampling the detected change in reference to a sampling window of a clock signal input of a bistable circuit to determine if the detected change occurs within the sampling window, and selecting a stable data input to present to an input of the bistable circuit based on whether the detected change occurs within the sampling window. The sampling window represents a time period during which a change in the data signal can cause metastability in a bistable circuit.

Abstract: A wireless network is provided with a method to eliminate the commonly encountered problems associated with the development of the master timing in a network. According to the provided method, the master network timing is completely eliminated. Accordingly, in an exemplary implementation of the present invention, each node of a network has its own master clock used for transmissions that is free running and not adjusted in any way. Each node has also a receiver equipped with a mechanism to acquire and track the timing of all the network nodes that are within the communications range and that are permitted the access. In essence there is no master network timing and each transmitter hops and transmits according to its master clock. Furthermore, it is the responsibility of each receiver to track multiple timing separately for each hopping transmitter. The provided method is suitable for a wide range of applications including wireless networks and in particular for networks using frequency hopping.

Abstract: The present invention refers to methods and apparatuses for providing synchronization in a time division multiplexed network, wherein data is transferred on multi-access bitstreams in circuit-switched channels that are defined by respective time slots of regularly recurrent frames of said bitstreams, said frames being defined by regularly recurrent frame synchronization signals transferred on said bitstreams. According to the invention an auxiliary regularly recurrent frame synchronization signal is generated and selected as a basis for defining said frames on a bitstream if the frame synchronization signal that is used as a basis for synchronizing said frames during normal operation is not detected in accordance with an expected frame rate.

Abstract: A method for switching between multiple clock signals in a digital circuit is provided that includes providing to a clock selector at least three distinct clock signals for the circuit. A master clock signal for the circuit is generated with the clock selector based on a first one of the distinct clock signals. The master clock signal is asynchronously blocked. The master clock signal for the circuit is generated with the clock selector based on a second one of the distinct clock signals. The master clock signal is synchronously unblocked.

Abstract: Detection of synchronization signals of digital broadcasting waves of respective reception systems is periodically carried out, and a relative time difference between synchronization timings of the synchronization signals is grasped. In the case where a synchronization signal can not be detected from the reception system under selection, the relative value is added to or subtracted from the generation timing of a synchronization signal of the other reception system, so that the synchronization timing that could not be detected is presumed.

Abstract: Group-wise testing of the clocks arriving at a switching office is undertaken by multiplexing the clocks onto a single line and developing a signal therefrom that is indicative of a problem, if it exists, in any of the component signals that were multiplexed. In one embodiment, the developed signal is a gated portion of the multiplexed signal. That signal is integrated over an integration frame and compared to the integrated signal of another integration frame. A difference between the two compared signals indicates that at least one of the clocks is out of frequency synch. Subsequent tests identify the offending clock, or clocks.

Abstract: A method for detecting synchronization loss of the trellis minimum path metric in V.34 modem communications. The invention detects synchronization loss due to bit inversions in trellis decoding in transmitted digital frames due to a periodic inversion pattern that is used for superframe synchronization. The method provides synchronization loss detection by finding the ratio of moving averages for a series of data blocks to the average of a series of inverted 4D symbols located periodically in the beginning and center of received data frames.