Abstract: The present invention discloses a clock data recovery method having quick locking and bandwidth stabilizing mechanism used in a clock data recovery circuit. A relative position relation between a serial data and a sampling clock is detected by a phase detection circuit in an adaptive control period to generate a tracking direction. The tracking direction of a first clock period is directly outputted as an adaptive tracking direction by an adaptive tracking circuit. For each of the clock periods behind the first clock period, a previous tracking direction is replaced by a current tracking direction only when the current tracking direction exists and is different from the previous tracking direction of a previous clock period such that an actual tracking direction is generated when the adaptive tracking direction changes. The phase of the sampling clock is adjusted according to the actual tracking direction by a clock control circuit.

Abstract: A test and measurement system has a test and measurement instrument, a test automation platform, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to receive a waveform created by operation of a device under test, generate one or more tensor arrays, apply machine learning to a first tensor array of the one or more tensor arrays to produce equalizer tap values, apply machine learning to a second tensor array of the one of the one or more tensor arrays to produce predicted tuning parameters for the device under test, use the equalizer tap values to produce a Transmitter and Dispersion Eye Closure Quaternary (TDECQ) value, and provide the TDECQ value and the predicted tuning parameters to the test automation platform.

Abstract: According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.

Abstract: Systems, methods, and devices estimate timing values for data transmission associated with wireless communications devices. Methods include receiving, at a transceiver of a wireless communications device, at least one symbol included in a data transmission, obtaining a plurality of samples of the at least one symbol, and generating, using one or more processors, a plurality of correlation values for each of the plurality of samples. Methods further include generating, using the one or more processors, a multi-sample interpolation model based on at least some of the plurality of correlation values and determining, using the one or more processors, an estimated maximum correlation value and a temporal offset value based on the multi-sample interpolation model, the temporal offset value being used for a time of arrival computation.

Abstract: Precision digital chronography based on detected changes in state of a processor is described. The changes in state may be detected by another processor and an averaged time interval generated. A signal corresponding to the averaged time interval may be communicated to a distributed database and propagated to remote systems. Devices associated with the remote systems may adjust or set a device clock in accordance with the averaged time interval.

Abstract: A method for operating a redundant automation system for controlling a technical process in which two-out-of-three system with three subsystems are operated, wherein a comparator is cyclically operated in each subsystem and compares the first, second and third output data with one another, and a respective comparator is operated such that, during each comparison in which the result is that all output data are approximately the same, no further action is performed, and during a comparison in which deviations between the output data are determined, that subsystem in which the deviations of its own output data from the other output data are the greatest is identified as faulty via a majority decision.

Abstract: A test and measurement instrument has an input configured to receive a signal from a device under test, a memory, a user interface to allow the user to input settings for the test and measurement instrument, and one or more processors, the one or more processors configured to execute code that causes the one or more processors to: acquire a waveform representing the signal received from the device under test; generate one or more tensor arrays based on the waveform; apply machine learning to the one or more tensor arrays to produce equalizer tap values; and apply equalization to the waveform using the equalizer tap values to produce an equalized waveform; and perform a measurement on the equalized waveform to produce a value related to a performance requirement for the device under test.

Abstract: Provided is a zero crossing point signal output method, including: continuously receiving zero crossing point square wave signals, and periodically sampling zero crossing point square wave signals at a predetermined sampling frequency; acquiring sampling numbers of 1st to Mth zero crossing point square wave signals to obtain an average sampling number S, and calculating a first zero crossing point interval T1; setting a zero crossing point signal output interval as the first zero crossing point interval T1; continuously outputting zero crossing point signals with an interval being the zero crossing point signal output interval; obtaining sampling numbers of M+1th to M+Nth zero crossing point square wave signals, calculating a difference value between each of the sampling numbers and S, and obtaining an accumulated difference value ?s through calculation; when ?s is not within a predetermined change range, obtaining a second zero crossing point interval T2 and setting the zero crossing point signal output inte

Abstract: Sequences to synchronize devices and related methods are disclosed herein including an access address generator to cryptographically generate a first bit sequence, an access address selector to read a first portion of the first bit sequence and read a second portion of the first bit sequence, the second portion different than the first portion, an access address analyzer to identify a first access address from a first section of the first portion based on a first criteria, the first criteria a function of a first autocorrelation function and identify a second access address from a second section of the second portion based on a second criteria, the second criteria a function of a second autocorrelation function.

Abstract: Embodiments of the present disclosure relate to methods and apparatuses of synchronization signal transmission and receiving in a wireless communication system. The method of synchronization signal transmission in a wireless communication system may comprise transmitting a signal set containing one or more synchronization signals, wherein the one or more synchronization signals are transmitted in a predetermined signal transmission pattern within a signal transmission period, and wherein the predetermined signal transmission pattern indicates information on synchronization signal transmission. With embodiments of the present disclosure, it may indicate the information on synchronization signal transmission information by means of the signal transmission mode. Thus, especially for an initial access process, it can provide a common frame for both single beam based deployment and multi-beam based deployment.

Abstract: One embodiment of the present invention sets forth a technique for communicating within a network. The technique includes receiving, from a first node in the network and at a first receive time, a first periodic beacon that includes a first network time associated with the first node. The technique also includes determining a first transmission time of a first unicast message to the first node based on the first network time and a unicast interval between consecutive unicast listening times on the first node. The technique further includes transmitting the first unicast message to the first node at the first transmission time.

Abstract: A test and measurement instrument, such as an oscilloscope, having a Nyquist frequency lower than an analog bandwidth, the test and measurement instrument having an input configured to receive a signal under test having a repeating pattern, a single analog-to-digital converter configured to receive the signal under test and sample the signal under test over a plurality of repeating patterns at a sample rate, and one or more processors configured to determine a frequency of the signal under test and reconstruct the signal under test based on the determined frequency of the signal, the pattern length of the signal under test, and/or the sample rate without a trigger.

Abstract: A method for communication in a network that includes multiple nodes having respective network interfaces and interconnects between the network interfaces, which include at least first and second network interfaces connected by a physical interconnect having a given latency. The method includes defining a target latency, greater than the given latency, for communication between the first and second network interfaces. Data are transmitted between the first and second network interfaces over the physical interconnect while applying, by at least one of the first and second network interfaces, a delay in transmission of the data corresponding to a difference between the target latency and the given latency.

Abstract: Disclosed is an operating method of an encoder, which includes receiving a first bit stream including first to N-th bits, determining at least one symbol in the first bit stream, wherein the at least one symbol includes “M” consecutive bits each having the first bit value or the second bit value, and generating a first data packet including a first header and at least one packet symbol. The first header includes a least symbol address of a first symbol of the at least one symbol and an inverted value of a bit value of the first bit, a first packet symbol of the at least one packet symbol includes a bit value of the first symbol, a least symbol address of a second symbol of the at least one symbol, and an inverted value of a bit value of a next bit of the first symbol.

Abstract: Optical transmitters and receivers for improving synchronization of data transmitted over an optical network are described. The receiver can perform non-linear filtering as part of framer index estimation operations to improve the synchronization. The receiver can determine estimated positions of framer indices in data frames received from the transmitter. Next, using a non-linear filter, the receiver can remove estimated positions that are likely erroneous or are greater than a threshold away from the median or mode estimated framer index position. By removing the likely erroneous estimated positions, the receiver can then determine the estimated position of a framer index position for multiple frames with greater confidence.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Abstract: Precision digital chronography based on detected changes in state of a processor is described. The changes in state may be detected by another processor and an averaged time interval generated. A signal corresponding to the averaged time interval may be communicated to a distributed database and propagated to remote systems. Devices associated with the remote systems may adjust or set a device clock in accordance with the averaged time interval.

Abstract: A phase-shifted sampling module for sampling a signal is described. The phase-shifted sampling module includes a primary sampler module, an ADC module, and an equalization module. The primary sampler module includes an analog signal input, a first signal path, and a second signal path. The equalization module includes a primary sampler equalizer sub-module. The primary sampler equalizer sub-module is configured to compensate low-frequency mismatches between the first signal path and the second signal path. Further, a method for determining filter coefficients of an equalization module of a phase-shifted sampling module is described.

Abstract: A digital signal processing (DSP) device includes a first fitter to equalize channel dispersion associated with signal transmission through a medium, a second filter to cancel channel reflections, and a third filter to at least reduce noise. The DSP device is a receiver DSP of the SERDES.

Abstract: A method for execution by a low voltage drive circuit (LVDC) operably coupled to a bus includes, when activated, setting data reception for a control channel of a plurality of channels on the bus, where the control channel is a sinusoidal signal having a known frequency. The method further includes receiving the control channel and capturing a cycle of the control channel when the control channel is void of a data communication. The method further includes comparing the cycle of the control channel with a cycle of a first receive clock signal of the LVDC and when the cycle of a first receive clock signal compares unfavorably to the cycle of the control channel, adjusting phase and/or frequency of the cycle of the first receive clock signal to substantially match phase and/or frequency of the cycle of the control channel to produce an adjusted first receive clock signal.

Abstract: A transmitter includes output drivers respectively corresponding to data transmission lines, driver control logic configured to control the output drivers in response to data pattern information, and a data pattern detector configured to detect a data pattern in relation to at least two data transmission lines among the data transmission lines over a predetermined period of time, and output the data pattern information corresponding to the data pattern.

Abstract: An apparatus includes a receiver buffer, a phase compensation circuit, a data sampler circuit, and an error sampler circuit. The receiver buffer may generate an equalized signal on a signal node using an input signal received via a channel. The phase compensation circuit may, in response to an initiation of a training mode, replace the equalized signal on the signal node with a reference signal. The data sampler circuit may sample, using a data clock signal, the reference signal to generate a plurality of data samples. The error sampler circuit may sample, using an error clock signal, the reference signal to generate a plurality of errors samples. The phase compensation circuit may also adjust a phase difference between the data clock signal and the error clock signal using at least some of the plurality of data samples and at least some of the plurality of error samples.

Abstract: Systems and methods are disclosed herein that relate to Peak-to-Average Power Ratio (PAPR) reduction in a MIMO OFDM transmitter system. In some embodiments, a method of operation of a transmitter system includes, for each carrier of two or more carriers, performing precoding of frequency-domain input signals for the carrier to provide frequency-domain precoded signals for the carrier, the frequency-domain input signals for the carrier being for a plurality of transmit layers for the carrier, respectively. The method further includes processing the two or more pluralities of frequency-domain precoded signals for the two or more carriers, respectively, in accordance with a multi-carrier processing scheme to provide a plurality of multi-carrier time-domain transmit signals for a plurality of antenna branches, respectively, of the MIMO OFDM transmitter system.

Abstract: A multi-level signal receiver includes a data sampler having (M?1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M?1) reference voltages, to thereby generate (M?1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M?1) sense amplifiers by: (i) adjusting at least one of (M?1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M?1) reference voltages during a second training mode, based on equalized values of the (M?1) comparison signals, where each of the (M?1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

Abstract: A method of operating a communicator includes operating a first receiver of a plurality of receivers on a first channel of a series of channels. A second receiver of the plurality of receivers is operated on a second channel of the series of channels. A third receiver of the plurality of receivers is operated on a third channel of the series of channels. The second receiver that operates on the second channel includes a reception overlap period of about 25% to about 75% with the first receiver that operates on the first channel and a reception overlap period of about 25% to about 75% with the third receiver that operates on the third channel.

Abstract: A device for retrieving media includes a memory configured to store media data of a media presentation; and one or more processors implemented in circuitry and configured to: retrieve a manifest file for a media presentation indicating that container parsing of media data of a bitstream can be started at a resync point of a segment of a representation of the media presentation, the resync point being at a position other than a start of the segment and representing a point at which the container parsing of the media data of the bitstream can be started; use the manifest file to form a request to retrieve the media data of the representation starting at the resync point; send the request to initiate retrieval of the media data of the media presentation starting at the resync point; and present the retrieved media data.

Abstract: A method of reading data includes: receiving a digital signal, wherein the digital signal includes a sync signal and a data signal; performing an oversampling operation to the digital signal, and calculating a plurality of sampling points according to the oversampling operation; by a first counter counting the sampling points to obtain a first count value; based on the first count value defining a second count value; defining a unit interval; in the unit interval, defining a data reading range; and in the data reading range, reading the data signal corresponding to data of the unit interval as a first value when a potential of each of the sampling points counted is changed from a first potential to a second potential.

Abstract: A method includes setting a current level of a write signal to a first non-zero value for a first period of time. The write signal is provided to a memory element during the first period of time. The current level of the write signal is adjusted from the first non-zero value to a second non-zero value, different from the first non-zero value, for a second period of time. The write signal is provided to the memory element during the second period of time. The current level of the write signal is adjusted from the second non-zero value to a third value, different from the first non-zero value and different from the second non-zero value, for a third period of time. The write signal is provided to the memory element during the third period of time.

Abstract: The present disclosure describes techniques and systems for wireless communications between a base station [120] and a user equipment [110] using an enhanced radio-resource control idle mode. The described techniques and systems enable a user equipment [110] to receive a radio-resource control release message [410] that includes a cell radio-network temporary-identifier and, in response, enter [415] the enhanced radio-resource control idle mode. While in the enhanced radio-resource control idle mode, the user equipment [110] may receive a message [420] in accordance with the cell radio-network temporary-identifier and present the received message.

Abstract: A method for protecting data includes encrypting information to generate a first tweak, combining a data block with the first tweak, encrypting the tweaked data block to form encrypted data, combining the encrypted data with the first tweak, and providing the combined encrypted data for storage in a memory address. Storing the combined encrypted data at the memory address generates a first stimulus different from a second stimulus generated by storing same encrypted data combined with a second tweak at the memory address. The first stimulus is generated based on the first tweak and the second stimulus is generated based on the second tweak.

Abstract: An endoscope system includes at least any one of a processor device that is attachable to and detachable from an endoscope or a light source device that is attachable to and detachable from the endoscope. In a case where the endoscope is mounted on the processor device or the light source device, the processor device or the light source device performs a request sequence in which a request signal, for requesting a start of execution of encoding processing with respect to digital image signals, is transmitted to the endoscope.

Abstract: Apparatus including a shared device in communication with a plurality of computing machines external to the shared device, the shared device including at least one PTP domain coefficient storage area, the at least one PTP domain coefficient storage area receiving a PTP coefficient from a computing machine having a PTP client, and providing the PTP coefficient to a computing machine not having a PTP client. Related apparatus and methods are also provided.

Abstract: A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

Abstract: A method for cloud gaming. The method including generating a video frame when executing a video game at a server. The method including performing a scan-out process to deliver the video frame to an encoder configured to compress the video frame, wherein the scan-out process begins at a flip-time of the video frame. The method including transmitting the video frame that is compressed to a client. The method including determining at the client a target display time for the video frame. The method including scheduling at the client a display time for the video frame based on the target display time.

Abstract: In one embodiment, a local clock is synchronized to a master clock using a Kalman filter to determine state variables using a state transition matrix that includes at least one coefficient that is associated with a digital-to-analog converter (DAC), where the state variables include a unit step variable indicative of a unit step for the system. The local clock is controlled based on the state variables determined using the Kalman filter. The unit step is indicative of an amount by which the frequency of the local clock signal changes in response to a change in the digital input of the DAC.

Abstract: In a delay circuit, first and second sets of transistors are connected in series between a supply voltage and a ground. The first and second sets of transistors both include a current source transistor, a cascode transistor, and a control transistor. The first set of transistors generates a current that charges a capacitor to generate a ramp signal with a positive slope. A first bias transistor may cause the ramp signal to be biased to ground upon activating the first set of transistors. The second set of transistors generates a current that discharges the capacitor to generate the ramp signal with a negative slope. A second bias transistor may cause the ramp signal to be biased to the supply voltage upon activating the second set of transistors. The delay circuit transitions the state of the output signal based on a voltage level of the ramp signal.

Abstract: A communication device including a clock, a memory, and at least one processor is disclosed. The at least one processor is configured to execute instructions stored in the memory that cause the at least one processor to perform operations including receiving at least one message from a second communication device of a plurality of communication devices over a preconfigured time duration, determining a first local time of the clock of the communication device at which the at least one message from the second communication device is received, and determining a sync-time of the second communication device based on the at least one message from the second communication device. The operations include mapping the sync-time of the second communication device based on the first local time and the determined sync-time of the second communication device and adjusting a sync-time of the communication device based on the second local time.

Abstract: The present application provides a salt and pepper noise filtering method and device based on morphological component analysis. The method comprises: obtaining a to-be-filtered image containing salt and pepper noise; calculating the dimension of the to-be-filtered image, labeled as [n, m]; initializing an n*m-dimensional all-1 labeled matrix as a salt and pepper noise labeled map; obtaining a preset region centered on a pixel point with a pixel value of 0 or 255, and calculating a noise variance between the pixel points in the preset region; labeling the position of a salt and pepper noise point in the salt and pepper noise labeled map according to the noise variance between the pixel points in the preset region, and updating and determining the salt and pepper noise labeled map. The salt and pepper noise is filtered through the method based on morphological component analysis, which improves the quality of the image.

Abstract: A system receives a first clock signal with a first frequency and a second clock signal having a second frequency lower than the first frequency. The system generates a new second clock signal aligned with the first clock signal based on a known phase/frequency relationship between the clock signals. A counter counts cycles of the first clock signal. The system generates a new second clock signal with an edge aligned with a first clock signal when the counter reaches a predetermined count value and the system resets the counter. A window opens that includes a time period when the edge of the first clock signal is expected. If an edge of the first clock signal is detected outside of the window, the counter is reset responsive to the detected edge.

Abstract: Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy.

Abstract: A chip-carrier package includes a data processing system having one or more slave dies, a master die and a system bus. Each slave die includes a slave device and a slave-side wireless bus interface (WBI) coupled to the slave device. The master die includes a master device, one or more bus-side WBIs coupled to the master device. Each bus-side WBI is configured to be wirelessly coupled to at least one slave-side WBI of the one or more slave dies and a system bus. The system bus includes the one or more bus-side WBIs and the slave-side WBIs of the one or more slave-side dies. The system bus is configured to exchange information between the master device and the slave devices of the one or more slave dies.

Abstract: Circuits and methods for performing a clock and data recovery are disclosed. In one example, a circuit is disclosed. The circuit includes an FSM. The FSM includes: a first accumulator, a second accumulator, and a third accumulator. The first accumulator is configured to receive an input phase code representing a phase timing difference between a data signal and a clock signal at each FSM cycle, to accumulate input phase codes for different FSM cycles, and to generate a first order phase code at each FSM cycle. The second accumulator is coupled to the first accumulator and configured to accumulate the input phase codes and first order phase codes for different FSM cycles, and to generate a second order phase code at each FSM cycle. The third accumulator is coupled to the second accumulator and configured to accumulate the input phase codes and second order phase codes for different FSM cycles, and to generate a third order phase code at each FSM cycle.

Abstract: The frequency stability of an optical local oscillator is improved by locking a laser to a silicon Fabry-Perot cavity operating at a temperature near 124 K, where the coefficient of thermal expansion of silicon is near zero. The cavity is mounted inside a cryostat housed in a temperature-stabilized vacuum system that is surrounded by an isolating enclosure and supported by an active vibration platform. Laser light is steered with a superpolished mirror toward a superpolished focusing optic that couples the laser light into the cavity. Light reflected from the cavity is used to stabilize the laser via the Pound-Drever-Hall technique, while light transmitted through the cavity is used to stabilize the laser power. A resonant transimpedance amplifier allows the laser power to be reduced, which reduces heating of the cavity caused by residual absorption of the light.

Abstract: A method for synchronizing a logical clock in a device comprising a physical clock, an input port, and an output port, the device further comprising a logical clock and a time compensation clock sharing the physical clock, the time compensation clock making it possible to determine a residence time, comprising obtaining a theoretical residence time, during a pre-synchronization phase according to which the logical clock is not synchronized, adding a value representative of the obtained theoretical residence time to a residence time value stored in a synchronization message to be forwarded, during a synchronization phase according to which the logical clock is synchronized, obtaining a residence time and adding a value representative of the obtained residence time to a residence time value stored in a synchronization message to be forwarded, and synchronizing the logical clock as a function of a residence time value stored in a received synchronization message.

Abstract: An interface is provided for processing digital signals in a standardized format in a distributed antenna system. One example includes a unit disposed in a distributed antenna system. The unit includes an interface section and an output section. The interface section is configured for outputting a first complex digital signal and a second complex digital signal. The first complex digital signal is generated from a digital signal in a standardized format received from a digital base station. The output section is configured for combining the first complex digital signal and the second complex digital signal into a combined digital signal. The output section is also configured for outputting the combined digital signal. The combined digital signal comprises information to be wirelessly transmitted to a wireless user device.

Abstract: Embodiments relate to a predictor device for controlling at least one actuating variable of a plant having at least one actuator, which can be controlled by the actuating variable, and a state with at least one controlled variable that can be detected by a sensor. The predictor has an adaptation device and an L1-adaptive control apparatus. The predictor has a state modelling device for estimating a behavior of the plant and outputs an estimated state with at least one estimated variable. The embodiments relate to an aircraft with such a control device for flight control. The embodiments also relate to an L1-adaptive control method using an L1-adaptive control apparatus, an adaptation device generating a matched uncertainty signal and an unmatched uncertainty signal, and a predictor having a state modelling device. The embodiments relate to an aircraft with a control device for flight control, which executes such a method.

Abstract: A communication device for a vehicle includes: a transmitting section that transmits differential signals from a first control section to a second control section via a transmission path; a receiving section that receives the differential signals that were transmitted to the second control section by the transmitting section; a skew measuring section that measures a signal difference of the differential signals on the transmission path; and a transmitting/receiving skew correcting section that, based on the signal difference measured by the skew measuring section, corrects both transmitting time differential signals that are transmitted from the first control section and receiving time differential signals that are received at the second control section.

Abstract: A delay adjustment circuit, comprising: a detection circuit configured to output a control signal upon detecting a data signal edge; a timing circuit configured to obtain a setup time and a hold time according to the control signal; a computation circuit configured to perform a computation with respect to a plurality of setup times and a plurality of hold times so as to obtain time information of a row data signal; and an adjustment circuit configured to correspondingly adjust, according to the time information and a preset relative time delay, a relative time delay between an output data signal and a clock signal.

Abstract: A method, system, and apparatus enabled to selectively choose a baud rate for communication of optical data using a modem enabled to operate with an optical signal modulated at plurality of finely tuned baud rates.