Abstract: Systems and methods are disclosed for adjusting clock frequencies of endpoint devices in a mesh network for narrowband and ultra-narrowband communications. An endpoint device receives a reference timing signal over a wireless network from a reference device in the network. The endpoint device determines the current value of the clock frequency of the endpoint device and further determines the frequency difference between the reference frequency of the reference timing signal and the current value of the clock frequency. Based on the frequency difference, the endpoint generates a control signal and applies the control signal to the crystal oscillator of the endpoint device to adjust the frequency of the crystal oscillator. The endpoint device communicates with another device in the network using the oscillating signal generated by the adjusted crystal oscillator.

Abstract: An ADC (12) in an optical receiver (1) generates a sample signal composed of time series samples by oversampling a received signal that is an electrical signal converted from an optical signal by a light receiving unit (11). A symbol timing detection unit (132) of a DSP unit (13) detects a symbol timing in the sample signal. When it is determined that a symbol timing is appearing at a longer interval than a predetermined interval based on this detection result, a symbol timing adjusting unit (133) skips one or more samples included in the sample signal to read out samples at the predetermined interval, while when it is determined that the symbol timing is appearing at a shorter interval than the predetermined interval, the symbol timing adjusting unit inserts the same samples as one or more samples included in the sample signal immediately after the one or more samples to read out the samples at the predetermined interval.

Abstract: A signal transmission system has a modulation signal converter 1 that generates a modulation signal using a Manchester code with a duty ratio of 50% in accordance with transmission data; a clock generator 6 that generates a clock with the amount of delay with respect to the rising or falling edge of the modulation signal; and a data detector 5 that generates received data by sampling the modulation signal in synchronization with the clock. Since the modulation signal converter 1 generates the modulation signal by combining the Manchester code with the duty ratio of 50%, its duty ratio is always 50% independently of the transmission data, thereby preventing the DC offset of the modulation signal on the receiving side. Accordingly, it offers an advantage of achieving good communication quality with a simple circuit configuration without producing the DC offset in the modulation signal on the receiving side.

Abstract: An implantable medical device is provided having circuitry to control operation of the implantable medical device and a receiver configured to receive communication signals on an allocated band of a plurality of communication channels separated in frequency by a channel spacing. The receiver includes an oscillator and a signal source configured to apply a quench signal to the oscillator. The quench signal has a frequency corresponding to the channel spacing. The receiver is enabled to receive on all of the plurality of communication channels simultaneously by applying the quench signal.

Abstract: One aspect of the present invention includes a bi-phase communication receiver system. The system includes an analog-to-digital converter (ADC) configured to sample a bi-phase modulation signal to generate digital samples of the bi-phase modulation signal. The system also includes a bi-phase signal decoder configured to decode the bi-phase modulation signal based on the digital samples. The system further includes a preamble detector comprising a digital filter configured to evaluate the digital samples to generate an output and to detect a preamble of the bi-phase modulation signal for decoding the bi-phase modulation signal based on the output.

Abstract: An embodiment of the invention includes a receiver with reduced error terms and incoming jitter tracking that improves jitter tolerance. An embodiment provides these benefits based on a voltage integrator that recovers data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. An embodiment provides these benefits based on a time integrator that recovers, using digital logic, data and clock information from incoming signals without use of a PLL, PI, CDR, and the like. Other embodiments are described herein.

Abstract: A wireless communication apparatus receives a wireless signal whose phases represent data values and determines the data values represented in the phases of the wireless signal. The apparatus includes a counter that updates a count value at a frequency higher than a frequency of the wireless signal, and resets the count value to an initial value when the phase of the wireless signal changes or when the counter overflows, a capture timing setting unit that sets a phase capture value in response to a resetting of the count value, and a phase capturing unit that captures the phase of the wireless signal when the count value reaches the phase capture value.

Abstract: Two Manchester encoded bit streams each bit stream with accompanying embedded clock data are disclosed. The two encoded bit streams are encoded at the source using opposite polarities of the source clock to position transitions within the bit streams at the rising and falling edges of the source clock. The receiver may extract the clock data from both bit streams. Because both rising and falling edge clock data is available between the two bit streams, the receiver does not need a phase locked loop (PLL) or incur the accompanying expense of such PLL. Further, by avoiding use of a PLL, a nearly all digital circuit may be created, which may provide further cost and space savings. Still further, a higher data throughput is provided without increasing pin count or signal bandwidth.

Abstract: A sensor circuit for obtaining physical quantities with a small margin of error even when the temperature varies is provided. The sensor circuit includes a sensor, a sampling circuit for obtaining a voltage value or a current value of a signal output from the sensor during a predetermined period and holding the value, and an analog-to-digital converter circuit for converting the held analog voltage value or current value into a digital value. The sampling circuit includes a switch for obtaining the voltage value or the current value and holding the value. The switch includes a transistor including an oxide semiconductor in a channel formation region.

Abstract: Methods and apparatus are presented for obtaining clock data from Manchester coded serial data streams, in which received data is sampled at a sample rate higher than the serial data baud rate, multi-bit groups of transition bits are generated which individually indicate data transition locations in a corresponding multi-bit sampled data bit group, and clock data is derived using the multi-bit groups of transition bits without requiring receipt of synchronization data or receipt of a separate clock.

Abstract: A communications system and protocol for a radio communications network including a number of transceiver devices. The protocol ensures that network variables to be shared by all devices are correctly received and updated by all devices. The protocol also provides for accurately detecting the transition from one time slot to another, in a given data transaction. The protocol utilizes a method of providing a marker in a data time frame for use such as marking the end of a variable slot in a data frame. The method includes encoding data into states, and then generating a marker that is an illegal combination of states in the encoding scheme.

Abstract: A communication system includes a communication station that converts a value information into a code value based on a corresponding relationship in which a difference between a first value information and a second value information is set to any value equal to or greater than two, where the second value information corresponds to a code value where an error occurs in one bit of the code value corresponding to the first value information.

Abstract: There is provided an information processing apparatus, including a signal receiver that receives a signal encoded in such a way that a signal containing a first bit value and a second bit value, wherein the first bit value is represented by first amplitude values, the second value is represented by a second amplitude value, and polarity of the encoded signal amplitude value is reversed in each period, a conversion processor performs conversion to add a delayed signal that is delayed by delaying a signal received by the signal receiver by one period of the received signal, an inversion processor that performs inverse processing of the conversion on the signal output from the conversion processor, and an input data decoder that decodes an input data by determining the first and second values based on the amplitude value of the signal output from the inversion processor.

Abstract: Biphase mark codes (BMC) are used in digital communications. Most BMC formats use preambles for rate determination and synchronization. A decoder compares the intervals of continuous high or continuous low voltages in a BMC stream to predetermined minimum and maximum values of half cell, full cell and one-and-a-half cell intervals for all supported sampling rates. If a pattern matching a preamble is found, the sampling rate is locked in and the decoder is synchronized to the BMC stream. Once locked, the decoder uses the predetermined minimum and maximum values at the locked rate to generate half cell, full cell and one-and-a-half cell indicators for a decoding state machine which decodes data in the BMC stream or decodes expected preambles.

Abstract: Disclosed is a method for modulating and demodulating data. The method composes symbols by grouping a plurality of symbols for pulse position modulation to newly add symbol compositions to fixed symbols used for the pulse position modulation of the related art. Further, the method uses grouped symbols to improve data transmission rate as the average amount of information increases.

Abstract: Aspects of the disclosure provide a method for detecting marks. The method includes receiving a data signal from a channel. Further, the method includes matching the data signal to a template that corresponds to a predetermined pattern transmitted over the channel to detect marks, prior to decoding the data signal into a decoded bit stream.

Abstract: Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.

Abstract: A communication receiver and a receiving method are disclosed. An analog front-end device samples a receiving signal and generates a sampled signal. A signal detector detects presence of the receiving signal according to the sampled signal. A symbol timing recovery (STR) unit determines an optimal symbol sampling point according to a zero-crossing point of the sampled signal when the receiving signal is present, and then generates a recovered symbol based on an optimally chosen sampled value according to the optimal symbol sampling point.

Abstract: A signal processing apparatus, which executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10” to any one of binary digital signals “0 and “1”, and assigning two bits of “01” to the other binary digital signal, is provide with a decoding unit which executes the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of the first bit and the second bit of the Manchester-encoded digital signal.

Abstract: A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

Abstract: There is provided an information processing device, including a preamble detection portion, a sync detection portion, a storage portion, a storage control portion, a delay time imparting portion, a bias computation portion, a half sampling portion, an adaptive equalization portion an equalization performance determination portion that compares equalization errors for each one of the sync portion candidates for which the training equalization has been performed by the adaptive equalization portion, and that sets the candidate position with the least error, and a binary determination portion that decodes the Manchester code into NRZ code by subjecting to binary determination the received signal that has been adaptively equalized by the adaptive equalization portion. The storage control portion reads the received signal from the storage portion based on information about the candidate position with the least error that has been set by the equalization performance determination portion.

Abstract: A signal processing apparatus, which executing a decoding process for a digital signal Manchester-encoded by assigning two bits of “10” to any one of binary digital signals “0 and “1”, and assigning two bits of “01” to the other binary digital signal, is provide with a decoding unit which executes the decoding process with a processing unit corresponding to a term of two bits of the Manchester-encoded digital signal so as to detect only any one of the first bit and the second bit of the Manchester-encoded digital signal.

Abstract: A decoder and related method adaptively generate a clock window. A falling edge of a horizontal synchronization signal is detected, and the time difference between an actual frame code and a predefined frame code is determined. The beginning and the end of the clock window are then adaptively determined based on the falling edge and the time difference, such that symbol timing recovery through received clock run-in signals may be performed within the generated clock window.

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: An apparatus for recovering data and a method thereof are provided. The apparatus includes a reference clock generator which generates a reference clock, and a data recovering unit which detects an edge of received data and recovers the data using a time difference between a reference point of the reference clock and the detected edge.

Abstract: A Digital Phase-Locked Loop (DPLL) has a digitally-controlled oscillator (DCO) that generates an output clock frequency determined by a digital input with most-significant-bits (MSB's) and a least-significant-bit (LSB). The LSB is generated by a Pulse-Width-Modulation (PWM) controller clocked by a control clock that is the output clock divided by C. A reference clock is compared to a feedback clock that is the output clock divided by M. The PWM controller generates M/C LSB's for each reference clock period and loads them in parallel to a parallel-to-serial shift register that serially delivers the LSBs. The pulse width is determined by a fine digital loop filter that filters phase comparison results using a fine time resolution. A coarse digital loop filter generates the MSB's from phase comparison results using a coarse time resolution. LSB waveforms are dithered by randomly selecting high-going or low-going pulses and randomly adjusting pulse widths.

Abstract: In one aspect, a wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the tr

Abstract: Methods, apparatus, and systems for generating bit-wise path equivalency information corresponding to 1T decision nodes in a soft output Viterbi algorithm (“SOVA”) decoder operating with an nT clock signal. An add, compare, select circuit (ACS) of the SOVA generates decision data for decision nodes 1T through nT responsive to each nT clock signal pulse. The decision data is applied to corresponding 1T through nT path equivalency detector circuits to generate 1T through nT path equivalency information for generation of soft output signals corresponding to the 1T through nT decision data.

Abstract: Digital data encoding and decoding method and system is provided. The data encoding includes encoding a frame signal into a bit stream, including detecting a specific bit pattern in the bit stream when the frame signal is present, generating a control signal in respect to the specific bit pattern, and encoding the bit stream into one or more marks and one or more spaces so that encoded data include a unique encoding pattern for the frame signal. The data decoding includes detecting at least one of mark and space from encoded data, recovering a bit stream from the encoded data when the at least one of mark and space is present, detecting a specific bit pattern associating with a frame signal from the encoded data when the at least one of mark and space is present, and recovering the frame signal from the encoded data.

Abstract: A galvanic isolator having a transmitting section and a receiving section is disclosed. The transmitting section includes a frame input circuit, a data encoder, and a data transmitter. The frame input circuit receives an input data frame that includes a plurality of input binary bits. The data encoder encodes the input binary bits to generate an encoded data frame that includes a sequence of encoded binary bits in which two successive encoded binary bits represent each input binary bit. The successive encoded binary bits representing a 1 are 01 or 10, and the successive encoded binary bits representing a 0 are 00 or 11. The sequences are chosen to maximize the number of transitions in the encoded data frame. A data receiver recovers the encoded data frame by examining successive pairs of encoded data bits using a clock that is reset on the edges in the encoded data frame.

Abstract: The present invention provides methods and systems for allowing a receiver in a (wireless) communication system to synchronize its timing and frequency subsystems in accordance with a received signal. In accordance with one aspect, a method is provided in which a relative time of arrival of sync values provided in a received signal are determined and used to align the receiver's reference signal(s) accordingly. Other aspects of the invention will become apparent from the detailed description of exemplary embodiments that follows.

Abstract: An ASK modulator for reducing the difference in the On/Off ratio due to the difference in the envelope frequency components without deteriorating an adjacent wave leakage power is disclosed. The ASK modulator includes a Manchester encoder that generates Manchester-encoded signals by applying Manchester encoding to an input signal sequence, a waveform shaping unit that generates band-limited encoded signals from the Manchester-encoded signals, and detects and limits minimum values of waveforms of the band-limited encoded signals to generates shaped signals, and a modulating unit that modulates carrier waves based on the shaped signals.

Abstract: A method is provided. In this method, a clock signal and an input signal are received, where the input signal is a Manchester encoded signal. A unit interval (UI) number is incremented for each UI received upon receipt of a valid UI. The UI number is compared to a plurality of threshold values after the each increment of the UI number, where each threshold value is associated with at least one of a plurality of sum values. For each threshold value, once exceeded by the UI number, its sum value is incremented for each cycle of the clock signal, and a plurality of window lengths are calculated, where each window is calculated based at least in part on at least one of the sum values at predetermined values of the UI number.

Abstract: Data message sync patterns for use in a network that utilizes Manchester (Bi-Phase) signal encoding with an embedded sync pattern. The sync pattern of the invention differs from conventional sync patterns for Manchester (Bi-Phase) type signal encoding, allowing greater deviation of the local oscillators in the communication network without increase in the communication network bandwidth.

Abstract: A method for decoding a Manchester-II encoded DISPLAYPORT compatible signal is provided. In this method, several counters are reset. A unit interval (UI) counter is incremented for each UI received upon receipt of a valid UI, and the value of the UI counter is compared to a plurality of threshold values after the UI counter is incremented. When the value of the UI counter exceeds each of the threshold values, for each clock cycle, a sum counter is incremented corresponding to the exceeded threshold value, and a plurality of window lengths are calculated, where each window is calculated based at least in part on the value of one of the sum counters at predetermined values of the UI counter.

Abstract: An approach is provided for supporting carrier synchronization in a digital broadcast and interactive system. A carrier synchronization module receives one or more signals representing a frame that includes one or more overhead fields (e.g., preamble and optional pilot blocks and one or multiple segments separated by pilot blocks). The module estimates carrier frequency and phase on a segment by segment basis and tracks frequency between segments. Carrier phase of the signal is estimated based upon the overhead field. Estimates carrier phase of random data field are determined based upon the estimated phase values from the overhead fields, and upon both the past and future data signals. Further, the frequency of the signal is estimated based upon the overhead fields and/or the random data field. The above arrangement is particularly suited to a digital satellite broadcast and interactive system.

Abstract: A wireless communication device includes an antenna configured to receive electromagnetic energy corresponding to a wireless communication signal outputted using an interrogator and to output electrical energy corresponding to the received electromagnetic energy, communication circuitry coupled with the antenna and configured to sample the electrical energy to process the wireless communication signal, synchronization circuitry coupled with the antenna and the communication circuitry and configured to generate a clock signal to control sampling of the electrical energy using the communication circuitry, wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal responsive to a plurality of transitions of the electrical energy during a first data period and wherein the synchronization circuitry is configured to generate a plurality of transitions within the clock signal during a second data period including generating at least one of the transitions indep

Abstract: A signaling method reduces bandwidth requirements and signaling delays normally associated with sending text-based signaling messages over a wireless links. An application at a transmitting endpoint generates and sends a binary-encoded signaling message, along with a binary interpreter that enables the receiving endpoint or SIP server to construct a text-based message from the binary encoded message. The binary-encoded signaling message may include references to a saved state, or to a dictionary to enable compression of the message. The signaling method can be used with any text-based signaling protocol, such as the Session Initiation Protocol, the Session Description Protocol, and the Real Time Streaming Protocol.

Abstract: A clock and data recovery circuit that tracks the frequency and phase fluctuation of serial data includes a feedback controller for monitoring tracking speed of an extraction clock with respect to the frequency and phase fluctuation of the serial data and applying feedback control to an integrator adaptively and moment to moment, thereby raising the tracking speed of the recovered clock and improving the jitter tolerance characteristic.

Abstract: The invention relates to a method and a circuit arrangement for determining the carrier frequency difference during the demodulating of received symbols (P1, P2) in the complex phase space (I, Q; R, ?) of a quadrature modulation method (QAM), wherein to determine the frequency the received symbols are compared with symbols (S1, S2) at nominal positions in the complex signal space. In order to make the determination independent of a rotation of the coordinate system of the received signals with respect to the coordinate system of the symbols, it is proposed to determine the angle (?(P1, P2)) between two received signal values (P1, P2) and compare it to possible nominal angles of the quadrature modulation method. An angle deviation between the determined angle of the received signal values and the nominal angle can be used as a direct measure of a frequency deviation (?f).

Abstract: A method and apparatus for receiving digital audio data which does not require the recovery of a clock from the data. Instead, the digital audio data is sampled at a rate greater than a clock rate of the digital audio data. Appropriate transitions in the digital audio data are detected to allow reconstruction of digital values represented by the digital audio data.

Abstract: A method and circuit are shown for decoding a Manchester encoded data input signal, wherein preamble found, data input, and recovered clock signals are received and a phase of the data input signal stored responsive thereto. A decision time signal alternates state responsive to the recovered clock signal. A switch pulse signal asserts when the decision time signal is active and the stored phase and current phase of the data signal have the same logic value, which is stored and cleared responsive to the recovered clock signal. A data output is decoded from a decision pair of phases responsive to the recovered clock, preamble found and decision time signals. The stored and current phases of the data input signal are selected to be the decision pair when neither the switch pulse signal or stored switch pulse signal are asserted and, otherwise, the stored phase and inverted stored phase are selected.

Abstract: A method and device for wireless data transmission between a base station and one or more transponders, in which electromagnetic carrier waves are emitted by the base station and symbols are transmitted from a given transponder to the base station by modulation and backscattering of the electromagnetic carrier waves, wherein a change in a modulation state takes place synchronously with synchronization markers transmitted by the base station. A change in the modulation state is carried out by a transponder with a specifiable time delay that is relative to the synchronization markers.

Abstract: A decoding process, by an electronic circuit of a diphase asynchronous frame carried by an encoded data signal and comprising L information bits followed by at least one stop bit. The process comprises a step for automatically detecting the length L in information bits of the frame so as to decode the entire frame, the length L of the frame being variable from one frame to another and such that Lmin?L?Lmax=(Lmin+k), where k is a predetermined whole number greater than or equal to one.

Abstract: A receiving device is provided. A pulse width is measured, it is selected whether a determination process is performed for a pulse width having the length of one bit in accordance with the measured value of the pulse width or a pulse width having the length of ½ bit, it is discriminated whether a current pulse edge is a pulse edge at the center of the bit or a pulse edge at the boundary between bits while considering the bit data right before the determined bit, and when it is determined that the current pulse edge is the pulse edge at the center of the bit, the bit data is determined by the rising edge or the falling edge of the pulse edge.

Abstract: Circuitry is provided in a programmable logic device incorporating clock-data recovery circuitry on I/O channels to allow the use of otherwise unused noise-reduction circuits in the I/O channels, such as decision-feedback equalization (DFE) circuits, to cancel or minimize cross-talk with other channels or other sources of cross-talk. Selectable connections are provided to allow various potential sources of cross-talk to be programmably connected to the DFE circuits instead of unused CDR output taps. When a user finalizes a user logic design, the user can determine the sources of cross-talk and the unused taps relative to a particular channel, and programmably connect the sources to the DFE circuits corresponding to those unused taps. DFE coefficients may then be adjusted to cancel or at least minimize the cross-talk. Programmable time delays can be provided to adjust for clock differentials between the cross-talk source and the particular channel under consideration.

Abstract: A MIMO receiver is provided with a preprocessor for performing QR decomposition of a channel matrix H wherein the factored reduced matrix R is used in place of H and Q*y is used in place of the received vector y in a maximum likelihood detector (“MLD”). The maximum likelihood detector might be a hard-decision MLD or a soft-decision MLD. A savings of computational complexity can be used to provide comparable results more quickly, using less circuitry, and/or requiring less consumed energy, or performance can be improved for a fixed amount of time, circuitry and/or energy. Where the MLD uses approximations, such as finite resolution calculations (fixed point or the like) or L1 Norm approximations, the reduced number of operations resulting from using the reduced matrix results in improved approximations as a result of the finite resolution operations. Other methods of reducing the channel matrix might be used for suitable and/or cumulative advantages.

Abstract: A delay section delays a detected signal by less than one bit time in the NRZ data. A subtraction section performs subtraction between a delayed signal and the detected signal, and outputs a resultant signal. A clock extraction section extracts, from crossing points of a subtracted signal, crossing points whose time interval is more than or equal to (Tb??) and less than or equal to (Tb+?) (wherein 0<??Tb/8, 0<??Tb: Tb is one bit time in the NRZ data), and outputs a synchronous signal synchronized with the extracted crossing point. A clock recovery section synchronizes a clock signal with the phase of the synchronous signal, and outputs a data clock signal. A determination section determines the polarity of the subtracted signal outputted from the subtraction section in accordance with the data clock signal, and outputs the determination result as the NRZ data.

Abstract: The invention relates to a drive control for an electric drive with a secure electrical separation of power element and control element. The aim of the invention is to reduce the number of components such as optic couplers and buffer amplifiers between the power element and a control electronics. To this end, a suitable electrical transformer (U) is inserted in a digital communication interface (K) between the control unit (R) and the control electronics (A) for the purpose of providing a secure electrical separation. To make use of a transformer (U) possible, a non-zero frequency encoding, for example a Manchester encoding, is carried out. Alternatively, an Ethernet physics can be used to provide a suitable communication interface. The transformer electrically insulates the two communication paths from each other that are provided in an Ethernet physics and preferably has little coupling capacity and a low attenuation factor.