Abstract: A method of determining an end of a transmitted frame at a receiver on a frame-based communications network. An end of frame format for the transmitted frame is provided having an end of frame plurality of symbols. A received transmitted frame is filtered using filter coefficients matched to the end of frame plurality of symbols to provide a correlation sequence low-pass filtered signal. A squared magnitude of the correlation sequence is computed. The squared magnitude of the correlation sequence is low-pass filtered to provide a low-pass filtered correlation signal. The low-pass filtered correlation signal is delayed to provide a delayed low-pass filtered correlation signal. The delayed low-pass filtered correlation signal is multiplied by a fixed predetermined threshold to provide a multiplied correlation signal. The multiplied correlation signal is compared with the low-pass filtered correlation signal to provide a match/no match comparison indicative of the possible end of a transmitted frame.

Abstract: A method for synchronizing data frames in a communication system, and in particular an apparatus and method for preventing flag emulation in a system for synchronizing data frames using flags, in which a start and an end of each data frame having a data sequence to be transmitted are indicated using a flag. The method comprises classifying the data sequence into a plurality of unit data sequences, the step of inputting the unit data sequences into a predetermined table as indices, the step of outputting output data sequences having dummy bits which are alternatively inserted from the table in correspondence to the indices, and the step of attaching the flags to front and rear ends of the each data frame, respectively.

Abstract: A method of communication between a master unit and a slave unit is of the type including the transmission of messages comprising a useful information word, as well as one or more service bits. The messages include two bits to encode the end-of-transmission information. The value of these bits provides information on the nature of the useful information transmitted to thereby improve the integrity of the communications.

Abstract: A proximity IC card (PICC) which relates to and provides a carrier synchronization type demodulator, which is able to stably receive a PSK signal from a PICC and is enhanced in noise immunity, and which is realized at a low cost and in such a way as to have a small size. The carrier synchronization type demodulator is adapted to receive and demodulate PSK-modulated subcarrier signals to be synchronized with and superposed onto a sent carrier signal.

Abstract: A decoder for motion-picture-experts group (MPEG-4) video detects start codes at the beginning of video object planes (VOP) and resync markers at the start of each video packet (VP) in the VOP. When an error occurs in the bitstream, a parser searched for a next start code or resync marker to find the start of the next video packet. A partial match of the unique start-code bit sequence signals a fuzzy match, allowing the VOP header and data to be decoded even when bit errors occur in the VOP start code. A fuzzy match of the shorter resync marker can also be enabled. Fuzzy matching of VOP start codes and resync markers allows for faster recovery from corrupted bitstreams such as those transmitted over wireless networks.

Abstract: A first counter measures the span of the start bit of a first character of an AT command transmitted from a DTE based on instructions from an MPU. A decoder receives a measurement result of the first counter, outputs frequency-dividing data for producing a clock for sampling the first character, and also outputs, when the rate of the start bit is more than a preset value, a flag indicating this matter. A second counter selects, in accordance with whether or not the flag has been set, the frequency-dividing data from either the decoder or the MPU, and produces the sampling clock. A shift register receives data subsequent to the start bit of the first character based on the sampling clock from the second register, holds the received data, which data is then read by the MPU.

Abstract: A method of transmitting information over POTS wiring includes transmitting a first delimiter signal, in the form of a multi-cycle waveform having a frequency of approximately 7.5 MHz, over the POTS wiring. A second delimiter signal, also comprising a multi-cycle waveform, is then later propagated over the POTS wiring. The time duration between the respective propagations of the first and second delimiter signals defines a symbol, which encodes information. The time duration is also such that reflections on the carrier medium resulting from the propagation of the first delimiter signal decay to a predetermined level prior to propagation of the second delimiter signal.

Abstract: Carrier frequency and frames are synchronized in bursty data transmissions over unknown channels that cause inter-symbol interference. The synchronization procedure comprises two stages. The first stage performs a time-domain processing of samples to exploit a periodic signal repetition and to extract the coarse timing, the frequency offset and also to resolve frequency ambiguities. The second stage estimates the fine time offset of a received modulation signal. A coarse estimate of a frame start position of a received sequence of desired data samples may be improved by using the coarse timing estimate to generate frequency-domain received samples. A frequency-domain correlation is then determined between the frequency-domain received samples and noiseless samples. When using a fixed number of training samples, a “sandwich” preamble (“sandamble”) is utilized to achieve greater efficiency than a conventional repetition preamble.

Abstract: Disclosed is a carrier sense (CS) apparatus for data communication. The carrier sense apparatus for data communication detects a start time point and an end time point of a reception frame using a power threshold value and a time threshold value of a preset signal to recognize a length of the reception frame at a modem receiver for data communication. The apparatus includes a power converter for converting a voltage value of an input signal into a power value; a power accumulator for accumulating the power value for a prescribed window interval; a power threshold comparator for comparing an accumulated power value generated from the power accumulator with a predetermined power threshold value, and generating the result value; and a time threshold comparator for counting a predetermined time for which the result value generated from the power threshold comparator is continuously maintained, and determining whether the counted time exceeds a predetermined time threshold value.

Abstract: The invention relates to a circuit arrangement for a receiver for receiving bursts of a non-continuous signal, with a device for tuning to the current parameters of the signal required for evaluating a burst, in which the device for tuning is controlled in such a way that the parameters achieved at the end of a burst are extrapolated to the start of the next burst and used to evaluate it and as the starting point for further tuning, and also a transceiver for subscriber-side connection to a local wireless access network for the worldwide telecommunications network, the receiving part of which contains a circuit arrangement of this kind.

Abstract: A receiver for receiving synchronized digital transmissions organized in frames, each frame having a frame start, has a clock for generating pulses at time intervals with respect to a time reference and a counter for generating a count of the time intervals with respect to the time reference. A/D converters sample the digital transmission using the pulses from the clock. A cyclic prefix correlator detects the frame start during a count corresponding to an A/D sample. This count is indicative of the time interval during which the frame start was detected with respect to the reference. A memory is provided for storing a plurality (typically 36) counts indicative of the time interval during which the frame start was detected. A pointer is generated from the counts stored in memory. The pointer is indicative of a projected time interval during which a future frame start is expected to arrive.

Abstract: A method and apparatus for determining the appropriate timing interval for each bit or data symbol in serial data communications. A sending device transmits a predetermined bit sequence, such as a binary pattern corresponding to one byte, either on its own initiative or in response to an action of a receiving device. A microprocessor in the receiving device measures a calibration time interval between the leading edge of a start bit and a subsequent marker transition, either between subsequent data bits or between the final data bit and the stop bit. This measured interval may be mathematically converted to units useful to calibrate a function or device that conducts input/output operations. Optionally, the process may be repeated periodically to compensate for clock rate drift. This invention may be used for autobaud data rate detection, or matching the actual data rate of a remote serial device, and permits accurate communications without precision timing references.

Abstract: An improved method and apparatus for decoding serial data uses a bit-wise synchronization technique in which a single bi-directional counter integrates the value of each successive bit to decode the bit state. The counter is sized relative to the receiver module oscillator frequency and the minimum data transmission speed to prevent overflow under worst case conditions, and the count is reset to one-half the maximum count at the beginning of each bit. During the bit period, oscillator clock pulses respectively increase or decrease the count when the bit value is above or below a threshold, and the bit value is determined in accordance with the most significant bit of the counter at the end of the respective bit period. Only a single counter is used to decode the data, and the data is substantially insensitive to noise because filtering can be used to reliably establish the state boundaries of the data bits.

Abstract: A communication apparatus according to the present invention detects the trailing edge of the received data and, with the detection of the trailing edge the apparatus, acknowledges the reception of the start bit in the received data. The bit level of the start bit is monitored to examine whether or not the bit level is at a predetermined bit level. If any change is detected, a signal indicating occurrence of a start-bit-detection error is output to the outside.

Abstract: Methods and apparatus for feature recognition time shift correlation are presented. An exemplary method includes the step of identifying a feature in an input data stream. A starting time associated with the identified feature relative to a boundary of the input data stream is stored. A time interval until the identified feature is next repeated in the input data stream is then measured. Next, the measured time interval is compared to each of a set of valid interval values for the identified feature. A difference is then calculated between the stored starting time and a starting time associated with the identified feature relative to a boundary of a reference data sequence when the measured time interval matches one of the valid interval values. The calculated difference determines an amount that the input data stream must be time-shifted to achieve correlation with the reference data sequence.

Abstract: A system and method for transferring a data stream between devices having different clock domains. The method initiates a serial data stream between a transmitter and a receiver. The transmitter operates according to a first clock having a first clock rate, and the receiver operates according to a second clock having a second clock rate. A ratio between the second clock rate and the first clock rate is an integer number greater than or equal to one. A first state is provided over a serial line between the transmitter and the receiver One or more start bits are provided over the serial line. The start bits indicate a second state different from the first state. One or more ratio bits are provided over the serial line after the start bit. The ratio bits indicate the ratio between the second clock rate and the first clock rate. The start bits are received. Using a transition between the first state and the second state evident in receiving each of the start bits, the ratio bits are received.

Abstract: A method of acquiring a communications signal is provided. The method includes the steps of storing a forward chirp sync segment (106) of an auto-correlating forward chirp sync (102) and storing a reverse chirp sync segment (108) of a symmetric auto-correlating reverse chirp sync (104). A header comprising of either a forward chirp sync FCS (102) or a reverse chirp sync RCS (104), a predetermined number of data blocks comprising a data frame (308), and the symmetric auto-correlating trailer is received. The header, the data blocks, and the symmetric trailer are susceptible to frequency error. The method correlates the FCS segment (106) with the auto-correlating FCS (102) to provide a FCS correlation signal (312) and correlates the RCS segment (104) with the auto-correlating RCS (108) to provide a RCS correlation signal (314). The method determines the frequency error, symbol timing, and frame timing based upon the FCS correlation signal (312) and the RCS correlation signal (314).

Abstract: When a sync pattern in a frame of a bit stream is detected to synchronize a data processing apparatus with the bit stream, data patterns containing a pattern identical to the sync pattern are often erroneously detected as the sync pattern. In order to overcome such problem, an apparatus for detecting data in a bit stream is provided. The bit stream contains a sequence of frames, and each frame has a predetermined number of bits and comprises a sync pattern and a data portion. The apparatus contains a detecting circuit, a counting circuit, and a synchronization signal generating circuit. The detecting circuit detects a first data pattern in the bit stream that equals the sync pattern and detects a second data pattern in the bit stream that equals the sync pattern. The counting circuit begins counting bits in the bit stream to generate a count value when the first data pattern is detected by the detection circuit.

Abstract: A low jitter method for extracting clock or data from a serial digital bitstream generates from a digital decoder a window signal from the serial digital bitstream by sampling the serial digital bitstream with a sample clock signal. The window signal envelops a specified transition of the serial digital bitstream, and is used as a gate input to an AND circuit to extract the clock signal or desired data from the bitstream without introducing jitter. The clock signal may then be used to clock out data previously extracted by the digital decoder.

Abstract: The speed of asynchronous serial communications is detected by determining a duration of a data bit within an asynchronous data stream. The duration of the data bit is used to generate a clock frequency. The clock frequency is used to clock data from the asynchronous data stream into a register. The clocked data is processed according to an error indication.

Abstract: A data synchronization method and circuit are provided. A data synchronization circuit (28) includes a header timer (40), a timeout counter (44), a compare circuit (46), and a synchronization field register (48) for use in a read channel (10). During a read operation in the read channel (10), the data synchronization circuit (28) searches for the presence of a synchronization field in a read signal indicating that user data will be provided next. The search occurs over a predefined period of time. The header timer (40) enables a header timer signal for a first predefined period of time. The timeout counter (44) receives the header timer signal and enables a timeout counter signal for a second predefined period of time after the first predefined period of time expires. The compare circuit (46) compares the read signal to the known value or synchronization field stored in the synchronization field register (48).

Abstract: There is disclosed a bit sync search and frame sync search system operative with a digital data signal as transmitted by a digital radio transmitter. The bit search is implemented by detecting a predetermined phasing signal which is incorporated in the digital signal and which has a repetitive bit pattern of ones and zeroes. The phasing signal is first detected by providing an in-phase and quadrature component signal and correlating those signals to provide an output signal indicative of the bit pattern in the phasing signal. After the phasing signal has been provided and an oscillator associated with a receiving apparatus is compensated according to the detected phasing signal, a tracking mode is entered, whereby a frame signal is captured and the system generates histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling portion of a received bit.

Abstract: A system clock of a radio telephone is adjusted in relation to an associated transmitter/receiver station system clock by detecting a predetermined part (SYNC word) which occurs periodically in a digital signal. A clock signal having pulses synchronous with the system clock signal of the radio telephone is formed. The clock pulses in the clock signal are counted between the detection of two predetermined parts in the digital signal, and the system clock is corrected in response to the number of pulses between the detection of said two predetermined parts in the digital signal.

Abstract: There is disclosed a bit sync search and frame sync search system operative with a digital data signal as transmitted by a digital radio transmitter. The bit search is implemented by detecting a predetermined phasing signal which is incorporated in the digital signal and which has a repetitive bit pattern of ones and zeroes. The phasing signal is first detected by providing 94 in-phase and quadrature component signals and correlating those signals to provide an output signal indicative of the bit pattern in the phasing signal. After the phasing signal has been provided and an oscillator associated with a receiving apparatus is compensated according to the detected phasing signal, a tracking mode is entered, whereby a frame signal is captured and the system generates histograms of data bit transitions for producing an error signal indicative of the difference of the transmitted clock rate and the sampling portion of a received bit.

Abstract: A data transmission unit having a clock generating circuit for generating a continuous transfer clock signal which is always output from the data transmission unit regardless of presence or absence of transmission and reception; a data converter for converting parallel data to serial data; and a data transfer circuit for transferring the serial data in synchronism with the transfer clock signal. It can achieve the transmission of the serial data at high speed and with high reliability.

Abstract: A method is disclosed for extracting data words from a binary serial bit stream having a fixed bit rate and consisting of fixed length words of n bits each, where n is an integer, each word is preceded by a start bit and followed by one or more stop bits. First a predetermined identifiable transition is detected in said bit stream preceding each data word. A clock signal (DCLK) consisting of n clock pulses is generated in response to each detection of the predetermined transition in coincidence with the bits the data word following the predetermined transition. A data ready signal (DR) is generated after the passage of n bits to delineate the word boundary, and the data words are extracted from the bit stream using the thus generated clock pulses and the data ready signal.

Abstract: A data reception control device for receiving a group of commands transmitted by a start-stop transmission method including a first type of commands of which data transmission rates are detectable and a second type of commands of which data transmission rates are undetectable.

Abstract: A clock circuit for providing an integrated circuit with a high accuracy, crystal oscillator clock which interfaces to an "off-chip" crystal to provide a high accuracy clock signal while an internal, low power oscillator provides a low power clock source. Either clock may be selected to drive a programmable processor under program control. When high accuracy and stability are required, the crystal oscillator may be chosen as the processor clock, and when lower power is desired, the low power oscillator may be chosen as the processor clock while the high accuracy clock is disabled. The high accuracy oscillator is used to clock a first timer circuit, while the low power oscillator is used to clock a second timer circuit. The second timer circuit output, in turn, is synchronized to the processor clock so that the programmable processor can utilize the second timer circuit even when the processor clock is asynchronous to the second timer circuit.

Abstract: A method for common transmission of digital source and control data between data sources and sinks being connected by data lines, includes transmitting the source and control data in a format prescribing a clocked sequence of individual bit groups of equal length. In each bit group, there are one or more and in particular two control bits, which are used for the transmission of control signals. One control signal is assigned bitwise to the control bits of successive bit groups. A starting identification code which is identical for all of the control signals is provided at the beginning of each control signal.

Abstract: The invention relates to a method for detecting the beginning of time messages in the signal received from a time-signal transmitter. The signal of the time-signal transmitter consists of a series of blanking intervals on a carrier signal in the seconds clock cycle in which blanking intervals of different length cause different information units to be transmitted (ZERO pulse, ONE pulse, frame pulse). A time message, comprising the information units transmitted over a period of one minute, contains the actual time information in coded form. The time message has areas/sectors with defined, constant information units and areas/sectors with variable contents that code the time information. A reference message is stored in a first area of memory that contains the defined, constant information units that are located in fixed areas/sectors. A number of successive information units corresponding to the length of a time message are stored in a second area of memory.

Abstract: A system for monitoring and controlling an area comprising a controller for controlling system operational functions; at least one remote control transmitter for transmitting at least one system command to said controller in a code word having a fixed word and a hopping word therein; the fixed word having an identification code for selective control of the controller, the identification code programmed therein, and a channel code for issuing high and low security commands to the controller; a hopping algorithm for modifying the hopping code of the transmitter n-times in response to n-times activation of said transmitter and for modifying the hopping word m-times within the controller upon receipt of the code word m-times from said transmitter; and, a bypass mode for bypassing the code hopping algorithm and for controlling system functions in response to the controller receiving the low security command.

Abstract: A data receiving unit includes a data receiving circuit for receiving, through a transmission path, transmission data which has been encoded into a predetermined transmission code by using a predetermined transmission clock signal and includes a reference pulse having a pulse width corresponding to a period of the transmission clock signal, a clock for generating a received clock signal in synchronization with the transmission data, and a data decoding circuit for decoding the transmission data received by the data receiving circuit using the received clock signal generated by the clock, where the clock includes an oscillator generating at least a reference clock having a period which is shorter than that of the transmission clock signal, a counter circuit counting an interval between points of change of the transmission data received by the data receiving circuit according to the reference clock signal, a reference pulse detector circuit for detecting the reference pulse on the basis of a count value from th

Abstract: A method of processing a received signal in a wireless communication system (20), the method comprising the steps of detecting a first digital signal at a first receiver (26), measuring timing parameters of the first digital signal, and sending data associated with the timing parameters to a second receiver (28).

Abstract: A spread spectrum communication apparatus receives a preamble signal or a postamble signal as a pilot signal, and applies a correlative demodulation by using a single spread signal to the pilot signal, and a correlative output obtained after the correlative demodulation is compared to a reference value. If the correlative output is equal to or greater than the reference value, then it is recognized as a preamble or postamble signal. In accordance with a trailing edge of the preamble signal or a leading edge of the postamble signal, a start point or an end point of information transmission can be recognized, respectively, in a lower level of a communication system without using a unique word in a data stream, thereby reducing overhead of an upper level protocol and improving data transmission efficiency.

Abstract: The invention provides a system for measuring the synchronization of SONET signals. The invention counts the bits in an STS-1 signal starting at a reference time point and ending when the framing bytes A1 and A2 are detected. The counts are repeated every other SONET frame. The system can be applied to multiple SONET signals arriving at a location. The system can employ a CPU to analyze the bit counts to determine if the timing of a SONET signal begins to experience wander.

Abstract: The object of the present invention is to provide a data transmission system, wherein even when more than two among a plurality of stations interconnected by one common transmission line try to communicate mutually by a start-stop transmission PWM mode, if the phases within a bit in the data of the own station and a corresponding bit of the data on the transmission line which has been received through a plurality of own station are compared and they coincide with each other as the result thereof, then the own station continues transmitting the data, while otherwise it comes to stop transmitting, whereby even if there is a difference between the clock frequency of the own station and that of another station, the phases in the corresponding bits of the two different data can be smoothly compared.

Abstract: A system (10) for transmitting a synchronous stream of data is set forth. The system (10) includes a universal asynchronous transmitter/receiver (30) includes a circuit for asynchronously transmitting a data character; a timing circuit for generating a signal (255, 260) upon completion of the asynchronous transmission of the data character; and an output line (140, 145) controllable to go to a data state independent of the data states of the bits of the data character. The system further includes a central processing circuit (15, 20, 25) that is responsive to the timing circuit of the UART (30). The central processing circuit (15, 20, 25) controls the output line (140, 145) of the UART (30) to go to a series of data states corresponding to individual bits of the synchronous data stream. The period of the individual bits corresponds to the signal generated by the timing circuit.

Abstract: A serial data receiving device comprises a first memory means for storing serial data while shifting the data bit by bit whenever receiving each one bit of the data and converting the serial data into parallel data when all the bits constituting the serial data are stored; a first detecting means for detecting the storage of all the bits constituting the serial data in the first memory means, a second memory means for storing a signal allowing the serial data to be received in accordance with the detection result by the first detecting means, and a first control means for controlling the reception of the serial data (outputting a hand-shake signal or transfer clock, for example) in accordance with the stored contents in the second memory means. A serial data transfer apparatus is equipped with the serial data receiving device, wherein the receiving device controls the transfer of the serial data.

Abstract: A start code detecting apparatus for detecting a start code which indicates the start position of each layer from the bit stream of a compressed image according to the MPEG-standard is provided. The start code detecting apparatus includes two registers, a barrel shifter, a start code detector, a state machine, a code length generator and an accumulator. The start code detecting apparatus adopts the barrel shifter and the start code detector, so that the start code designating the start position of each layer can be effectively detected from the compressed bit stream.

Abstract: A high bit rate start code monitoring, searching and detecting circuit includes a Least Significant Bit (LSB) zero counter, a Most Significant Bit (MSB) zero counter, first and second adders, first and second registers, a comparator, a start code detector, and a start code decoder. The LSB zero counter counts the number of consecutive zero bits from the least significant bit while the MSB zero counter counts the number of consecutive zero bits starting with the most significant bit. A LSB zero count output is added with a prescribed value by the first adder to arrive at a Zero.sub.-- Bits.sub.-- Shifted.sub.-- Out (ZBSO) value, which is saved in the first register. A MSB zero count output is added with the stored value of the ZBSO value during the subsequent clock cycle. If the summed (S) value is greater than or equal to 23, then the start code detector is enabled. The start code detector can detect parts of a start code contained in two separate bitstreams or a start code embedded in a bitstream.

Abstract: A serial transfer system for performing serial data transfer between transmission and reception stages which have phase locked loops for generating reference clock signals. The serial transfer system has a transmission circuit and a reception circuit. The a transmission circuit converts parallel data from the transmission stage into a serial data signal at the same time that it appends a data marker to the parallel data in response to the reference clock signals from the phase locked loop of the transmission stage and transmits the converted serial data signal through a coaxial cable. The reception circuit receives the serial data signal from the transmission circuit through the coaxial cable, converts the received serial data signal into the original parallel data using its appended data marker and the reference clock from the phase locked loop of the reception stage and outputs the converted parallel data to the reception stage.

Abstract: A data receiving device, applicable to a system which receives data sequentially transmitted thereto in a non-periodical manner under control of a host CPU, is configured by a receiving circuit, a counter circuit, a memory circuit and register circuits. A plurality of input data are sequentially supplied to the receiving circuit, so that the receiving circuit produces a strobe signal when receiving each input data. The counter circuit measures a receiving interval of time between moments of receiving two input data which are consecutively received by the receiving circuit. The memory circuit has specific storage capacity for storing predetermined sets of main data and time data, wherein the main data are extracted from the receiving circuit and the time data correspond to the receiving interval of time. Herein, the main data are stored with being related to the time data.

Abstract: A data transfer apparatus includes a computer-side input and output unit for transmitting a data signal which is periodically updated, and a printer-side input and output unit for receiving the data signal transmitted from the computer-side input and output unit and detecting the logic level of the data signal. Particularly, this data transfer apparatus further includes a state transition time measuring circuit, a computer-side CPU, and a printer-side CPU cooperated to transmit a transition test data signal from the computer-side input and output unit in a tuning mode, measure the transition time of the transition test data signal received by the printer-side input and output unit, and adjust transfer parameters which define the transmission rate of the data signal to be transmitted from the computer-side input and output unit and a timing for detecting the logic level of the data signal, on the basis of a result of measurement.

Abstract: A method to encode and to decode frames of data used in synchronous protocols, including HDLC and SDLC. The invention operates on blocks of data, such as data bytes or data words, in a parallel rather than a bit serial manner. The invention compares an aligned block of data with reference bit sequences for flag or abort signal detection, for zero detection, for zero deletion, for detection of consecutive one bits, and for zero insertion following a stream of consecutive one bits, for encoding and decoding according to various protocols. The invention also maintains proper data alignment following such zero insertions or deletions, and provides encoding and decoding under both data overrun and data underrun conditions.

Abstract: An asynchronous serial data receiving device receives serial data, containing main data of bits sandwiched between a start bit and a stop bit, which are transmitted thereto in an asynchronous manner. In the device, the serial data are temporarily stored in a shift register circuit in response to high-speed clocks whose speed is higher than transmission rate of the serial data. A counter circuit counts number of the high-speed clocks. Every time a change of level is detected in the serial data, counting operation of the counter circuit is reset so that the counter circuit re-starts counting from its initial number. The change of level is detected responsive to the serial data or noise. Existence of the start bit is acknowledged on the basis of a fact that the counter circuit continues counting for a window time, without being reset, in a duration of the start bit. Herein, the window time is less than a half of the duration of the start bit.

Abstract: A receiver device is provided with a low latency recovery apparatus for recovering serially transmitted digital data. The receiver device operates asynchronously in respect to a transmitting device. The low latency recovery apparatus synchronizes the receiver device in one clock time to support throughput of high speed transmission messages received from interconnection networks or interface cables. A metastability proof latch is provided. A synchronization method provides individual alignment for each incoming message. There is instantaneous response to back-to-back messages from different sources. Synchronization is accomplished in the receiving device by implementing a clocking system capable of generating N phase-shifted clocks all operating at the same frequency as the incoming data. The N clocks are shifted an approximately equal amount in relation to each other.

Abstract: A glitch free clock switching circuit which produces a predictable and specifiable number of clock pulses to the system elements when switching between clock signals, even during full operation. In addition, the present invention has the capability of only switching between clocks at times that coincides with every Nth clock cycle. This is important in various types of computers systems including high reliability systems because it results in a clock switching circuit which can provide a clock signal which remains consistent throughout the computer system even in light of multiple hardware failures.

Abstract: A variable-length decoder variable-length-decodes a received variable-length-encoded data. The variable-length-encoded data is bit-stuffed in each data block to create data portions with a predetermined number of bits. Frame start codes representing a start of each frame and mass of macroblock start codes distinguishing between a plurality of masses of macroblocks are inserted into the data. Synchronization of data between frames and masses of macroblocks are accomplished via: a first-in-first-out (FIFO) memory which stores encoded data; a decoder which variable-length-decodes the input data in response to a control signal and generates an end-of-block (EOB) error signal when an EOB is not found; a decoding interface which interfaces between the decoder and a timing controller; and a timing controller which synchronizes decoding by use of start and initialization signals.

Abstract: The invention relates to a device for recovering a symbol timing for the decoding of received signals formed by code-modulation symbols transmitted in an orthogonal frequency-division multiplexing mode (OFDM). The signals are formatted in symbol blocks of which each block presents redundant information. The invention comprises means for delaying the symbol blocks and for subtracting from a symbol block the delayed symbol block corresponding thereto. In this manner a difference signal e(t) is obtained which is used for controlling a loop formed by a local oscillator operating at the clock frequency, a frequency divider and a phase comparator.

Abstract: A "zero phase start" optimization circuit for a Partial Response, Maximum Likelihood ("PRML") data channel dynamically determines a more optimal starting phase for the timing recovery process in a synchronous communication or storage system. The disclosed circuit includes a quantizer, a summing junction, either an absolute value or squaring function, and an integrator. A firmware based optimization routine causes a timing control loop to go through a series of timing acquisition modes, each time starting a clocking oscillator at different phase. The optimization circuit calculates the mean squared error between actual and expected sample values from a known frequency preamble pattern for each timing acquisition. The minimum MSE value corresponds to a more optimal starting phase for the timing control loop oscillator.