Abstract: A system (10) for transmitting a synchronous stream of data is set forth. The system (10) includes a universal asynchronous transmitter/receiver (30) includes a circuit for asynchronously transmitting a data character; a timing circuit for generating a signal (255, 260) upon completion of the asynchronous transmission of the data character; and an output line (140, 145) controllable to go to a data state independent of the data states of the bits of the data character. The system further includes a central processing circuit (15, 20, 25) that is responsive to the timing circuit of the UART (30). The central processing circuit (15, 20, 25) controls the output line (140, 145) of the UART (30) to go to a series of data states corresponding to individual bits of the synchronous data stream. The period of the individual bits corresponds to the signal generated by the timing circuit.

Abstract: In a demodulation device for processing a received data including a predetermined pattern, at each m bits, a bit pattern including the predetermined pattern is set, and the received data is shifted by one bit each time. A result of the shift is compared with the set bit pattern each time shifting is performed. The result of the shift is output in the case where coincidence is obtained. In the case where coincidence cannot be obtained, comparison is continued.

Abstract: A data receiving device, applicable to a system which receives data sequentially transmitted thereto in a non-periodical manner under control of a host CPU, is configured by a receiving circuit, a counter circuit, a memory circuit and register circuits. A plurality of input data are sequentially supplied to the receiving circuit, so that the receiving circuit produces a strobe signal when receiving each input data. The counter circuit measures a receiving interval of time between moments of receiving two input data which are consecutively received by the receiving circuit. The memory circuit has specific storage capacity for storing predetermined sets of main data and time data, wherein the main data are extracted from the receiving circuit and the time data correspond to the receiving interval of time. Herein, the main data are stored with being related to the time data.

Abstract: An inter-repeater backplane that may operate in either a synchronous or asynchronous mode for data transmission. The inter-repeater backplane includes a bus of electrical signal conductors coupled between repeaters for communicating electrical signals and data transmission mode detector for determining whether to transmit data synchronously or asynchronously. Data is recovered from a received data packet and is reframed for transmission across the inter-repeater backplane. According to which mode of data transmission is selected, the data is then retimed and transmitted across the backplane. In the synchronous mode of data transmission, the data is synchronized with the system clock. When the asynchronous mode of data transmission is selected, the data is transmitted asynchronously with respect to the system clock. In the asynchronous mode, the recovered data is timed with a clock signal associated with the transmitting repeater.

Abstract: A system and method for the transmission and recovery of asynchronous data. For instantaneous synchronization, the receiver is equipped with a high frequency timing base which has a far higher frequency than either the data-generating or transmitting rate. The receiver clock is instantly synchronized upon detection of the first transition of the incoming data packet. Data packet verification can be conducted and data processed with minimal loss of data.

Abstract: A number of detection circuits, one for each source of control signal set inputs, and a high speed resolution circuit, are provided for resolving multiple control signal inputs into a single stable, predictable, and useful output signal. The detection circuits detect active control signals in the various control signal set inputs, and generate detected signals. The high speed state resolution circuit generates an output signal, conditionally changing the output state based on the detected signals and the current state being output. When deciding whether to change the output state, the high speed resolution circuit considers only the detected signals applicable to the current output state and responds accordingly, ignoring all other detected signals that are not applicable. The detection circuits and the resolution circuit are coordinated in timings, ensuring proper resolution.

Abstract: A number of detection circuits, one for each source of control signal set inputs, and a high speed resolution circuit, are provided for resolving multiple control signal inputs into a single stable, predictable, and useful output signal. The detection circuits detect active control signals in the various control signal set inputs, and generate detected signals. The high speed state resolution circuit generates an output signal, conditionally changing the output state based on the detected signals and the current state being output. When deciding whether to change the output state, the high speed resolution circuit considers only the detected signals applicable to the current output state and responds accordingly, ignoring all other detected signals that are not applicable. The detection circuits and the resolution circuit are coordinated in timings, ensuring proper resolution.