Abstract: An electronic system having a spread spectrum clock is disclosed. A spread spectrum clock source creates and transmits both a spread spectrum clock signal and a modulation signal. A spread spectrum clock generator uses a modulation waveform on the modulation signal to frequency modulate a reference oscillator frequency. A logic unit comprises a Phase Locked Loop that receives the spread spectrum clock signal and the modulation signal and generates a logic unit clock signal.

Abstract: A method, system, and computer-readable media are provided for transmitting wireless data across a coaxial cable. In one aspect, a set of computer-readable media provides a method that includes receiving a request from a mobile device for data and transmitting the data across a coaxial cable to a cable modem. The method further includes sending the data to the mobile device through a base station, wherein the base station communicates with the cable modem in order to receive the data.

Abstract: A subcarrier allocation method for use by a transmitter, the transmitter being configured to, when transmitting first and second data streams, allocate pilot symbols for the first and second data streams to subcarriers, such that a first plurality of subcarriers carry the pilot symbols for the first data stream and a second plurality of subcarriers carry the pilot symbols for the second data stream. The method includes allocating, when the transmitter transmits the first data stream but does not transmit the second data stream, the second plurality of subcarriers to carry no formation or information relating to the first data stream.

Abstract: Methods and systems for vector combining power amplification are disclosed herein. In one embodiment, a plurality of signals are individually amplified, then summed to form a desired time-varying complex envelope signal. Phase and/or frequency characteristics of one or more of the signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time-varying complex envelope signal. In another embodiment, a time-varying complex envelope signal is decomposed into a plurality of constant envelope constituent signals. The constituent signals are amplified equally or substantially equally, and then summed to construct an amplified version of the original time-varying envelope signal. Embodiments also perform frequency up-conversion.

Abstract: An adaptive receiver comprises a receiver module that receives an orthogonal frequency division multiplexing (OFDM) signal. An operating parameters module monitors at least one operating parameter of the receiver module and generates a select signal based the at least one operating parameter. An estimator module selects between first and second algorithms based on the select signal and selectively estimates a carrier frequency offset (CFO) of the OFDM signal using the one of the first and second algorithms. Alternately, an estimator module adjusts algorithm operating parameters of a first algorithm based on the select signal and selectively estimates a carrier frequency offset (CFO) of the OFDM signal using the selected algorithm operating parameters of the first algorithm.

Abstract: The present invention relates to a method for interpolating, for the purpose of measurement of lengths and/or angles, at least two position-dependent, periodic analog signals that are phase-shifted with respect to each other and that are generated by scanning a measuring scale. According to the inventive method, the analog signals are converted to a digital data stream using a sigma-delta modulator, the data streams are combined with correctional factors and then with each other to generate a string of results, and said string of results is used to generate new correctional values by the use of a quality criterion to be satisfied for interpolation and also to generate the output signals of interpolation. The values (d) of the string of results are accumulated over a specified time interval in order to generate the correctional values (k1, k2) and the output signals (w).

Abstract: A method includes maintaining temporally parallel DSL data communication sessions with DSL modems of a group via a set of lines. The method includes, in response to substantially stopping to receive DSL communications from one of the DSL modems via one of the lines, transmitting a substantially reduced average power to the one of the lines and monitoring the one of the lines to determine whether DSL communications have restarted being received from the one of the DSL modems. The method also includes resuming the maintaining of the temporally parallel DSL communication sessions in response to the monitoring determining that DSL communications have restarted being received from the one of the DSL modems.

Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.

Abstract: A system and method for power control in a wireless transmitter. A power control loop includes a feed forward unit coupled to a data source, the feed forward unit processes a signal for transmission, a feedback unit coupled to the feed forward unit, the feedback unit generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit, a closed loop power control unit coupled to the feedback unit and to the feed forward unit, the closed loop power control unit generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source or software instructions, and a ramp path power control unit coupled to the data source, the ramp path power control unit generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: A data receiving apparatus and method includes a current-voltage conversion block, which receives a current-type transmit signal including data and a clock signal inserted into the data at a different level from the data, and then converts the received signal into at least one first voltage and at least one second voltage having a different level from the first voltage, and a comparison block, which makes a comparison between the first and second voltages, and then outputs the received signal as one of the data and the clock signal based on a result of the comparison. The data receiving apparatus can easily recover a clock signal while exhibiting better characteristics during the recovery of the clock signal because it is insensitive to a variation in reference voltage and a variation in current at the transmitting state of the timing controller, which are caused by a process variation.

Abstract: A programmable logic device can be configured as a fractional rate resampling filter capable of performing downsampling prior to upsampling without modifying the overall filter response. Input data may be received at a first sample rate and may be downsampled to generate downsampled data. Portions of the downsampled data may be respectively output to different filtering paths. Each filtering path may include a cluster of filter components that corresponds to different subfilters of the overall filter response and may be operable to receive and process the different portions of the downsampled data. Outputs of each cluster may be combined to generate output data at a second sample rate. The resampling filter structure can reduce the number of multiplier circuits used by allowing time-division multiplexing among different filter components.

Abstract: According to the invention, an information output, e.g. a voice output, video information output, or a simultaneous output of video and audio information, which is to be transmitted via a packet-oriented network, is generation by means of pre-coded information output components. Said pre-coded information output components are present in a memory system and are retrieved as part of the processing of a request for the output of information by an information output system. Similarly, generation rules for the information output can be stored in the memory system and accessed by the information output system in order to generate the information output. According to one embodiment, information output components or generation rules are created in an information output configuration system and are subsequently made available in the memory system. The invention optimizes the use of resources for information-output services.

Abstract: A transmitting apparatus and method transmits different modulated signals from a plurality of antennas, and employs a configuration that includes a modulation section that obtains a modulated signal by performing signal point mapping of transmit bits using a signal point arrangement that is divided into a plurality of signal point sets on the IQ plane, whereby the minimum distance between signal points within a signal point set is smaller than the minimum signal point distance between signal point sets; and an antenna that transmits a modulated signal obtained by the modulation section. A signal point generating apparatus generates a first and second symbols to be transmitted by first and second antennas, respectively.

Abstract: The present invention includes a time-division-multiple-access (TDMA) communication system having a base station and at least one mobile station, each transmitting and receiving an analog radio-frequency signal carrying digitally coded speech. The speech is encoded using a vocoder which samples a voice signal at variable encoding rates. During periods when the radio-frequency channel is experiencing high levels of channel interference, the encoded voice channel having a lower encoding rate is chosen. This low-rate encoded voice is combined with the high degree of channel coding necessary to ensure reliable transmission. When the radio-frequency channel is experiencing low levels of channel interference, less channel coding is necessary and the vocoder having a higher encoding rate is used. The high-rate encoded voice is combined with the lower degree of channel coding necessary to ensure reliable transmission.

Abstract: A low power communication encoding method is provided. A first piece of encoded information and a second piece of encoded information are generated based on a comparison of a current transmission record and a previous transmission record. Then transmission data is selected based on which of the first and second pieces of encoded information will result in transmitting a fewer number of logical lows. Ultimately, the transmission data is transmitted on an open drain data line.

Abstract: Polar and quadrature modulator for receiving a baseband processed voice signal and for processing, modulating and transmitting voice signal. Voice signal processor and modulator for processing voice signal into Orthogonal Frequency Division Multiplexed (OFDM) or Orthogonal Frequency Division Multiple Access (OFDMA) signal. A location finding signal receiver, demodulator and processor for receiving, demodulating and processing a location finder signal into demodulated processed location finder signal. Location finder signal receiver receiving signal from two or more satellite and two or more ground based transmitters. Diversity receivers for signal reception from cellular and from Wireless Local Area Network (WLAN). Filtered polar modulated signal used in a Time Division Multiple Access (TDMA) system including Global Mobile System (GSM). Receiver for receiving transmitted signal has a radio frequency (RF) unit which is located at a remote location from demodulator.

Abstract: A method for measuring a phase locked loop bandwidth parameter for a high-speed serial link includes the steps of initiating a jitter frequency of a clock input of a phase locked loop equal to a reference frequency with a frequency generator; determining a reference jitter amplitude value of a clock output of the phase locked loop with a waveform analyzer at the reference frequency, the reference jitter amplitude value being a function of a time interval error jitter trend of the clock output at the reference frequency; and adjusting the jitter frequency of the clock input with the frequency generator until an adjusted jitter amplitude value of the clock output reaches a goal value as determined by the waveform analyzer, the adjusted jitter amplitude being a function of a time interval error trend of the clock output at the adjusted frequency.

Abstract: Systems and methods provide for data transfer and transmission according to a synchronous one-bit interface protocol. A bit stream is generated including first data to be transferred or transmitted and second data from which a clock period used to encode the first data may be extracted. The bit stream is provided to a processor for decoding. In one embodiment, the bit stream includes a start segment or sequence, a data segment and a stop segment or sequence. A clock period is encoded into and is extracted from the start and/or stop sequences. The data segment is decoded on the basis of the clock period.

Abstract: A signal routing apparatus comprises a register bank to store a set of data signals. A delay locked loop generates a set of phase displaced clock signals. A phase controlled read circuit sequentially routes the set of data signals from the register bank in response to the phase displaced clock signals. A Low Voltage Differential Signaling buffer connected to the phase controlled read circuit transmits the data signals in a Low Voltage Differential Signaling mode. The phase displaced clock signals operate in lieu of a higher clock rate in order to reduce power consumption.

Abstract: Closed-loop rate control for data transmission on multiple parallel channels is provided. An inner loop estimates the channel conditions for a communication link and selects a suitable data rate for each of the multiple parallel channels based on the channel estimates. For each parallel channel, a received SNR is computed based on the channel estimates, an operating SNR is computed based on the received SNR and an SNR offset for the parallel channel, and the data rate is selected based on the operating SNR for the parallel channel and a set of required SNRs for a set of data rates supported by the system. An outer loop estimates the quality of data transmissions received on the multiple parallel channels and adjusts the operation of the inner loop. For example, the SNR offset for each parallel channel is adjusted based on the status of packets received on that parallel channel.

Abstract: Systems and methods for reducing the peak-to-average ratio (PAR) at the transmitter can reduce the dynamic range required in various analog components. PAR can be reduced by applying a time-domain compensation signal which reduces the magnitude of peaks in the time-domain signal prior to transmission where the time-domain compensation signals use tones that are reserved for the purpose of reducing the PAR. The reservation of these reserved tones for PAR can be implemented by altering the typical startup procedures in a digital subscriber line (xDSL) system. The use of the reserved tones to reduce the PAR can be implemented using a low complexity algorithm or using an adaptive technique.

Abstract: The system (700), apparatus (600), and method of the present invention provide an hierarchical pseudo-circularly symmetric and full circularly symmetric training sequence structure (100) for high-speed communication system. The hieratical pseudo-circularly symmetric part (101) is preferably used for burst detection, coarse frequency and timing error estimation and AGC gain setting. The full circularly symmetric part (102) is preferably used for channel estimation, fine frequency error estimation. The resulting sequence has a very good peak-to-average power (PAPR) property, making it suitable for many applications. The bandwidth efficiency is also improved due to using symmetric sequences.

Abstract: A receiver and a method for a receiver is disclosed. The receiver comprises a signal processing path for receiving a first signal modulated by a first modulation method and having a first bandwidth and a second signal modulated by a second modulation method and having a second bandwidth. A common gain control function is provided for processing said first and second signals. A common DC offset cancellation is also provided for said first and second signals. In a preferred embodiment the gain control and the DC offset cancellation a provided by a single circuit.

Abstract: A process variable transmitter that preferably includes a transmitter output circuit that provides bidirectional HART and controller area network communication transceiver lines. The transmitter output circuit also includes sensor circuit interface contacts. An isolated circuit couples to the sensor circuit interface contacts. The isolated circuit includes sensor circuitry sensing a process variable. The isolated circuit further comprises a galvanic isolation barrier galvanically isolating the sensor circuitry from the HART and controller area network transceiver lines. A stacked power supply provides power management. Other aspects may include a controller area network current limiter diagnostic output, timed sequencing of microcontroller startup and shutdown, a local operator interface and power management.

Abstract: The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate adjustments may be made by changing the number of information bits per symbol, or Forward Error Code (FEC) coding rate. A forward error correction (FEC) block size is maintained at a constant amount. Therefore, as the number of information bits per symbol are increased, an integer multiple of bits per epoch is always maintained. The scheme permits for a greater flexibility and selection of effective data rates providing information bit rates ranging from, for example, approximately 50 kilobits per second to over 5 mega bits per second (Mbps) in one preferred embodiment.

Abstract: Systems and methods for adaptive signal sampling and sample quantization for resource-constrained stream processing. Exemplary embodiments include a signal sampling and signal quantization method for a data stream from a ECG sensor into a pervasive device, the method including adaptively sampling the data stream, compressing data samples from the data stream, reducing the number of samples via quantization, defining a utility function for signal reconstruction, and formulating optimization on the reconstructed signal that is jointly sampled and quantized.

Abstract: A system and method for data communication over a cellular communications network that allows the transmission of digital data over a voice channel using a vocoder that operates in different modes depending upon characteristics of the inputted signal it receives. To prepare the digital data for transmission, one or more carrier signals are encoded with the digital data using one of a number of modulation schemes that utilize differential phase shift keying to give the modulated carrier signal certain periodicity and energy characteristics that allow it to be transmitted by the vocoder at full rate. The modulation schemes include DPSK using either a single or multiple frequency carriers, combined FSK-DPSK modulation, combined ASK-DPSK, as well as PSK with a phase tracker in the demodulator. These modulation schemes permit data communication via a CDMA, GSM, or other type of voice traffic channel at a low bit error rate.

Abstract: Disclosed are various embodiments of an input signal combiner. In one embodiment, a receive stage receives a multi-phase waveform and separates the multi-phase waveform into a plurality of waveforms. Analog-to-digital converters convert the plurality of analog waveforms into at least one digital signal. At least one gain stage adjusts an amplitude of each of the digital signals and combines the amplitude adjusted digital signals into at least one gain adjusted combined signal. A signal extraction stage extracts an inbound signal from the at least one gain adjusted combined signal according to a demodulation scheme.

Abstract: A voltage memory stores a signal level of a transmission signal from a signal generator at a timing of a clock signal, and outputs the transmission signal. A voltage difference detector detects a signal level of a transmission signal at a timing subsequent to the timing and detects a first signal level difference between the signal level and the signal level from the voltage memory. A maximum value detector, a voltage difference detector and bias voltage sources delay the transmission signal so as to keep a rise time of the transmission signal substantially within a predetermined value range by adding capacitances corresponding to the first signal level differences from the voltage difference detectors to transmission lines.

Abstract: A network repeater having a plurality of repeater ports selectively establishes links with remote nodes at one of two data rates based on the capabilities of the remote network node and a determined link integrity. A network repeater establishes a link with a network node using auto-negotiation techniques to establish a 100 Mb/s link. The network repeater then monitors the link for symbol errors, and determines an integrity of the link based on a detected number of symbol errors relative to a prescribed threshold. If the detected number of symbol errors reaches the prescribed threshold, indicating poor link integrity due to poor cable connection or condition, faulty network device, etc., the network repeater performs a down shifting operation by breaking the established 100 Mb/s link, and restarting auto-negotiation to establish a 10 Mb/s link.

Abstract: A method is provided of characterising a data stream of binary symbols, the method comprising sampling the stream at a predetermined rate sufficient to capture at least two samples per binary symbol, identifying the shortest continuous run of samples having the same logic level and assigning a symbol rate to the stream on the basis that the identified run is one symbol in length.

Abstract: Disclosed herein are embodiments of an improved built-in self-test (BIST) circuit and an associated method for measuring phase and/or cycle-to-cycle jitter of a clock signal. The embodiments of the BIST circuit implement a Variable Vernier Digital Delay Locked Line method. Specifically, the embodiments of the BIST circuit incorporate both a digital delay locked loop and a Vernier delay line, for respectively coarse tuning and fine tuning portions of the circuit. Additionally, the BIST circuit is variable, as the resolution of the circuit changes from chip to chip, and digital, as it is implemented with standard digital logic elements.

Abstract: A filter tuning circuit for a wireless communication system is provided. A filter tuning circuit includes a comparator and a counter which control a transconvertance value of a differential transconverter to tune a filter.

Abstract: Certain aspects of a digital baseband transmitter with digital RF/IF support in GSM/GPRS/EDGE compliant devices may comprise receiving digitized data within a chip. A control signal may be generated within the chip indicating whether the received digitized data is to be processed by an IF processing interface or a digital RF processing interface. The baseband processor has the capability to work together with different kinds of RF chips on the market and since this design is implemented on a single module, most of the circuits are shared which reduces the die size significantly. This design also provides a customer more flexibility to choose among different RF vendors.

Abstract: A method and apparatus for transmitting digital data in a cellular environment. Adjacent cells of the cellular system are prevented from simultaneously transmitting data. Because the noise from transmissions of adjacent cells is a primary source of interference, the transmission rate of power limited base stations can be dramatically increased when the noise from adjacent cells is eliminated. The transmissions to each subscriber station are made at a fixed transmission power level. However, the data rate of transmitted signals differs from one subscriber station to another depending the path loss differences. In a first exemplary embodiment, the data rate of transmissions to a subscriber station is determined by selecting an encoding rate for the transmitted signal while holding the symbol rate constant.

Abstract: Device, system, and method of resource allocation in a wireless network. Embodiments include optimal space-frequency architectures for very high peak rates in wireless systems. For example, an apparatus for wireless communication in a power-limited, very wideband system includes a wireless communication device having a media access controller (MAC) and a physical layer (PHY) that are adapted for a multiple-input-multiple-output (MIMO) orthogonal frequency-division multiple access (OFDMA) communication scheme; a plurality of antennas, operationally coupled to said device, to send and receive wireless communication signals according to the MIMO-OFDMA communication scheme; and a resource allocator, to allocate transmission resources of the device into desired MIMO channels optimized according to at least one of signal-to-noise ratio (SNR), bandwidth, number of users, and signal-to-noise-plus-interference ratio (SINR).

Abstract: Data compression and decompression methods for compressing and decompressing data based on an actual or expected throughput (bandwidth) of a system. In one embodiment, a controller tracks and monitors the throughput (data storage and retrieval) of a data compression system and generates control signals to enable/disable different compression algorithms when, e.g., a bottleneck occurs so as to increase the throughput and eliminate the bottleneck.

Abstract: A power control loop includes a feed forward unit 301 coupled to a data source, the feed forward unit 301 processes a signal for transmission, a feedback unit 302 coupled to the feed forward unit 301, the feedback unit 302 generates a feedback signal representative of an output power level of the signal transmitted by the feed forward unit 301, a closed loop power control unit 303 coupled to the feedback unit 302 and to the feed forward unit 301, the closed loop power control unit 303 generates an additive correction signal based on an error signal computed from the feedback signal and data provided by the data source, and a ramp path power control unit 304 coupled to the data source, the ramp path power control unit 304 generates a multiplicative correction signal based on an additive correction signal and data provided by the data source.

Abstract: Data compression and decompression methods for compressing and decompressing data based on an actual or expected throughput (bandwidth) of a system. In one embodiment, multiple access profiles are utilized to assist in compressing data according to various compression rates and compression ratios.

Abstract: A method and apparatus is provided for providing a phase glitch error filter for a delay lock loop. The device comprises a delay lock loop to provide an output signal based upon a phase difference between a reference signal and a feedback signal. The delay lock loop comprises a filter unit to provide filtering of noise on a phase control signal to substantially reduce a false delay lock loop state.

Abstract: An architecture for use in wireless receiver applications, particularly for ADC conversion of received in-phase I and quadrature Q signals. A single ADC is shared to convert both signals, and the ADC input is alternately switched between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of the single ADC.

Abstract: A circuit is provided for transferring a signal from a fast clock domain to a slow clock domain. The circuit includes a fast clock domain configured to receive an input signal and, responsively, transfer an intermediate signal. The circuit also a slow clock domain configured to receive the transferred intermediate signal from the fast clock domain and, responsively, generate an output signal. The circuit further includes a first synchronizer disposed in the slow clock domain and a second synchronizer disposed in the fast clock domain. The first synchronizer, operating with a slow clock, is configured to receive the intermediate signal and, responsively, provide the output signal as a transferred signal which is synchronized to the input signal. The second synchronizer, operating with a fast clock, is configured to receive a feedback signal from the first synchronizer for acknowledging synchronization of the output signal to the input signal.

Abstract: A frequency synchronization method comprise a first step of detecting a frequency error which occurs when a high-frequency receiving signal is converted into a digital signal of a base-band, performing rounding or discarding processing and generating a local oscillation signal depending on the converted analog signals, a second step of generating a digital signal whose frequency depending on a discard component obtained by the rounding or discarding processing when the rounding or discarding processing is performed, and a third step of canceling a frequency component of the digital signal which is generated by the second step from a frequency component of the digital signal of the base-band.

Abstract: A method is disclosed for controlling the operation of a low power radio platform that realizes the physical layer (PHY) with a software portion and an analog front end, the analog front end disposed between the DSP and an antenna, and realizes the MAC layer with a microcontroller unit (MCU). The DSP, analog front end and MCU are maintained in a low power mode of operation when not in data communication. When data communication is initiated, a hardware controller controls at least one hardware interface disposed between the DSP and the analog front end to initiate multiple time based tasks to transfer data to and from a buffer. During the execution of these tasks, the controller causes a task in the DSP to be initiated for processing of data in the buffers and, upon completion of at least one of the tasks, notifying the MCU of such. The controller controls the hardware interface to terminate operation when predetermined time based events have occurred.

Abstract: A method of transmitting data in a wireless communication system from a transmitter to a receiver, comprising the steps of modulating data at the transmitter using a first signal constellation pattern to obtain a first data symbol. The first data symbol is transmitted to the receiver using a first diversity branch. Further, the data is modulated at the transmitter using a second signal constellation pattern to obtain a second data symbol. Then, the second data symbol is transmitted to the receiver over a second diversity path. Finally, the received first and second data symbol are diversity combined at the receiver. The invention further relates to a transmitter and a receiver embodied to carry out the method of the invention.

Abstract: A technique for reducing crosstalk between communications paths includes scrambling data using scrambling functions that reduce or substantially minimize a probability that worst-case data patterns occur on communications paths adjacent to a potential victim communications path. In at least one embodiment of the invention, a method includes scrambling a plurality of data bits based at least in part on respective ones of a plurality of distinct combinations of one or more taps of a linear feedback shift register (LFSR). The plurality of data bits are scrambled for transmission during a first bit-time on corresponding ones of a plurality of adjacent communications paths.

Abstract: Various embodiments of the invention may use bitmaps to communicate channel quality index (CQI) information for multiple sub-channels in an orthogonal frequency division multiple access (OFDMA) wireless communications network. A base station may use bitmaps to report on whether the CQI information for each sub-channel has been under-reported or over-reported. A mobile station may use bitmaps to consolidate CQI information for multiple sub-channels into a single CQI set of parameters.

Abstract: One embodiment of the invention provides a wireless communication device including: a wireless communication unit that wirelessly receives first power consumption information from a device, the first power consumption information including a plurality of data pieces, each data piece indicating power consumption in the device for processing a streaming data signal encoded in each of a plurality of encoding formats; an encoding format selection unit that selects one of the encoding formats for a data signal to be transmitted, based on the received first power consumption information; and an encoding controller that encodes the data signal to be transmitted in the encoding format selected by the encoding format selection unit to generate an encoded data signal as a streaming data and outputs the encoded data signal to the wireless communication unit, wherein the wireless communication unit wirelessly transmits the encoded data signal as the streaming data to the device.

Abstract: A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.

Abstract: A radio communication apparatus that is capable of switching modulation schemes. The radio communication apparatus includes a QPSK modulation signal generator, a QAM modulation signal generator, a transmission radio, and a common transmission power amplifier. The QPSK modulation signal generator modulates transmission data by a QPSK modulation scheme and outputs a QPSK modulation signal. The QAM modulation signal generator modulates transmission data by a QAM scheme and outputs a QAM modulation signal. The transmission radio receives the QPSK modulation signal or the QAM modulation signal and outputs a transmission signal, which is amplified by the common transmission power amplifier.