Abstract: A frequency divider circuit is provided. The frequency divider circuit processes multiple input clocks. The frequency divider circuit includes a frequency dividing circuit and a retiming circuit. The frequency dividing circuit generates an intermediate clock according to a first subgroup of the input clocks. The retiming circuit generates multiple output clocks according to a second subgroup of the input clocks and the intermediate clock. The periods of the input clocks are all a first period, and the periods of the output clocks are all a second period. The first period is smaller than the second period. The frequency dividing circuit and the retiming circuit operate according to a mode control signal which determines a ratio of the first period to the second period.

Abstract: A light control sheet including a first transparent electrode, a second transparent electrode, a first light control layer positioned between the first and second transparent electrodes, and having light transmission property which is variable by a change in a voltage across the first and second transparent electrodes, and a voltage control unit which applies an AC voltage across the first and second transparent electrodes, and changes a frequency of the AC voltage applied.

Abstract: A memory processing unit can be configured to compute partial products between one or more elements of a first matrix stored in a first storage location and sequential bits of one or more elements of a second matrix stored in a second storage location. The partial products can be calculated utilizing zero bit skipping to increase throughput and or reduce energy consumption. The partial products for each column of elements can be accumulated and bit shifted to compute the dot product of the first and second matrix.

Abstract: A counter including a state determination unit and a counter reset unit is provided. The state determination unit is for receiving a current count value to calculate a next count value. The counter reset unit compares a reset counter value and a delay cycle value to determine using a first comparator or a second comparator, and compares the reset counter value and the current count value to output a counter reset signal to the state determination unit to reset the current count value, wherein a bit number of the first comparator is smaller than a bit number of the second comparator.

Abstract: A digital counter includes: a plurality of flip-flops configured to generate a plurality of count signals; and a controller configured to prevent level transition of an input terminal of a flip-flop to generate a count signal corresponding to a least significant bit (LSB), in response to a clock signal and a count end signal.

Abstract: A digital frequency divider including a parallel output register, a presettable asynchronous counter and a decoder. The parallel output register contains a desired count value. The presettable asynchronous counter has its preset data inputs coupled to the output of the parallel output register. The decoder receives its input from the data outputs of the presettable asynchronous divider and its output coupled to the load input of the presettable asynchronous counter.

Abstract: A programmable graphical display switch is described herein that provides users with a way of controlling other devices and for customizing how that control is initiated and communicated to a user.

Abstract: A solid-state image pick up device including a pixel array unit having unit pixels arranged in a matrix pattern. Each unit pixel includes a photoelectric converter. Additionally, the solid-state image pick up device has column signal lines that correspond to the respective columns of the matrix pattern, a row scanning means for selectively controlling each unit pixel, and an analog-digital converting unit for converting analog signals output from the unit pixels in a row selectively controlled by the row scanning means. The analog-digital converting unit further includes an asynchronous counter which performs counting in two modes and the asynchronous counter includes a counter processor configured so that when switching between the count modes occurs, a running count value is broken and there is an interval between the count modes and when a mode begins the running count value is reset to the value before the running count value was broken.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may also include increasing the number of first binary values in the binary field. Additionally, a second number indicating a second portion of the current number of the counter may be stored in another portion of memory. The second number may specify the number of times the first binary values has comprised the entirety of the binary field. Thus, the first number and second number may specify the current number of the counter. Storing the first and second number may be performed a plurality of times to implement a counting function of the counter.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: A circuit and method for distributing events in an event stream. A circuit for distributing events in a signal into a plurality of channels of circuitry capable of timestamping events is described. The circuit includes a first plurality of flip-flops arranged in a cascading configuration. The cascading configuration distributes a primary event stream into a first plurality of secondary event streams on each successive rising edge of the primary event stream. The circuit also includes a second plurality of flip-flops arranged in another cascading configuration for distributing the primary event stream. The primary event stream is distributed into a second plurality of secondary event streams on each successive falling edge of said primary event stream.

Abstract: A clock divider circuit producing 0° and 90° outputs with a 50% duty cycle is provided. In one embodiment, the clock divider circuit may include a pair of cross-coupled circuits. The clock divider circuit may produce a first output clock signal and a second output clock signal that is phase shifted a positive 90° with respect to the first output clock signal. The operation of the circuit may be responsive only to the input clock signal. In other words, the circuit may not require a reset signal to operate in a deterministic fashion.

Abstract: A programmable high speed frequency divider, in which flip-flops for forming a frequency divider which is capable of being programmed with a programmable dividing ratio is simplified increase the speed of the frequency divider. By simplifying the least significant bit flip-flops, including the flip-flop representing the least significant bit, among flip-flops forming a frequency divider, the speed of the counter in the frequency divider is increased and the frequency limit of an input clock which can be divided is raised.

Abstract: A ripple counter becomes programmable by use of intervening circuitry selectively inhibiting state transitions according to an initial programming step. The illustrated embodiment of a programmable ripple counter includes a forward chain of count registers operating generally in the fashion of a ripple counter, but selectively inhibited by an intervening control signal originating from a reverse chain of control registers. By selectively controlling the number of state transitions inhibited and by selectively controlling the number of registers participating in the counting operation, a low power general purpose programmable ripple counter results.

Abstract: A counting system with a dynamic maximum count includes a counter, match logic, and a maximum count controller. The counter has a present count register, a clock (or event indicator) event input, and a reset input. The maximum count controller can be programmed with an adjustable maximum count stored in a maximum count register. The match logic includes a count-wide AND gate fed by NAND gates. Each NAND gate has an inverted input coupled to a respective bit position of the present count register and an uninverted input coupled to a respective bit position of the maximum count register. The function of the match logic is to indicate a match whenever the present count has a 1 at every bit position that the maximum count has a 1, irrespective of the present count values at bit positions at which the maximum count has 0s. Thus, imperfect matches are provided for. The values of the imperfect matches always exceed the values of perfect matches, so they are not usually encountered.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.

Abstract: A reference clock signal oscillator generates a reference clock signal. A first programmable counter performs frequency dividing on the reference clock signal and outputs a reference signal resulting-from the frequency dividing. A voltage controlled oscillator generates an output clock signal, the frequency of which is controllable by input voltage control. A second programmable counter performs frequency dividing on the output clock signal and outputs a feedback signal resulting from the frequency dividing. A phase comparator compares the reference signal and the feedback signal, and outputs a phase difference signal which is based on the phase difference between the phases of the reference signal and the feedback signal. A driving circuit includes a charge pump and a loop filter and generates a signal to be applied to the voltage controlled oscillator based on the phase difference signal and performs filtering on the signal to be applied to the voltage controlled oscillator.

Abstract: A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.).

Abstract: Frequency divider circuit, frequency synthesizer comprising such a divider and radio telephone comprising such a synthesizer. A frequency divider circuit according to the invention includes a succession of N divide-by-two or divide-by-three dividing cells for an input frequency signal, while specific ones of these cells can be disabled to obtain division factors smaller than 2.sup.N.

Abstract: A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and a clock input. The output of the second flip-flop is coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops are acted upon by a clock signal. A first AND gate is connected upstream of the first flip-flop and has a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop.

Abstract: A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a mode register, respectively. The first and second registers act as, in the reload-timer mode a data register and a counter register, respectively, while in the counter mode, the first and second registers act as the counter registers.

Abstract: A dividing ratio is represented by a ratio (M/N) of two integers (M) and (N), and six data (N), (-N), (M), (M+N), (M-N) and (0) are generated, then one of the six data is selected on the basis of a condition that is predetermined by an input signal to be divided and a comparison result of the data (N), (-N) and data which is derived by addition or subtraction between the selected data from the six data and the previous calculation result of the addition or subtraction; and output or interception of an output signal is controlled on the basis the comparison result, and thereby the input signal is divided by the dividing ratio (M/N).

Abstract: A semiconductor integrated circuit includes an input terminal provided for each of input terminals. The input circuit outputs either one of "HIGH" or "LOW" as a frequency dividing ratio setting signal when the corresponding input terminal is "HIGH" or "LOW" in level but outputs another one of "HIGH" and "LOW" as a frequency dividing ratio setting signal when the corresponding input terminal is in an open state. Thus, the frequency dividing ratio of the programmable divider is determined, by fixing the level of only required ones of the input terminals into "HIGH" or "LOW" through, for example, wire bonding in the package while leaving all the others in open state.

Abstract: A timer circuit provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit having a first input for receiving an input signal to start a ramp signal, a second input for receiving a ramp timing conrol signal, and an output for providing a ramp signal. A comparator has a first input coupled to the output of the ramp generator, a second input coupled to a reference voltage source, and an output for providing an end ramp signal. A counter circuit has a first input for receiving the end ramp signal to begin counting, a second input for receiving a counter timing control signal, and an output for providing a terminal count signal. The end ramp signal and the terminal count signal are combined in an AND gate to provide a signal that is delayed by a predetermined amount from the input signal.

Abstract: Modulo timer apparatus including a chain of modulo counter stages is controllable by write signals generated by a central controller. The central controller is operative to generate a write signal corresponding to a selected counter stage, and a digital control signal. The initial counter stage of the chain includes a selecting circuit controlled by the digital control signal to couple either a reference clock signal or the corresponding write signal to the initial counter stage to alter the count thereof. Each successive counter stage includes a corresponding selecting circuit also controlled by the digital control signal to couple either a pulse signal generated from the preceding counter stage as it counts through its modulus value or the corresponding write signal to the successive counter stage to alter the count thereof.

Abstract: A programmable frequency divider for dividing the frequency of a supplied high-frequency signal directly into a lower frequency includes a plurality of 2-scale-factor prescalers or programmable frequency divider units each capable of being switched between divide-by-2 and divide-by-3 modes. The 2-scale-factor prescalers are connected in cascade for producing an output signal which is frequency-divided at one of multiple division ratios at a time.

Abstract: A binary counter (60) provides for resolution doubling by producing a wavetrain (Q0) which represents the zero-order bit of the counter and has the same frequency as the clock input (REFCLOCK).

Abstract: An asynchronous nonlogical counting device includes at least a first counter and a second counter connected in cascade. The first counter has a frequency dividing ratio of 2.sup.n where n is a natural number. A control unit produces a control signal based on the count value of the first counter. The second counter has a variable frequency dividing ratio which is based on the control signal. The counting device can be made programmable by substituting a comparator circuit for the control unit. The comparator compares the output of the first counter to an instruction signal from an external source.

Abstract: A coincidence circuit for detecting when n-bit binary input data coincides with the current value of an n-bit counter. A plurality of "1" detecting circuits determine, when a corresponding input bit is one, whether a corresponding counter bit is also one. A first-coincidence detecting circuit determines the first time that all the "1" input bits have corresponding "1" clock bits. Each "1" detecting circuit includes an inverter and a NOR gate. The first-coincidence detecting circuit includes an OR gate and a latch circuit.

Abstract: A programmable counter or frequency divider includes the combination of a fixed modulus prescaler (110) and a programmable divider (120, 130, 140, 150, 160) in which the prescaler provides more than a single clock phase to the programmable divider and the programmable divider utilizes the multiple clock phases to allow operation in a true fractional-integer mode. The overall combination of the prescaler and programmable divider functions as a programmable divider for which the minimum increment in the overall divider modulus is less than the prescaler modulus, but the maximum clock frequency usable is the maximum clock frequency of the prescaler.

Abstract: A high speed digital programmable frequency divider (100) capable of frequency division by even and odd integers is disclosed herein. The frequency divider (100) of the present invention includes a waveform generator (200) for providing a periodic input waveform of a first period and the inverse thereof. The present invention further includes a clocked ring oscillator circuit (400) for providing first and second closed signal paths, in response to the input waveform, disposed to invert signals passing therethrough. The first and second signal paths have a common output node (499) and first and second propagation delays substantially equal to first and second integral multiples of the first period, respectively. In addition, the frequency divider (100) includes a programmable switch network (500) for opening the first and second signal paths to provide a periodic output waveform at the output node (499).

Abstract: A frequency divider circuit for dividing an input signal with a predetermined integer or non-integer divisor. The frequency divider circuit comprises a polynomial counter, decode logic, and a clock edge selector. The polynomial counter, responsive to a clock signal at a predetermined frequency, cycles through a predetermined set of logic states which are logical combinations of the previous state, and generates a set of output signals which indicates the present logic state of the polynomial counter. The decode logic, responsive to the output signals of the polynomial counter, implements a predetermined logical mapping of said output signals into a decoded output signal. The clock edge selector, responsive to the decoded output signal of the decode logic, utilizes flip-flops and other logic to generate integer and non-integer multiples of the clock signal. The frequency divider circuit selects either integer or non-integer divisors depending on the informational content of a control signal.

Abstract: A method and arrangement for a fully synchronized, programmable frequency divider is disclosed that exhibits a near 50% duty cycle output signal independent of the divisor, whether even or odd, and that is suitable for use in a phase-locked loop (PLL) frequency synthesizer. As described in a first embodiment, the arrangement includes a data loader 31, a counter 32, a half-period detector 33, and a synchronizer 34. Next, a fast-locking, low-noise PLL frequency synthesizer is disclosed incorporating the fully synchronized, 50% duty cycle divider, and having a reference signal generator 71-72, a phase detector 73, a controlled oscillator 74-75, and the fully synchronized, programmable frequency divider 76. In a second embodiment, a fully synchronized programmable divider is described, including a data loader 31, a counter 32, a half-period detector 33', a synchronizer 34', and an additional block 82, a half-clock period detector.

Abstract: A timer which can be used to provide interrupt signals at predetermined but variable periods for multi-tasking microcomputers or serial data acquisition in pagers comprises a plurality of modulo counters. Each modulo counter has selectable clock inputs and has an output coupled via switches to a NOR gate and to the other modulo counters. Programmable configuring means control the switching means to configure the counters so as to produce desired outputs at the logic gate. The configuring means can also reset the modulus of the modulo counters to any desired value. Thus, the timer produces variable interrupt signals with little or no overhead processor time.

Abstract: A stable binary counter as applicable to synchronous counters, to frequency dividers and more particularly to microwave integrated circuits is constituted by a plurality of elementary counters mounted in cascade. Each elementary counter is formed by a half-adder having two inputs, one "sum" output and one "carry" output. The "sum" output is connected to the input of a master-slave flip-flop, the output of which is connected in a feedback loop to one input of the half-adder. The master and slave flip-flops are controlled by the two complementary waveforms of a single clock signal. The "carry" output of one half-adder is connected to the input of the following half-adder.

Abstract: A pulse generator with adjustable pulse frequency, pulse width and pulse delay contains a start-stop oscillator (1) whose oscillator pulses are counted by a counter (2) in adjustable counting cycles. After each counting cycle, the oscillator (1) is shut down for an adjustable time interval. The pulses of the output signal of the pulse generator are produced at the occurrence of a predetermined count value, and the end of these pulses is essentially determined by a second predetermined count value. As the oscillator (1) has a fixed operating frequency and for the purpose of frequency interpolation is periodically shut down during short time intervals and then restarted, a pulse generator is obtained having very small frequency deviations over a wide frequency spectrum.

Abstract: An improved duty cycle timer provides a duty cycle control signal having alternate "on" and "off" intervals of different logic states. The timer utilizes integrated circuitry having first and second independent clock sources respectively driving first and second multistage, binary counters. One counter measures the "off" interval and the other counter measures the "on" interval. Each counter provides a signal representative of the completion of the interval which it measures, and that signal is connected to a resetting input of the opposite counter for initiating the measuring interval of that opposite counter. Typically, one interval is longer than the other. The duty cycle control signal is provided by the output of one of the counters. In an illustrated embodiment, the duty cycle timer controls operation of a defrost mechanism for a refrigeration circuit and the "off" interval is longer than the "on" interval.

Abstract: A programmable divide-by-N counter employs a plurality of speed enhancement techniques to provide an overall operational speed corresponding to the speed at which a single-clocked flip-flop is capable of being toggled. The counter configuration provides flexibility in selecting the value of N, the programmable divisor, as well as the possibility of increasing the length the counting chain without producing a reduction in overall operational speed. The speed enhancement techniques are primarily located in the reset logic portion of the counter. A key aspect utilized through-out the overall circuit is that critical signal propagation paths in terms of speed of operation present no more than four gate delay intervals in total response time.

Abstract: Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits. A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.

Abstract: A programmable delay generator is based upon an asynchronous or ripple counter the stages of which change state at definably different times. A full terminal count is decoded including the condition of a lowest order stage which changes state at a unique time which is different from the time at which any other stage changes, for thereby defining an unambiguous delay period. A partial terminal count programmably determines the length of circuit output and the reloading of the ripple counter with a programmable, time delay determining, initial value.

Abstract: A trigger holdoff system for an oscilloscope is provided in which a desired trigger signal is taken out from a repetitive group of raw trigger signals with variable time therebetween. A trigger generator generates raw triggers which clock a divide by N counter programmable by a microprocessor. When the counter reaches its terminal count, a trigger is passed on to sweep or acquisition circuits from the trigger holdoff system and an enable signal is set so that the next raw trigger reloads the counter.

Abstract: A delayed sweep oscilloscope having a word recognizer displays multi-digit parameters representing an event count necessary to initiate a delayed sweep, and a word to be recognized on oscilloscope data input lines. The numbers are modified digit-by-digit by rotating a first control knob to move a cursor on the screen to select a digit to be altered and then by rotating a second control knob to alter the selected digit. The control knobs are mounted on the oscilloscope front panel and when not used to modify these parameters, the control knobs may be used to control other oscilloscope functions.

Abstract: A clock circuit is initiated by an external trigger pulse. Timing measurements commence at a first rate, and after a first delay (t.sub.1) which is sufficient to allow an oscillator of the clock circuit to stabilize. After a second delay (t.sub.1) the clock circuit operates at a second rate which is half the first rate. The clock circuit then represents the time from reception of the external trigger pulse. The first and second delays are derived by charging a capacitor at a constant rate and comparing the voltage level developed across it with respective reference voltages (V.sub.1, V.sub.2) in comparators.In general, the second rate may be 1/r+1 times the first rate, where r is the ratio of the first delay to the second delay.

Abstract: A counter/divider apparatus employing an array of counters arranged in parallel. Each counter repeatedly counts through a sequence of a number of clock pulses. The number is different for each counter and the numbers are relatively prime numbers. The outputs of the counters are applied to a detector that recognizes a preset combination of output signals which is present after a predetermined number of clock pulses have been received. The detector then produces an output pulse which clears all the counters to their initial states, and the cycle is repeated. The apparatus thus divides the input clock pulses by the aforementioned predetermined number.

Abstract: A data processor having an integral timer including a clock generator producing a specific frequency output comprises a counter chain having an input and output thereof for supplying a fixed frequency divide function. A programmable prescaler couples the clock generator output to the counter chain input for providing a predetermined divisor input to the counter chain. A postscaler operates in consonance with the programmable prescaler coupled to the counter chain output for providing a timer output compensated for the predetermined divisor input. In operation, the timer output has a frequency bearing a constant relationship to the clock generator output frequency independent of the predetermined divisor input of the programmable prescaler.

Abstract: An adjustable ratio divider comprises a controllable gate connected in series with a divider for passing a clock signal in pulse form whose frequency is to be divided. A means is provided for controlling the gate to subtract a selectable number (including zero) of clock pulses from the clock signal to control the division ratio of the divider.

Abstract: A high speed programmable prescaler has an input divider that divides an input stream of clock pulses by either 2 or upon command by 3. Connected to the input divider is a plurality of dividers that are electrically cascaded together from a first member to last member with each member of the plurality of dividers being capable of dividing the clock pulses applied to it by either 2 or upon command by 3. A prescaler selects either 2 or 3 for dividing the input stream of clock pulses so that number of clock pulses necessary to obtain an output pulse can be represented by the equation of 2.sup.N +M where N is the number of members of the plurality of dividers and M is the control number having a range of 0 to 2.sup.N -1.The critical path delays are minimized by using a flip-flop in the input divider to divide by 2 and then on command shifting the output of the flip-flop by 180.degree. to obtain the divide by 3 function.

Abstract: A variable rate, bi-directional slew control employing a dual-concentric potentiometer having a first shaft attached to a first spring for urging it to remain in an extreme clockwise position and a second shaft urged by a second spring to remain in an extreme counterclockwise position wherein an extension of a sleeve provides the means for manual manipulation of the first shaft in a counterclockwise direction and the second shaft in a clockwise direction. A first tap associated with the first shaft is electrically connected to a first off-zero detector which is itself connected to a pulse generator which is in turn connected to an up input of an up/down counter. A second tap associated with the second shaft is electrically connected to a second off-zero detector which is connected with a second pulse generator which is in turn connected to a down input of the up/down counter.

Abstract: In utilizing frequency dividers at high frequencies the maximum operating frequency is determined by the delay time through the frequency divider. To minimize this delay time, a digital frequency divider is provided having a binary counter constructed of flip-flops and a shift register coupled to the output of said counter, wherein the output state of the shift register is forcibly reduced to a low level in response to a control signal for varying the number of frequency division of said counter. A circuit is also provided for feeding the input terminal of the flip-flop at the first stage of said counter with an OR output made up of the outputs of said shift register and said counter. Thus, the digital frequency divider can operate at a speed which is limited only by the toggle frequency of said flip-flop circuits.