Abstract: A driving circuit, including: a pull-up transistor and a pull-down transistor, where a first terminal of the pull-up transistor is connected with a power source, a second terminal of the pull-up transistor is connected with a first terminal of the pull-down transistor to together output a driving signal, and a second terminal of the pull-down transistor is connected to ground; and a control circuit connected with a control terminal of the pull-up transistor and/or the pull-down transistor respectively and configured to control the on or off switching of the pull-up transistor and/or the pull-down transistor so as to change the driving signal. The pull-up transistor and the pull-down transistor are not switched on at the same time under the control of the control circuit.

Abstract: A counter circuit is provided that can switch delay times by use of a simple circuit configuration. A counter circuit includes plural stages of flip flops connected in cascade, in which a flip flop in a first stage receives a clock from an oscillator as an input signal, and a flip flop in a given stage after the first stage receives a Q output of a preceding stage as an input signal, wherein all or part of the plural stages of flip flops receive a mode signal, and wherein each of the plural stages of flip flops divides by 2 a frequency of the received input signal for output as a Q output when the mode signal indicates a normal delay mode, and each stage of the flip flops that receives the mode signal allows through passage of the received input signal for output as a Q output when the mode signal indicates a delay shortened mode.

Abstract: The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.

Abstract: Described are fast synchronous counters with reduced combinatorial logic. In one embodiment, a four-bit shift register is configured in a ring and preset with a data pattern (e.g., 1000). The register is then rapidly shifted into any of four unique states. Combinatorial logic connected to the shift register converts the four unique states into a two-bit binary signal representative of the four states. In the general case, counters in accordance with this embodiment represent N-bit binary numbers using 2N synchronous storage elements. Two or more counters can be combined to produce larger synchronous counters. An up/down counter in accordance with yet another embodiment is connected to a multi-path delay line to create a variable delay circuit. The switching speed of the delay circuit is independent of the number of delay settings. Also advantageous, the delay circuit scales linearly, in terms of power consumption and area, with changes in delay granularity.

Abstract: 1.

Abstract: An increasing monotonic counter over n bits formed as an integrated circuit, including an assembly of 2n+1?(n+2) irreversible counting cells distributed in at least n groups of 2p?1 counting cells, where p designates the group rank, and at least n?1 parity calculators, each calculator providing a bit of rank p, increasing from the most significant bit of the result count, taking into account the states of the cells of the group of same rank.

Abstract: A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the transit of an external address in the master storage circuit; a circuit for enabling the connection between the slave storage circuit and the master storage circuit; a circuit for enabling the connection between the master storage circuit and the slave storage circuit; a circuit for calculating the product of the external address and of an input carry signal which arrives from a preceding counter stage; and a circuit for calculating an output carry signal on the basis of the external address and of the input carry signal.

Abstract: A digital delay generator device is based on a series arrangement of cells, wherein each cell has a first input for receiving a single-phase clock signal, a second input for receiving a delayable signal for thereto imparting a cell delay, and an output for a so-delayed signal. Each cell comprising a series stack of transistors, and various cells comprise further transistor means for receiving a bypass control signal. Such further transistor means are arranged for under control of a bypass control signal effectively bypassing one or more cells to thereby effect a quantized overall delay shortening. In particular, such various cells form a contiguous pair in said string, and the transistor means effectively form respective transistor bypasses over clock-signal-controlled transistors in the associated series stack at mutually opposite sides of their respective stack.

Abstract: A master-slave flip-flop has two switches that control the flow of data into and through the master and slave stages. The switches are controlled by a three-phase clock signal that is designed to address the problem of data shoot-through. Implementations of the flip-flop rely on weak feedback techniques that allow the flip-flops to be implemented using weak keeper devices in the feedback paths of the master and slave stages and without switches in those feedback paths. The flip-flop enables fast and reliable flip-flops to be implemented with minimal layout area and power consumption.

Abstract: A high-speed counter circuit comprising an input line for inputting a clock signal, at least two bit counters for generating a count value of at least two bits in response to the clock signal from the input line, at least one clock synchronizing circuit responsive to an output signal from at least one higher-order bit counter of the at least two bit counters, for transferring the clock signal from the input line to a lower-order bit counter of the at least two bit counters, and a delay circuit for delaying the clock signal from the input line by a propagation delay time of the at least one clock synchronizing circuit and applying the delayed clock signal to a highest-order bit counter of the at least two bit counters. According to the present invention, the high-speed counter circuit can minimize a delay time from the application of the clock signal to the generation of the count value to enhance the operation speed.

Abstract: A synchronizing circuit including a plurality of latches, comprised of a first dynamic type through latch circuit and a second dynamic type through latch circuit between which is disposed a static type through latch circuit, the circuits connected in cascade. Data is sampled at the timing of the rising edge of the clock signal generated by a pulse generation circuit connected to a clock input circuit and data is output at the timing of the trailing edge. By defining the clock pulse width generated at the pulse generation circuit larger than the clock skew, it is possible to prevent malfunctions of the LSI caused by clock skew caused by deviation of timing of the clock distribution. Moreover, by providing a dynamic type through circuit for a scan test input to the first dynamic type through latch circuit in parallel, a scanning function can be realized and a malfunction due to the clock skew during scanning can be prevented.

Abstract: A frequency dividing circuit includes a first inverter circuit supplied with a first frequency-divided signal, a second inverter circuit supplied with a second frequency-divided signal which has a complementary relationship to the first frequency-divided signal, and a first pair of push-pull circuits. There are also provided a first switch circuit performing a first switching operation in response to a first input signal and selectively supplying output signals of the first and second inverter circuits to the first pair of push-pull circuits so that one of the first pair of push-pull circuits performs a pull-up operation when the other one thereof performs a pull-down operation.

Abstract: A circuit configuration being made by differential technology for dividing a clock signal with switchable divider ratios of 4/5 by emitter coupled logic, includes first, second and third series-connected flip-flops each having an output, a data input and a clock input. The output of the second flip-flop is coupled to the data input of the third flip-flop, and the clock inputs of the first, second and third flip-flops are acted upon by a clock signal. A first AND gate is connected upstream of the first flip-flop and has a first input being acted upon by a control signal for switching over the divider ratio, and a second input being acted upon by an inverted signal from the output of the third flip-flop.

Abstract: A frequency divider includes a transmission gate having input and output terminals and a gate terminal to which a single-phase clock signal is applied to turn off and off the transmission gate; an element having an input terminal connected to the output terminal of the transmission gate for inversion, delay and amplification of a signal input to the input terminal of the element to produce an output signal and outputting the output signal to the input terminal of the transmission gate; and a frequency divider output terminal connected to the output terminal of the element and to the input terminal of the transmission gate for outputting a signal having a frequency equal to 1/n (n=integer) of the frequency of the clock signal. Since the frequency divider includes one transmission gate and one element, the delay time of the critical path required for inverting the produced frequency-divided signal is reduced so that accurate frequency division is performed with a high-speed clock.

Abstract: A general object of the present invention is to provide a latch of which demand is small. In a half-latch 101, control signals T2 and T2C which vary at late timings are applied to a main unit for data input (update) operation while control signals T1 and T1C which vary at early timings are applied to a feedback unit for data retaining operation. The data input (update) operation is never started until the data retaining operation is completed. The data retaining operation is practiced by retaining two signals having a negative logic relation with each other in a loop made up with two inverters. A signal related to retension of data and a signal newly input never reside in the same signal line. Thus, collision of those signals is avoided, and consequently, through-current due to the collision of the signals can be reduced.

Abstract: A fast counter includes a clock generator (18), a control circuit (22), and a counting circuit (12). The counting circuit is formed of at least one uniform delay structure (12a, 12b) having a plurality of counter bit cells (58, 60). The uniform delay structure has a regular configuration suitable for very large scale integration. The fast counter is implemented so as to provide minimal propagation delay at relatively low cost.

Abstract: A flip-flop circuit includes a data input terminal, a data output terminal, a memory circuit and a bypass circuit having a shorter delay time than that of the memory circuit. The memory circuit and the bypass circuit are connected in parallel between the data input terminal and the data output terminal so that the data are outputted to the data output terminal through the bypass circuit when the data are written in the memory circuit. As a result, the delay time of the flip-flop circuit is shortened.

Abstract: A counter cell includes a latch circuit, control circuit, and a pull-up circuit. The laatch circuit is formed of a first clocked half-latch (32), a second clocked half-latch (34) and an inverter (INV1) for storing a binary output signal. The first clocked half-latch (32) is responsive to a first clockk phase signal for transferring the binary output signal from its input to its output. The second clocked half-latch (34) is responsive to a second clock phase signal for transferring binary output signal from its input to its output. The control circuit is responsive to an input complement signal for selectively passing the first clock phase signal to the first clocked half-latch so as to permit toggling the state of the binary output signal. The pull-up circuit is responsive to the binary output signal and the input complement signal for generating an output complement signal.

Abstract: An improved dynamic frequency divider circuit is disclosed. A DC voltage generating circuit (10) generates a DC voltage (Vcon) having a level the same as a threshold voltage of an inverter. A voltage application circuit (41) supplies a voltage (Vcon) to one electrode of a capacitor through a high frequency signal component cut-off coil (8), and a high frequency signal component is superimposed on the provided DC voltage. Accordingly, an input signal of an inverter (1a) swings around the threshold voltage level as a center, so that the inverter (1a) can provide a signal having the duty cycle of 50% as an output. As a result, the dynamic frequency divider circuit can be prevented from malfunctioning.

Abstract: The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, the PMOS gates turn on and pass bit values. At the same time the adjacent NMOS gates, which are driven by the same low clock signal, shut off and prevent the passed bit values from traveling any further. The bit values are thus held between adjacent PMOS and NMOS gates. When the clock signal next goes high, the NMOS gates turn on and pass the held bit values while the PMOS gates driven by the same high clock shut off. The gates are connected by circuitry which essentially holds the bit values passed through the first associated gate until they are passed through the second associated gate. The shift register may also include gated or non-gated refresh circuitry, which operates to maintain a passed bit value.

Abstract: A counter circuit is disclosed. The circuit has a first tri-state inverter for receiving data bits and their components. It includes a first tri-state latch for receiving the data bits and their complements, connected to the output of the first tri-state inverter. It has a second tri-state inverter for receiving the data bits and their complements that is connected to the output of the first tri-state latch. It includes a second tri-state latch for receiving the data bits and their complements. The second tri-state latch is connected to the output of the second tri-state inverter. Its output is the output of the circuit, and, its output is fedback to the first tri-state inverter. Such a circuit is useful in setting an internal address of a dynamic memory device during a CBR cycle.

Abstract: A shift register apparatus comprising unit registers, clocks and gates. Only when data input to the apparatus is significant enough to shift the state of the unit registers, is the clock signal supplied selectively to the unit register of the applicable stage. The selective supplying of the clock signal reduces the power fed to clock lines. With a larger number of shift stages, a greater amount of power will be saved, especially in applications where the apparatus is used to generate multiphase pulses. Fewer drivers are needed to drive the clock signal, which may be supplied at the TTL level.

Abstract: A CMOS single phase register includes two pairs of cross coupled CMOS inverters connected together by transistor switches. The first pair of cross-coupled CMOS inverters is connected to a complementary pair of data inputs through a first pair of transistor switches which turn on in response to a first logic level. The complementary outputs of the first pair of cross-coupled CMOS inverters is connected to the inputs of the second pair of cross-coupled CMOS inverters through a second pair of transistor switches which turn on in response to a second logic level. The complementary outputs of the CMOS single phase register of the present invention are the outputs of the second pair of cross-coupled CMOS inverters. The ground connections of the first pair of cross-coupled CMOS inverters is made through a transistor switch which turns on in response to the first logic level.

Abstract: A master-slave flip-flop having a first bistable cell and a control circuit coupled to that first cell for changing the binary state of the cell in response to a set of complementary data inputs and a clock signal. The slave portion of the flip-flop includes a second bistable cell that is coupled to the first cell and a second control circuit for changing the state of the second cell in response to the output of the first cell and to a clock signal. The flip-flop is intended to be implemented using CMOS technology, and is capable of performing at frequencies greater than a gigahertz with low power consumption. The circuit configuration is highly symmetric, so that the master and slave portions may be interchanged.

Abstract: An improved high speed two phase clock counter is disclosed. The counter includes a plurality of counter cells coupled to a transition pattern recognizer. Through the use of these elements a counter is provided that overcomes the power consumption and size limitation problems associated with known high speed counters.

Abstract: A hyperfrequency dynamic divide-by-two frequency divider circuit includes an inverter stage A and a follower stage B, in which the output of the inverter stage is applied to the input of the follower stage via an interrupt transistor T.sub.1 which is controlled by the hyperfrequency input signal H having a frequency f.sub.e. The output Q of the follower stage B is fed back to the input of the inverter stage A and supplies the output signal having a frequency f=f.sub.e /2. The operation of the divider takes place subject to the conditions:1/[(.alpha.+1) Tpd].ltoreq.f.sub.e .ltoreq.1/[(.alpha.+1).tau..sub.1 ]where .alpha.=(T.sub.e -.tau.)/.tau., in which relations .tau..sub.1 is the propagation time in the interrupt transistor, .alpha. is the duty cycle, T.sub.e is the period of the input signal, .tau. is the period during which the interrupt transistor T.sub.

Abstract: A high performance latch circuit having complemented isolation means that selectively maintain the state of the latch at a given logic state or input a new logic state thereto. The latch is made up of several legs of series connected translators, the legs being connected in parallel. Selective gating is provided by the transistors directly coupled to the output node.

Abstract: An incrementer circuit includes a plurality of input terminals for receiving an address data, having a plurality of bits, to be incremented, a carry signal generating unit for generating a carry signal for each bit of the address data and a plurality of output terminals where an incremented address data appears. The carry signal generating unit includes a detector for detecting whether or not all of a predetermined number of less significant bits of the address data are at high level and outputs a detection signal if so. In response to this detection signal, a carry signal is generated and supplied to a bit which is more significant than the most significant bit of the predetermined number of less significant bits by one bit.

Abstract: The synchronization circuit of the preferred embodiment is a T flip flop which has a first output which changes state on the leading edge of the clock signal, and a second output which changes state on the trailing edge of the clock signal. The T flip flop has an exclusive OR gate input in which the T input is combined with the first output. The output of the exclusive OR is coupled to an internal node when the clock signal is at a first logic state, and isolated from the internal node when the clock signal is at a second logic state. The internal node is coupled to the first output when the clock signal is at the second logic sate and isolated from the internal node when the clock signal is at the first logic state. The first output signal is coupled to the second output signal when the clock signal is at the first logic state, and isolated from the second output terminal when the clock signal is at the second logic state.

Abstract: A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.

Abstract: A high speed CMOS binary up/down counter having a 200 MHZ clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. The counter performs in an up-count mode or a down-count mode in accordance with the state of a mode select signal. Each stage of the 4-bit counting section comprises a propagate/kill/generate gate for determining the status of a carry signal to a next stage, except the last stage of a 4-bit section, which does not require such a gate because it is coupled to a carry-forward generator along with the outputs from the other preceeding stages in the section. Each 4-bit section performs the counting function through a successive process of modulo-two sums of a lower order carry and the current state of a counter stage without the need for cumbersome gating structures.

Abstract: A master-slave flip-flop circuit includes a master circuit switching element controlled by a first clock signal for controlling transfer of data from an input terminal to a master circuit data holding element which holds data transferred through the master circuit switching element, and a slave circuit switching element controlled by a second clock signal for controlling transfer of data from the master circuit data holding element to a slave circuit data holding element which holds data transferred through the slave circuit switching element. The first clock signal is nearly in phase with, but lags a little behind, the second clock signal.

Abstract: A storage cell and a sense amplifier for use in a register or other memory in an integrated circuit. The storage cell has single-rail input and output, thereby eliminating the necessity of differential input lines and access transistors. The cell also has dual individually-addressable output buses. The sense amplifier includes a master latch connected to the bit line from the storage cell and a slave latch connected to the output. The master latch is normally maintained at its meta-stable condition by a normally-enabled gate. When the content of a storage cell is to be read, the cell outputs a signal onto the bit line, which signal drives the master latch to one side of its meta-stable state. The gate is turned off, allowing the master latch to go to the nearest stable state. The slave latch is connected to the master latch and assumes a state in response thereto. The slave latch and master latch are then disconnected and the master latch returned to its meta-stable state.

Abstract: A synchronizer circuit having a predictable and finite metastable time, and thereby a finite sample interval, resulting in the minimization of the probability of errors in asynchronous information transfer.

Abstract: A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.

Abstract: A 1.2 .mu.m CMOS binary counter having a 200 MHz clock rate comprises a 4-bit counting section that may be concatenated in multiple 4-bit sections. Each bit stage within a 4-bit counter section uses the current state of such stage to determine what happens in the next stage. Each 4-bit section performs the counting function through a successive process of additions of a lowest order carry-bit input. A count enable signal serves to enable the count process as well as serving as a carry-bit input to a first stage. Count enable effects a counter reset when in a logic "zero" state. Once the count enable is raised to the logic "one" state, the process of counting begins with the rising edge of the first clock pulse. As long as the count enable is maintained, counting continues. When the count enable is reduced to a "zero" state, counting is terminated, with a counter reset occurring on the next sequential rising edge of the clock.

Abstract: The basic element provided by the invention carries out the basic logic functions of storage and/or transfer of the data applied at the input, typical of a latch. Two ways of embodiment of the basic element having active phase at the high and low level of the clock signal are described. The basic element presents a transfer-gate transistor at the input controlled by the clock signal, followed by an inverter at whose signal leads two positive feedback networks are connected, one of which controlled by the clock signal, to stabilize the logic levels (FIG. 1).

Abstract: An electronic D-type flipflop includes two storage elements and two transmission gates wherein each gate includes only one MOS transistor. In the first gate the MOS transistor is of a first conductivity type and it is of a second conductivity type in the second gate. The MOS transistors each receive the same clock signal at their gate electrode. Because it is not necessary to form an inverted clock signal, problems due to phase differences between the clock signal and its inverse are precluded. Each of the storage cells includes a pair of inverters which are coupled end-around. The transmission characteristic of the forward inverting circuit is adapted in such a way that it compensates for the voltage drop across the preceding transmission gate. Only a small substrate surface area will be required when the flipflop is used in an integrated circuit.

Abstract: A counter cell for counting either up or down by one or two includes a multiplexer section, an increment/decrement section, and a carry section. The multiplexer section is responsive to control signals and input carry signals for generating a count signal which determines the counting by one or two. The increment/decrement section is responsive to count signal and an increment strobe signal for generating an incremented output signal and a decremented output signal. The carry section is responsive to the increment/decrement section and the input carry signals for generating a carryout-by-one signal and a carryout-by-two signal. A number of these counter cells are arrayed to form an N-bit counter.

Abstract: A static bistable flip-flop circuit using CMOS technology. The flip-flop reduces the number of CMOS transistors by not using two complimentary transistors in parallel for certain switches. This reduces the risk of transparency which is inherent with conventional CMOS complimentary transistors. Between the input and output of the circuit there is only a first N channel transistor, a first inverter, a second N channel transistor and a second inverter connected in series.

Abstract: A high speed, low power, multi-bit, single edge triggered, wraparound binary counter is provided which is resettable and loadable from a user-supplied address. The binary counter requires a relatively small amount of power due to the use of CMOS technology for construction of its circuitry, may be initiated at any of 2.sup.N (where N=bit count) start locations, and can be easily adapted to accommodate any desired number of counter cells. Further, it is capable of operating over wide ranges of temperatures and power supply conditions. The high speed binary counter is formed of a plurality of counter cells in which each counter cell includes a pass gate device responsive to a counter-update signal for allowing true and complement addresses to control a switching device when the counter-update signal is in the low state and for isolating the true and complement addresses from the switching device when the counter-update signal is in the high state.

Abstract: An incrementer cell includes an input section, an output section and a carry section. The input section is responsive to an input data signal and an input carry signal for generating an incremented output signal. The output section is coupled to the input section for generating a data out signal to be either the incremented output signal or the input data signal. The carry section is responsive to the input data signal and the input carry signal for generating a carry-out signal.

Abstract: The digital circuit is for receiving a master clock signal at a frequency te f on an input and delivering a rectangular shaped output signal at a lower frequency (M/N)f where M is an integer and N is an even integer greater than M. The circuit comprises an even number N of series connected flip-flops in a ring arrangement, each flip-flop being connected to receive input signals from the preceding flip-flop and from the following flip-flop and to receive a master clock signal on a clock input. The even numbered flip-flops are of a type different from the type of the odd numbered flip-flops. The outputs of the flip-flops each deliver a rectangular pulse signal having a duty ratio equal to 1/N of that of the master clock signal. The pulse signals are applied to a combination logic of OR type giving an output signal combining the outputs of said plurality of flip-flops.

Abstract: In order to reduce the likelihood of incorrect states being transferred from one cross-coupled transistor pair to the next in a frequency divider which comprises at least two such pairs (6a, 7a and 8a, 9a) which are energized alternately by means of a switchable current source arrangement (5) and which are inter-coupled to form a cyclic arrangement by means of data transfer transistors (6b, 7b, 8b and 9b) energized from the same outputs (22, 23) of the current source arrangement, the transistors employed are of the insulated gate field effect type. The channel width-to-length ratios of the pair transistors (6a, 7a, 8a, 9a) may be chosen to be different from the corresponding ratios for the data transfer transistors (6b, 7b, 8b, 9b) in order to improve either the high-frequency or the low frequency performance in accordance with the sign of such difference.

Abstract: An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.

Abstract: A racefree CMOS clocked logic circuit includes a first CMOS clocked gate for selectively transferring an input signal according to a first clock pulse and providing an interstage signal corresponding to the input signal; and a second CMOS clocked gate, which is connected directly to the first CMOS clocked gate, for selectively transferring the interstage signal according to a second clock pulse and providing an output signal corresponding to the interstage signal. The operation of first CMOS clocked gate is synchronized to the first clock pulse, and the operation of second CMOS clocked gate is synchronized to the second clock pulse. The second clock pulse is in-phase with or identical to the first clock pulse so that signal races between the input signal and the output signal are eliminated.

Abstract: A CMOS dynamic circulating-one shift register (10) is disclosed. One stage of a conventional N-stage circulating-one shift register is modified to become a control cell (14) which performs two additional functions, referred to as AUTOSET and AUTOCLEAR, to guarantee the existence of a single circulating logic one, after power up or during long-term use. To perform the AUTOCLEAR function, the output (Q3) of the control cell is connected to the CLR inputs of each of the remaining stages (12.sub.1 -12.sub.N-1) comprising the shift register. Therefore, when Q3 becomes a logic one, the remaining Q outputs are automatically cleared. The Q output from the control cell is also fed back as the D input to the first stage of the shift register (12.sub.1) to continue the circulation process.

Abstract: An 8.5 divider comprises a first and second 1/2 dividers to produce output pulses having phases different from each other by 90.degree., a first logic gate producing output pulses having a repetition frequency of a half of the input pulses, a third and fourth 1/2 dividers connected in series and dividing twice the output pulses of the first logic gate by two, a fifth 1/2 divider receiving the output of the fourth 1/2 divider, a second logic gate detecting the simultaneous presence of the outputs of the second, third and fifth 1/2 dividers to invert the phase of the output pulses of the first 1/2 divider and a third logic gate detecting the simultaneous presence of the outputs of the first and third 1/2 dividers and the inverted output of the fifth 1/2 divider.

Abstract: A latch circuit includes a CMOS inverter to which a logic signal is applied to the input through an input terminal, which inverter continues to supply an output signal to its output terminal; and first depletion type p and n-channel MOS transistors connected in series to each other, with the CMOS inverter being interposed therebetween. The latch circuit further includes second depletion type n and p-channel MOS transistors which are supplied, at their gates, with an output signal from the CMOS inverter; the second n-channel MOS transistor being connected between the first p-channel MOS transistor and a power supply terminal, and the second p-channel MOS transistor being connected between the first n-channel MOS transistor and a ground.

Abstract: A signal translating circuit is disclosed in which an input signal is supplied to a source follower transistor, a bootstrap capacitive component is presented between the gate and source of the source follower transistor, the signal from the source follower transistor is supplied through a first transmission gate to a next stage, and also led out to an output terminal. Further, the circuit formed of the source follower transistor and the first transmission gate is sequentially connected and the source follower transistor and the first transmission gate are alternately driven with different phases to each other whereby the input signal is sequentially transmitted at each stage.