Abstract: An apparatus for eliminating noise is disclosed. The present invention includes a counter, which counts in a first direction when an input signal is active, and in a second direction otherwise. A determining device is used to determine a predetermined first threshold value, and assert an output signal while such value is reached. The present invention also includes a limiting device, which prevents the counter from counting beyond or below a predetermined limit value.

Abstract: A counting apparatus having excellent fail-safe characteristics can be used in a rotation-stopped detection apparatus. As a first feature, timing of a high-frequency signal P.sub.2 is carried out by a counter 1 after completion of a counting of pulse signals P.sub.1. When the frequency of the timing output for the high-frequency signal is a predetermined value, a judgment signal, indicating that the counting is normal, is generated by a frequency discriminating circuit 30. As a second feature, a counter 100 is preset using a preset signal. Then, after verifying by an output from a self hold circuit 102 that the counter 100 has been reset, a counting output is generated from a self hold circuit 104. As a third feature, the counting apparatus is used as timer circuits 203, 300, 400, and the generation frequency of a rotation detection pulse signal I.sub.P based on a sensor signal, is obtained to thereby detect a rotation-stopped condition of a rotating body.

Abstract: Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc>d2>d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).

Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.

Abstract: A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through corresponding OR gates. A source of preload signals is coupled with the second inputs of the OR gates; and a combined trap detector and terminal count detector has inputs coupled with the outputs of the last n-1 stages of the shift counter circuit and an output coupled with the source of pre-load signals to operate it.

Abstract: An image forming apparatus supervisory system is provided. The image forming apparatus supervisory system includes an image forming apparatus and a control device. The image forming apparatus has an input unit for inputting an identification code and a transmission unit for transmitting the identification code. The control device is connected to the image forming apparatus, and has a reception unit for receiving the identification code and a transmission unit for transmitting to the image forming apparatus a signal for informing the image forming apparatus of a permitted number of time an image can be formed in response to receipt of the identification code. Upon receipt of the signal from the control device, the image forming apparatus permits forming an image the permitted number of times.

Abstract: A frequency gain display apparatus for an L/C band frequency up unit which is capable of generating a pulse for adjusting the gain of an L/C band frequency up unit used in a satellite system and a pulse for selecting a band width of a SAW (surface acoustic wave) filter and is capable of displaying a gain step of the same.

Abstract: The present invention relates to a control means for a printing machine, in particular a sheet-fed offset printing machine, having a plurality of units, such as feeders, printing units, varnishing and coating devices, deliverers, folding apparatus and the like, each unit being assigned a station having at least one computer and these stations being connected to one another via a first bus. It is intended to ensure that the switching processes which are to be carried out in the individual units of the printing machine at specific, predetermined angle positions can proceed exactly, even at the highest machine speeds. According to the present invention, for this purpose it is proposed that, in addition to the first bus, via which the stations exchange signals with one another, a second bus is provided, via which the individual stations may be fed with the angle position signals of a single-turn rotating angle encoder which is fitted on one unit of the printing machine.

Abstract: In an FPGA having registers which are part of a user's logic functions and a configuration memory which is read and written through an addressing structure, a register protect circuit controllably protects the contects of these user logic registers from being modified by signals from the user's logic, allows these registers to be written by a microprocessor through the configuration memory addressing structure, and allows both the user's registers and lines which provide combinational signals to be read by a microprocessor through the configuration memory addressing structure.

Abstract: A detector system filters the effects of periodic noise such as magnetic flux from nearby power lines or other periodic sources. The detector system further adapts in the case that the system incorporates microloops for the inductive sensors. The detector system further counts multiple vehicles while in presence mode. The detector system also logging of vehicle data and system faults.

Abstract: A ring counter includes a plurality of latches forming a shift register. A single bit is sequentially clocked through the shift register, so that only one output is active at any time. A logic circuit is connected to the outputs, and monitors the number of outputs which are active. If more than one output should somehow become active at one time, such as during power up, a reset signal is immediately generated to reset a single bit of the counter active. An external reset signal can also be applied to the logic circuit to force a reset of the counter.

Abstract: A computerized parking meter uses an ultrasonic transducer to precisely measure the distance to a parked vehicle and to reset the parking meter to zero when the vehicle leaves. The computerized parking meter utilizes low power and may be recharged by solar power. The computerized parking meter can be programmed with differing rates, calendar days, advertising and alarms. Unlocking the coin box requires both the proper computer code and a key. When the computerized parking meter receives the proper computer code a solenoid is activated which retracts a plunger allowing the key to unlock the coin box. A coin discriminator allows only proper coins to be inserted into the meter. Audible messages and alarms can be sounded and written messages displayed. A portable terminal can communicate with a central computer to enhance collections security and identify repeat parking violators.

Abstract: A counter system having associated counter error detection circuitry that utilizes the current parity, the previous parity, and a predicted parity for evaluating counter operation is described. In successive count cycles, a predicted parity is utilized, during the next subsequent count cycle is stored in flip-flop as the current parity, and in the next subsequent count cycle is stored a second flip-flop as a previous parity. Circuit are described for performing parity check and parity prediction functions. The previous parity, current parity and predicted parity will not be alike for any binary counter that operates properly. Circuity is described that holds and compares the parity of the Count, the current parity, and the previous parity, during each counter advance cycle and to provide an error signal when the counter is detected to be stuck.

Abstract: A method apparatus for determining the length of a roll of sheet material, including a side surface at which the edge of each of the plurality of layers of sheet material is exposed wherein the side surface of the roll of sheet material is exposed to a source of radiation and the radiation reflected from the edges of the roll is scanned in a radial direction to establish a first signal indicative of the reflected radiation and the number of edges of layers of sheet material. The length of the roll of sheet material is calculated using the sensed number of layers of sheet material in the roll. The method and apparatus are similarly adapted to determine the number of layers of sheet material in a stack of sheet material.

Abstract: An apparatus and method for determining a time that a system's main power was inactive includes a counter circuit (171) for accumulating transitions of a clock signal (149) while the system's main power (117) is inactive. Preferably, another circuit (159, 125) determines a periodicity of the clock signal (149) after the system's main power (117) transitions active. Then a computational circuit, preferably a microcontroller (129), determines the time (183) that the system's main power (117) was inactive dependent on a number of transitions of the clock signal (149) accumulated by the counter circuit (171) when the system's main power (119) was inactive and the determined periodicity of the clock signal (149) after the system's main power (117) transitions active. Preferably, this apparatus and method are used in a vehicle to determine how long a time that an engine is turned off and to modify an engine control strategy dependent on that determined time.

Abstract: A counter has a memory which stores at least three continuous numerical values and a controller which rewrites a lowest numerical value to a numerical value obtained by adding 1 to a largest numerical value within said continuous numerical values stored in the memory and discriminates whether or not said numerical values stored in the memory are continuous to judge a count error. When said numerical values stored in the memory are not continuous, the noncontinuous numerical value is corrected by adding 1 to the largest value of other continuous numerical values stored in said memory.

Abstract: Traffic monitoring equipment including traffic speed measuring equipment has a signal validation facility incorporated to enhance reliability of the equipment. This facility permits the monitoring operation, for example speed measurement, to proceed only if the validation is positive, if negative the operation is aborted and/or a warning signal or shutdown is activated. Validation is made of pulse sequence, pulse strength, radio frequency interference, insulation breakdown, cable integrity (where cables are used) and the like.

Abstract: A race-free arithmetic operation circuit is disclosed. The circuit comprises a register file array, an arithmetic logic unit (ALU), and apparatus for controlling the input and/or the output signal of the ALU. The apparatus for controlling can be two level-sensitive latches, located before and after the ALU, or one master-slave flip-flop, located either before or after the ALU.

Abstract: A rotor movement sensing system in a postage meter permits detection of the printing of postage even if power is lost during the printing cycle. A sensor senses a magnet on a disk when the rotor is substantially past its home position. A second sensor has a magnetic memory element. When the magnet on the disk passes near the memory element, that element is magnetized. A Hall-effect sensor at the memory element provides an interrupt to a processor to indicate magnetization of the memory element. A winding is provided around the memory element. The processor has an output which, when asserted, causes current flow through the winding, demagnetizing the memory element. Alternatively a reed switch senses rotor rotation, a flip-flop provides a bistable latch and its output provides a datum for the processor.

Abstract: A signal generating circuit includes a counter for counting up input clock pulses to output a trigger signal when counting up to a predetermined number of pulses, a CPU for outputting a mask request of a first trigger signal, a first flip-flop for storing the mask request of the CPU, a second flip-flop for latching a normal output signal of the first flip-flop by the trigger signal of the counter, and an AND circuit for calculating a logical sum of a mask request signal output from the second flip-flop and the trigger signal output from the counter. Thus, the trigger signal generating circuit masks the first trigger signal output from the counter and prevents the output of a superfluous trigger signal when a timing of a trigger signal generation is delayed.

Abstract: The disclosure relates to counters that require the counting to be done under conditions of high security. In such a counter, starting from a number represented by a certain number of bits, the stages of the counter are successively forced, one after the other, to represent the final number in an order such that at no instant do the contents of the counter represent a number smaller than the initial number. A particular structure is used to count very big numbers while, when the technology is of the EEPROM type. This prevents the stage that changes its state most frequently from being subjected to action more than is physically permitted by the technology used. The disclosed method makes it possible, in chip cards, to prevent the diminishing of memorized values representing substantial values which are, for example, monetary values.

Abstract: A new technique for testing the counting functionality, loading functionality, and operational speed of a binary counter is provided wherein additional logic is incorporated into the counter to enable the counter to be functionally tested with a minimum number of clock cycles. Thus, for an n-bit counter which is partitionable into k subcounters, the counting functionality and operational speed of the counter may be tested in at most 2.sup.n/k +2 clock cycles, and the loading functionality of the counter may be tested in at most 2.sup.n/k +1 clock cycles.

Abstract: A system for defining and controlling data transmissions in a multiplexing system having a host controller in bi-directional communication with a plurality of remote stations or nodes. The system comprises a series of simple frame flags generally defined as varying periods of inactivity on the bi-directional transmission line. Only specified numbers of transmitted data digits constitute valid transmissions. An arrangement is provided which responds to the receipt of an incorrect number of received digits (an error condition) in a manner which is a function of the number of digits which are actually received.

Abstract: An apparatus is disclosed that provides control of access to a module. In particular, the module should not be accessed while in a busy or unstable state. The module disclosed herein, by way of example, is a timer module. Access to the timer is controlled by the disclosed apparatus while the timer is changing state.

Abstract: A telephone network interface integrated circuit with digitally based loop current detection and digitally based ring signal detection. The ring signal detection includes discrimination with a cutoff frequency of about 13 Hz to distinguish ring signals from dialing signals. The discrimination includes filtration followed by triggering an oscillator for one time period and checking whether the number of oscillations exceeds a threshold.

Abstract: A multi-featured first-in-first-out (FIFO) memory device on a monolithic semiconductor integrated circuit chip. The FIFO device is bi-directional, in that the user may select the direction of data transfer through the device. The device may be configured in a transparent bypass mode of operation, wherein the FIFO memory array is bypassed, and data is transferred directed from either device input/output port to the other device input/output port. In another mode of operation allowing registered bypass operation, a byte of data may be written in an internal register from the device port being used to output data for later transfer to the device port presently being used to input data to the FIFO memory array. The FIFO device further includes a user-testable mode of operation, wherein data written into the FIFO memory array through a device input port may be read out of the same device input port.

Abstract: An electrical apparatus (e.g., copying apparatus) equipped with a counter for counting the number of specific cycles. Allowance or prevention of an operation cycle is controlled in accordance with voltage changes at a predetermined position of the controlling circuitry supplying a driving voltage to the counter. A specific operation of the electrical apparatus is enabled by connection of counter.

Abstract: A data detector comprises a counter having a plural-bit parallel output, compensation means for compensating a shift of output times of a low order bit and a high order bit of the counter caused by a carry signal from the low order bit to the high order bit, and detection means for detecting data of the low order bit and the high order bit of the counter compensated by the compensation means.

Abstract: A high speed digital counter that can be easily tested comprises a plurality of subcounters having an input for receiving an incrementing signal and a carry output for outputting a carry signal when the subcounter has reached its counting capacity. The carry output of each subcounter is gated to the input of a next more significant subcounter by an OR gate which receives as inputs the carry signal and a test signal. The OR gate performs an OR on these two signals and outputs the result to the input of the next more significant subcounter. The OR gate allows the test signal to access each subcounter separately, and thus, each subcounter may be tested individually.

Abstract: A first frequency dividing circuit receives an input clock signal from an input terminal and divides the frequency of the input clock signal to produce a first signal which it supplies to an output terminal. A second frequency dividing circuit divides the frequency of the input clock signal to produce a second signal having the same frequency as the first signal but differing from the first signal in phase. The second signal controls a gating circuit. When switched on, the gating circuit connects the output terminal to the input terminal, or to an auxiliary power-supply or ground terminal, thereby deskewing the signal at the output terminal.

Abstract: An input to the control unit of a microprocessor places the microprocessor in a WAIT condition whenever the input clock frequency is determined to be less than a predetermined minimum value. A timing circuit which includes a relatively high capacitance device generates a "kill" signal whenever the time interval between successive clock pulses is greater than a value corresponding to a cut-off frequency. The kill signal is applied to the control unit of the microprocessor and cannot be reset except with a system reset.

Abstract: A can end counting system which receives a stick of converted can ends, separates and counts the can ends, restacks and conveys a pre-determined number of can ends comprising an output stick to an end line packaging station. At least two counter-rotating screws, each having a separator knife positioned at the entrance end thereof, are provided with a continuous spiral groove cut into the periphery and coact with each other to separate the can ends, one by one, from an input stick and increasingly separate the can ends as they are carried toward the exit end of the device. A sensing device senses each of the can ends as they are carried toward the exit end of the device and sends a signal to a processing device which stores the total number of can ends included in a current output stick and controls a cut-off knife which separates and conveys the output stick toward an end line packaging station when a pre-determined number of can ends is attained.

Abstract: A phase lock loop monitors the frequency of redundant input clock signals and switches back and forth therebetween should one or the other become invalid. Thus, the PLL may continue normal operation even with a failure of one input clock signal. If both the input clock signals fail, an internal reference signal maintains the PLL at a nominal operating frequency until one of the input clock signals is restored whereby the loop can quickly re-establish phase lock. To determined validity, the input clock signals are sampled and stored by the reference signal in a predetermined manner. The input clock signal is valid if the samples of the input clock signal each have the same logic state after the sampling period; otherwise, the input clock signal is invalid if the samples of the input clock signal have at least one different logic state after the sampling period.

Abstract: A power unit assembly comprising an internal-combustion engine, a mechanical, unsynchronized gearbox, a clutch interposed between the engine and the gearbox, an inertia brake in which the gearbox, the relevant synchronization by means of the engine or the inertia brake and the control of the injection pump for the engine are controlled by an electronic processor adapted to inhibit the engagement of gear ratios to which an engine speed corresponds which does not fall within a programmed range of normal values; the processor is adapted to detect emergency operating conditions and, in such a case, to allow the engagement of a gear ratio which results in an engine speed value above said programmed range of values; to ensure synchronization even under such conditions the injection pump is provided with adjustment means adapted to allow speeds to be attained which are close to the upper limit of mechanical integrity of the engine.

Abstract: A watchdog timer capable of detecting clock signals when the opening frequency of a frequency source drifts lower or higher than a normal desired operating range, increasing circuit safety and reliability. The timer uses first and second clock oscillation circuits to generate first and second signals of frequencies f.sub.1 and f.sub.2 which are then divided by 1/N.sub.1 and 1/N.sub.2 in first and second frequency dividers, respectively. Third and fourth frequency dividers are used to divide the second frequency signal f.sub.2 by 1/N.sub.3 and 1/N.sub.4, respectively. A scale of N.sub.5 counter is connected to receive the f.sub.1 /N.sub.1 frequency signal as a clock input and the f.sub.2 /N.sub.3 frequency signal as a reset input, and provides an output signal at a frequency of (f.sub.1 /N.sub.1)/N.sub.5 which is less than f.sub.2 /N.sub.3 when the clock circuits are operating under normal conditions. A scale of N.sub.6 counter is connected to receive the f.sub.2 /N.sub.

Abstract: A circuit system for preventing a measuring device such as an engine speed measuring device or the like from being erroneously operated includes as essential components a filter circuit, a Schmitt trigger circuit, an oscillating circuit, a counting circuit, a pulse monitoring circuit and an adding circuit. A combination of the filter circuit and the Schmitt trigger circuit serve to properly shape a wave form of each of a series of pulse-shaped sensor detection signals. The oscillating circuit generates a series of pulses each having a reference frequency. The pulse monitoring circuit monitors a wave-form shaping output pulse by counting the number of a series of output pulses each having a reference frequency for a predetermined period of time with the edge of the wave-form shaping output pulse as a trigger.

Abstract: Disclosed is a pulse counting circuit for counting pulse signals comprising a first pulse signal generating means for generating a first pulse signal corresponding to an input signal, a counting means for counting at least either of said first pulse signal and a second pulse signal which differ from said first pulse signal corresponding to said input signal, said first pulse signal possessing a pitch set smaller than that of said second pulse signal, and a control means for selectively controlling the operation of said count means for counting said first and second pulse signal.

Abstract: An input to the control unit of a microprocessor places the microprocessor in a WAIT condition whenever the input clock frequency is determined to be greater than a predetermined maximum value. An RC circuit in combination with a Schmitt trigger generates a "kill signal" whenever the time interval between successive clock pulses is less than a value corresponding to a cut-off frequency. To assure that the microprocessor is not placed in a WAIT state by an occasional "glitch" on the clock input, the kill signal applied to the microprocessor control unit is provided from a four-bit counter. If the Schmitt trigger generates a kill signal on eight consecutive clock cycles, the counter output changes state and sequencing of microcode by the control unit is suspended.

Abstract: A counter includes an array of memory cells arranged in groups of memory cells, each group designating a counting decade, wherein each group of memory cells includes first and second word strings, each capable of storing a data word, and a fault flag, capable of indicating which word string contains the data word; sensing means coupled to the memory array for checking the status of the memory cells and for generating fault signals upon detection of a fault in a memory cell; logic means coupled to the memory cells and to the sensing means for selecting the first or second word string in response to a fault signal; wherein upon detection of a fault in a first word string, the data word is written into the second word string; and a central shifting unit coupled to the memory array for reading a data word stored in a word string into the shifting unit, incrementing the data word, and writing the incremented data word into its respective word string.

Abstract: A device for counting the number of very small projections on a surface of an object, which includes a casing therein housing a probe to be scanned in contact with the surface of the object having continuously occurring very small projections, a tip end portion of the probe being projected out of a forward end of the casing; a detecting unit including an acceleration sensor; a comparator for converting electric signals emitted from the detecting unit into pulse signals; a latching device provided with a delay circuit for latching the pulse signals received and maintaining its emitted signals for a certain length of time; and a display device for counting and displaying the output signals from the latching device.

Abstract: An electrochemical counting device in a casing, which contains counters that may be switched by a drive. The drive is connected to a switch armature, which engages a stepping wheel to shift the counters. The drive is also provided with two swivel arms, which are not mechanically connected. Each swivel arm is equipped with a spool. In order to shift the counters, both swivel arms are pivotable oppositely directed in a synchronized manner, perpendicular to the pole face of the permanent magnet. The permanent magnet is arranged between the two swivel arms. Both swivel arms are supported at the casing by a spring. The swivel arms cannot be pivoted accidentally towards each other due to impact and therefore cannot accidentally shift the counters. The electromechanical counting device may therefore be employed, where sudden impact or magnetic interference may occur.

Abstract: Apparatus and method for counting frequency of a signal with improved resolution. Frequency counters (10, 60, and 100) accumulate clock cycles from a reference oscillator (20) during a sample interval. In the simplest form of the frequency counter, the reference clock signal is inverted and both the noninverted and inverted clock cycles are accumulated in separate counters (40 and 44). The accumulated counts are totaled in a summing circuit (48) and divided by two to determine their average, thereby doubling the resolution of the frequency counter. A more complex embodiment of the invention corrects a raw count of cycles of an input signal (12) that are accumulated during an extended sample interval defined by successive rising edges of a sample signal (114).

Abstract: A dual-edge frequency counter and method for minimizing the effects of duty cycle modulation. In its simplest form, a dual-edge counter (50) includes a first counter (52) that accumulates reference clock pulses between successive rising edges of an input signal. An input signal is also applied to an inverter (54), which inverts the square wave signal prior to applying it to a second counter (56) that also accumulates reference clock cycles between successive rising edges of the inverted sensor signal. A summation junction (60) totals the accumulated counts from the first and second counters so that they can be averaged by a divider (62), which divides the total count by two. The technique is also employed in connection with a frequency counter that includes an integer counter (72) for totaling the number of cycles of the sensor signal occurring during a sample time defined by successive gate signals.

Abstract: An event counter has dual counting channels, each employing a ripple counter, and a timing generator supplying square wave switching signals of opposite phases to gates at the inputs of the two counters, the switching signals having a much greater periodicity than that of events to be counted, so that one, and only one, of the counters is counting at any one time. The timing generator also generates control signals to transfer a count from whichever counter is inactive to an associated latch and then reset the counter. When a counter is again enabled, the switching signal is also used to enable output from the latch of the previously stored count. This arrangement enables ripple counters to be used in an arrangement providing both continuous counting and continuous output availability.

Abstract: An autoclave or other equipment has a counter provided by an EEPROM for counting the number of times the autoclave has been used. The EEPROM has a first set of ten registers which contain the unit value of the count together with a fault code associated with the last use of the autoclave. Two further registers contain the hundreds and tens, and the ten thousands and thousands value of the count. The tens value in one of the further registers is used to determine in which of the registers of the first set the units value is stored, so that each of the registers in the first set is only written into ten times for every hundred counts, thereby extending the life of the EEPROM. Another register in the EEPROM contains information about the nature of the autoclave.

Abstract: Registers are inclined to react to any interference as follows: if any one stage inverts, the entire register inverts. In one embodiment, one additional bit is associated with the register, which bit is used to indicate that interference has occurred. Registers may then be inverted to their original form or may, by equating the meaning of the inverted form of the information contents of registers to the original form, ignore disturbance(s) caused by interference. Information media such as magnetic or optical discs for storage of such information thereon are also disclosed. The invention brings order to information failures caused by interference and thus is able to use such failures as opposed to other approaches which fight such failures. The invention avoids the need to keep track of original and inverted forms of information, independent of interference.

Abstract: A frequency divider circuit having N flip-flops connected in series, includes a logic circuit for monitoring at least one of the outputs of the N flip-flops and halting the frequency division operation of a prior stage flip-flop when the value of the output which is monitored is equal to a predetermined value when a reset signal is input, and restarting frequency division operation when the reset signal is cancelled.

Abstract: A two-modulus variable frequency-divider circuit comprises a variable frequency-divider, a plurality of .div.2 frequency-dividers succeeding the variable frequency-divider, and a monitor. Outputs of one or more of the .div.2 frequency-dividers are coupled to the monitor which develops a monitor output determined by the states of the .div.2 frequency-divider outputs applied thereto. The monitor output is fed back to the variable frequency-divider as a frequency dividing factor setting signal. The two-modulus variable frequency-divider circuit is further provided with a signal converting circuit having a signal inverting function, which can selectively invert, in accordance with an externally applied control signal, the output of the two-modulus variable frequency-divider circuit or the output of the final one of those .div.2 frequency dividers which provide the outputs thereof to the monitor.

Abstract: An asynchronous ripple counter counts from a predetermined binary value to zero in response to an input clock signal. Zero detection logic is coupled to the ripple counter for detecting, from a most significant bit to a least significant bit of the ripple counter, when the counter has counted to zero. Both the counter and the zero detection logic receive and store the predetermined binary value. The monitoring of the ripple counter's digits from MSB to LSB prevents false detections of zero states in the ripple counter and allows the ripple counter to be extended to an arbitrarily large number of bits without sacrificing the maximum input clock frequency.

Abstract: A system for determining the position of movable machine parts including an incremental pulse generator for generating angular-speed pulses includes a computer. At least one counting circuit via which the incremental pulse generator is connected to the computer counts the generated angular-speed pulses.