Abstract: A card counter (10) prints card inventory information locally and communicates with a remote computer (43) for permanent storage and retrieval of inventory information. A microprocessor controller detects a counting error in response to the actual count failing to match a preset count, failing to match a precount information machine read from a machine readable precount label (130) attached to the cards (18), in the event of a phrase error from a pair of parallel scanning card sensor circuits (58, 59) or if the final counts of the two card sensor circuits (58, 59) do not match. In the event of detection of a counting error, an error indication is provided and entry of the count into an accumulator memory is inhibited. The present number is entered into memory by selectively entering an actual count into the preset memory. A pair of separate accumulators are provided for concurrently accumulating totals of two different groups of cards (18).

Abstract: A redundancy circuit that substitutes a redundant circuit element for a corresponding defective circuit element includes a severable fuse link and a redundancy control circuit with an input connected to the severable fuse link and first and second outputs. When the fuse link is intact, the first output of the redundancy control circuit is in a first state and the second output is in a second state. When the fuse link is severed, a momentary signal on power up places the first output in the second state and the second output in the first state. The first output is coupled to the one circuit element and the second output is coupled to the corresponding redundant circuit element. If the one circuit element is defective, it is disabled by severing the fuse link.

Abstract: A card counter (10) prints card inventory information locally and communicates with a remote computer (43) for permanent storage and retrieval of inventory information. A microprocessor controller detects a counting error in response to the actual count failing to match a preset count, failing to match a precount information machine read from a machine readable precount label (130) attached to the cards (18), in the event of a phase error from a pair of parallel scanning card sensor circuits (58, 59) or if the final counts of the two card sensor circuits (58, 59) do not match. In the event of detection of a counting error, an error indication is provided and entry of the count into an accumulator memory is inhibited. The preset number is entered into memory by selectively entering an actual count into the preset memory. A pair of separate accumulators are provided for concurrently accumulating totals of two different groups of cards (18).

Abstract: An end-around coupled chain of n bit counter stages, including an inversion element in the chain, employs a detection/correction mechanism for an invalid counter position. A "1,0" state pair is detected in the highest order two bit stages and the simultaneous occurrence of any "1" state in an adjacent group of at least J stages (where J equals the integer part of the number of stages divided by three) indicates an invalid counter position. At least said adjacent group of bit stages is set to "0" in response to the detection of an invalid counter position.

Abstract: A counter comprising n one-bit cells receiving a clock signal (CK0) having a frequency f to be counted and a read transfer order (TO). The lower rank p cells operate at the frequency f and the n-p higher rank cells at a frequency f/2.sup.p. The lower rank p cells (51-53) directly receive the clock signal (CK0) at frequency f and, if necessary, the transfer order (TO) synchronized in correspondence with CK0. The higher rank n-p cells receive as a clock signal at frequency f/2.sup.p, a signal (CK1) delayed by at least two periods of said clock signal CK0 and at the most by (2p-2) pulses CK0 with respect to the counting signal of the highest rank cell among the lower rank p cells.

Abstract: A method and device for evaluating signals of an incremental pulse generator for generating at least two mutually phase-shifted angular speed signals includes counting the angular speed signals only if a permissible combination of the angular speed signals is present.

Abstract: A counting device determines the number of similar articles, or parts, passing a detector. The device is especially useful in packaging small parts into containers, and in insuring that each package contains the correct number of parts. The counter is preferably of the type in which the parts interrupt a beam of light, changing the current through a photoelectric cell. When the current in the photoelectric cell falls below a predetermined threshold level, the device generates a pulse which indicates the presence of a part. The pulses are counted electronically. The device preferably includes a microprocessor which can efficiently control the counting, calibration, and diagnostic operations. The microprocessor stores information relating to the threshold current level, for a given type of part. The value of the threshold can be determined by a separate calibration procedure.

Abstract: An apparatus for measuring the frequency of a pulse train signal and method therefor applicable to a speedometer of a vehicle are disclosed in which a count value C of at least one counter which counts number of pulses in the pulse train signal for predetermined counting intervals of time .DELTA.T (=T/n, wherein T denotes a frequency measuring time interval and n denotes a calculation constant) is updated to a value related to the count value for each predetermined counting interval of time .DELTA.T and stored and outputted for each predetermined counting interval of time .DELTA.T so that the same or better performance as that using a stagger ring method can be achieved. The value is expressed by (C-C/.alpha.) in a first preferred embodiment (wherein .alpha. denotes the calculation constant preferably equal to n), by (C-C.times.m/.alpha.+D) in a second preferred embodiment (wherein m denotes the number of counters and D denotes the latest count values of the m counters during .DELTA.

Abstract: A count error detecting device for count type measuring instruments is provided with a phase-shift circuit producing two N phase interpolation signals shifted in phase by 45.degree. from two signals in phase by 90.degree. each other; a plurality of comparators converting the two N phase interpolation signals into pulse signals; a pair of coincidence circuits connected to the comparators; a pulse discriminator circuit connected to the coincidence circuits; a counter circuit connected to the pulse discriminator circuit; and a flip-flop connected to one of the coincidence circuits and the pulse discriminator circuit. Thus, a circuit configuration of the device is facilitated, the ability of a detector can be fully displayed, and measurement efficiency can be widely improved. A conventional count error detecting circuit may be connected to the count error detecting device as an alarm circuit.

Abstract: Generally there is provided circuitry and a method for frequency multiplication of a first signal source including a first counter for counting pulses from a second signal of higher frequency by counting from a loaded value and generating a circuit output each time the first counter resets. A second counter is used to count cycles of the first counter and generate a feedback signal when a predetermined number of cycles have been completed (the system multiplication factor). Calibration is achieved by comparing the end of the period of the first signal to the occurrence of a feedback signal. In response the comparision circuit causes the loaded value to be changed to thereby control the output.

Abstract: Error rates above a given threshold are detected by initiating a counter to count a group of n bits on each occurrence of an error bit. The counters are inspected on each occurrence of an error to see whether the counter initiated x error bits earlier is still counting. If the counter is still counting the error rate is above a threshold of x error bits in a group of n bits in a serial stream.

Abstract: Described herein is a dynamic latch circuit having a pair of control terminals connected to receive complementary first and second control clock pulses which are generated at a predetermined frequency, and a register section for detecting the voltage of an input signal, in response to each of the first and second control clock pulses, and generating an output signal from a capacitive output node which is charged or discharged in accordance with the voltage of the input signal and is subsequently set at a low potential or a high potential. The latch circuit further comprises a voltage-generating circuit for detecting, based on a period of time elapsed from the trailing edge of the last generated first control clock pulse, that the supply of the first control clock pulses has been stopped and fixedly setting the output node at the low potential.

Abstract: An initial value setting system for an electronic device having system clearing means for generating a trigger pulse in response to power source voltage fluctuation, counter means for counting intervals between the trigger pulses generated successively by the system clearing means, and initial value setting means for undergoing an initialize operation of the electronic device in response to the counter means. In accordance with the present invention, an erroneous execution of all-clear due to electrostatic disturbance noise can be prevented by counting interval or number of the trigger pulses, and discreminating whether or not the initial value setting means should be operated.

Abstract: Input pulses are applied to toggle a first bistable whose output provide clock signals to a monostable timer whose period is set to the duration of one cycle of the input pulse a a critical frequency. A second bistable enables a third bistable and a counter only if an edge of a pulse from the timer occurs in an interval of the clock signals from the bistable. Thereafter the counter is clocked by pulses which are derived from the clock signals of the first bistable by the third bistable. The counter provides an indication after a predetermined number of the input pulses which have reached the critical frequency. An output signal derived from the indication may be maintained by a fourth bistable.

Abstract: Disclosed is a combination of a counter operating in response to an input signal, a latch circuit for latching the output of the counter and a read-command signal inhibiting circuit controlling the latch circuit so as not to effect the latch operation for a predetermined period from the input signal for a time necessary for the operation of the counter, in response to a read-command signal.

Abstract: Sampling pulses for determining a series of measurement periods are each synchronized, by a synchronizing circuit, with one of a plurality of input signal pulses to be measured. A first counter responds to the synchronized sampling pulse to start the counting of the input signal pulses. When the first counter has counted a predetermined number M of input signal pulses, a second counter starts counting the input signal pulses at the initial value M and stops the counting in response to the next synchronized sampling pulse. The count value of the second counter is applied to a display during the next counting of the input signal pulses by the first counter up to the predetermined number.

Abstract: A glitchless terminal count indication digital counter having a clock signal as an input thereto is disclosed and comprises a state logic means comprised of a plurality of DQ flip-flops for providing a digital count with the clock signal being sent to an input thereof, a next state decode means, a next terminal count decode means for providing an indication at its output that the digital output count will reach a terminal count at the next clock cycle, and a terminal count logic means for obtaining the indication from the next terminal count decode means and providing therefrom at the next clock cycle a glitchless terminal count indication. The next state decode means has inputs and outputs, with the digital count being an input thereto, and the state logic means and the next terminal count decode means being coupled to the output thereof.

Abstract: A circuit arrangement for monitoring a binary signal having at least one level shift within a characteristic waiting time, such circuit including two flip-flops which receive control pulses at intervals at least as long as the characteristic waiting time. In order to enable the two flip-flops to employ the same clock pulses, a gate circuit is assigned to each of them, the output of which is connected to the data input of the assigned flip-flop. If a control pulse is present, the first gate circuit ensures that the first flip-flop can switch to its set state, while the second gate ensures that the state of the second flip-flop is switched to the inverse of the state of the first flip-flop. If a control pulse is not present, the first flip-flop can only be switched to its reset state when the binary signal to be monitored has the binary value 1, while the second flip-flop cannot switch from its existing state.

Abstract: A circuit arrangement for adding, storing and reproducing electric counting pulses, is suggested, which preferably serves as an electronic kilometer counter of a motor vehicle with a distance transmitter (10). The circuit arrangement comprises an overwritable nonvolatile storage (16) which is divided into a series of storage registers (19) in which the counting pulses are stored by a one-unit shift code. When erroneous information occurs in any storage cell, the error of the indicated storage contents amounts to a maximum of .+-.1. This is achieved in that the control circuit (13), beginning with the first register (14), writes each new counting pulse into the next register (13, 12 . . . ) and, after reaching the last register (0), increases the contents of the first register and then the following respective registers by one unit with the next counting pulses. Such a circuit arrangement is to be used as a kilometer counter, operating time counter, quantity or piece counter, and the like.

Abstract: A time of day coincidence system for coinciding time of day values of a plurality of apparatuses includes a clock pulse generator for generating clock pulses having a predetermined interval, a TOD time of day timer controlled by the clock pulse, a time of day correction signal generator for generating a correction signal in a predetermined interval which is a predetermined multiple of the count cycle of the TOD timer. The clock pulse generator, the TOD timer, and the time of day correction signal generator are arranged commonly for the apparatuses. The system also includes a counter, a count of which is incremented in response to the clock pulse, a time of day read and set unit for reading out current time of day information from the TOD timer in response to an external instruction and setting the time of day information in the counter, and a time of day correction unit for correcting the count of the counter in response to the correction signal in accordance with a predetermined rule.

Abstract: An integrated circuit with a frequency dividing test function includes a first frequency dividing circuit which divides a given frequency signal, a second frequency dividing circuit for dividing the output signal from the first frequency dividing circuit and a single terminal receptive of external test clock pulses. A test circuit is connected to the reset terminal for inhibiting the output signal from the first frequency dividing circuit when the external test clock pulses applied to the reset terminal have a higher frequency than the divided frequency of the first output signal and for applying the external clock pulses to the second frequency dividing circuit to test the second frequency dividing circuit.

Abstract: A method of analyzing the voltage induced in an exciter coil of a stepping motor. After energization the exciter coil is loaded by a low impedance so that the induction voltage can produce a current. Subsequently, it is attempted to maintain the current through said coil equal to zero by periodically connecting said coil to a positive or negative voltage. The pattern of consecutive polarities of these periodic energizations is analyzed.

Abstract: A counter circuit for counting pulses inputted thereto asynchronously during a fixed period includes a counter 12' for counting the input pulses, a register 13 for storing pulses outputted by the counter 12' at fixed periods, and a control circuit 11' for generating a signal that controls the operating state of the counter 12' and register 13. When a signal that decides the operating period of the counter 12' is not being generated, namely between pulses indicative of the operating period, the counter 12' performs an ordinary counting operation. If an input pulse for counting is applied to the counter 12' during a period of time in which the abovementioned pulse is being generated, the control circuit 11' causes the counting operation to continue without clearing the counted value in the counter 12', after which the counted value in counter 12' is outputted to the register 13 to be latched therein, thereby preventing miscounting in the register 13.

Abstract: A delay circuit for a data manipulation circuit is provided in which data update signals to the data manipulation circuit are delayed when a data access signal is present so that data is not manipulated during accessing of the data.

Abstract: An apparatus for automatically counting stacked sheet-like materials having sheet-to-sheet brightness gradients alternating between positive and negative while simultaneously eliminating problems encountered when the sheet edge reflectance characteristics have combined lambertian and specular reflective natures. Rectification of a pitch matched sensor arrays data output combined with a selective disposition of the sensor and illumination optical components relative to the sheet edges to be counted based upon the maximum acceptance angle of the optical system yields the improved count data necessary to achieve accurate counting.

Abstract: In a counting circuit having non-volatile electrically erasable memory elements and a plurality of similar counters each representing one place of the count, respective memory elements of suitable capacity are associated with the counters. Low value counters can be connected cyclically to each other via their counting inputs and transfer outputs. Their association with the other places of a count is changed as a function of the count of the highest-value place. In this way, the result is obtained, without additional expense for memory, that the individual memory elements are erased equally frequently during the life of the counting circuit.

Abstract: A multistage counter circuit comprising a plurality of counters connected in cascade, each providing a carry signal and having signal logic levels at an output of each stage inverted by main clock pulses and sub clock pulses, and means including a flip-flop connected at the output of each stage for synchronizing the carry signal of each stage with the main clock pulses to generate a carry signal to a succeeding stage unafffected by delays in the carry signal of a preceding stage.

Abstract: A FIFO status circuit suitable to detect the full or empty status of a RAM based FIFO which is asynchronously addressable by write and read access signals. The circuit detects whether the preceding addressing of the FIFO was a read or a write operation to determine whether the FIFO is empty or full. In one form, the trailing edges of the FIFO write and read signals trigger respective pulse generators. Short duration matched pulses drive the corresponding set and reset inputs of a flip-flop. The out Q and Q outputs from the flip-flop are coupled individually to a pair of AND gates. Each AND gate is also driven by a FIFO equal signal, a signal which indicates that both the read pointer and write pointer of the FIFO memory are directed to the same address. Because the FIFO equal signal is stable before the pulses reach the flip-flop, it serves to mask metastable conditions which may arise in the flip-flop.

Abstract: A frequency divider for converting an n-bit periodic counting stream (each period containing a single zero or one bit, respectively, followed by n-1 one or zero bits) into a 2n-bit counting stream includes a two-input NOR gate or NAND gate, respectively, connected for delivering its output to an n-bit delay device, the NOR or NAND gate further connected for receiving the output of the delay device as feedback at one of its two-input terminals and for receiving the n-bit counting stream at the other of its two-input terminals. The output of the delay device is then a 2n-bit counting stream.

Abstract: A counting circuit includes a digital counter for counting the pulses of an input signal during a counting interval and a pair of digital latches for latching the binary state of the input signal at the beginning and end of the counting interval, respectively. The latched binary states of the input signal and the pulse count of the digital counter are evaluated by an interpreter such as logic circuitry or a microprocessor. The interpreter resolves the pulse count into half clock cycles by comparing the binary states and in response adjusts the pulse count by the addition or subtraction of half a clock cycle.

Abstract: Counter circuit apparatus which sequentially re-allocates lower-order counting operation in order to extend counter life. The counter is comprised of a plurality of lower order counters and at least one higher order counter. A count selection circuit is coupled to the plurality of counters which controls the counting thereof in response to applied event input signals. A map control circuit is coupled between the higher order counter and the count selection circuit which controls the count selection circuit in response to signals derived from the higher order counter. The map control circuit sequentially enables a predetermined one of the lower order counters to count individual ones of the applied event input signals. A count unscrambling circuit is coupled to the plurality of lower order counters and the map control circuit which produces an ordered count output signal that is indicative of the number of event input signals counted by the counter.

Abstract: A register of the type used on as address counter in a dynamic RAM is tested by a method which does not require cycling through every possible value of the register contents. The counter is first loaded with a fixed value, all 1's or all 0's, and the contents checked by an AND or OR gate, producing a one-bit output which is monitored off-chip. Then, the carry feedback path to the counter register is altered, as by inverting all but the LSB, and the contents again checked, using the one-bit output via the AND or OR. In this manner, the operation of the counter is tested in three cycles.

Abstract: A system to provide warning whenever unreliable data is being received by an airborne receiver for a microwave landing system. The received data is tested against certain criteria to determine validity. The received data is also tested to determine whether it was received via a direct path or via a multipath reflection. A validity counter records the percentage of valid data received. A multipath counter records the length of time data is received via direct path relative to the length of time data is received via multipath. Both counters control warning flags to cause a warning to be generated whenever the counter contents are below threshold values. The validity counter is set to an upper limit when its count crosses the threshold in a positive direction and is set to a negative limit when its count crosses the threshold in a negative direction.

Abstract: A Geiger-Mueller tube-based radiation measurement device includes circuitry for the correction of the dead time losses associated with the Geiger-Mueller tube. As the event count rate rises, the transfer function (e.g., the closed loop voltage gain) of an operational amplifier responding to an event count rate signal is modified to compensate for dead time losses experienced at high count rates. Preferably, an analog switch controlled by the event count rate signal automatically sets the voltage gain of the operational amplifier at a level corresponding to the desired amount of dead time compensation required to provide an accurate measurement of actual events. The dead time correction circuitry disclosed herein finds practical application in the use of well-known analog rate meter circuits of the charge pump type.

Abstract: The isochronism of binary counters can be checked by comparing the counting positions. If in a system two counters are required which are operated isochronously but not in synchronism, for example the individual read and write counters for memory addressing purposes, the arrangement according to the invention provides a simple solution by using one counter as a duplicate of the other one instead of duplicating both counters. The parity of the counting position after each increment of both counters is generated. The parity bit of the counter having the highest counting position is delayed by means of a shift register over a number of positions corresponding to the difference in counting positions between the two counters and is then compared with the parity of the counting position of the other counter.

Abstract: Constant-percent break interval pulse correctors insure that the break interval of a dial pulse subsists for a substantially constant percentage of the total pulse interval; i.e., break interval plus make interval. The constant-percent break interval pulse correction of the first pulse in a string of pulses is realized by employing an up/down counter which is controlled to count up at a first clock rate for a first predetermined interval from the beginning of the dial pulse, then to count down at a second clock rate for a second interval from the end of the first interval to the beginning of a subsequent dial pulse and then to count down at a third clock rate until a predetermined count is reached, e.g., zero. The second clock rate is the difference between the third and first clock rates. In one embodiment, proper correction of the last dial pulse in a string of dial pulses is realized by employing a plurality of such up/down counters.

Abstract: A circuit is disclosed for fault-monitoring a microprocessor. The circuit includes an oscillator having an output signal of the same frequency as a test signal output of the microprocessor. The circuit also includes a binary counter. The microprocessor test output is coupled to the reset input of the counter and the oscillator is coupled to the counting input of the counter. The counter counts when the test signal does not correspond in frequency to the oscillator signal. A lower order output signal of the counter is used as a reset for the microprocessor and a higher order output of the counter is used to generate a fault indicating signal if the microprocessor has not resumed correct operation and to inhibit the microprocessor. The oscillator is coupled to the counting input of the counter through a logic circuit. The two outputs of the counter are coupled to another logic circuit which supplies the reset and inhibit signals to the microprocessor.

Abstract: A watchdog timer for monitoring the operation of a computer monitors if the period of a writing signal (W.sub.T) generated by each execution of an instruction of a program is within the predetermined duration. The present watchdog timer comprises a register (2) for storing predetermined DATA upon receipt of the writing signal (W.sub.T), a counter (4) which is incremented by a clock pulse (.phi.), a comparator (3) for providing coincidence output signal when content of the counter reaches said predetermined DATA in the register (2), a first flip-flop (F.sub.1) for storing said coincidence output signal for one period of said clock pulse (.phi.), a second flip-flop (F.sub.2) for storing said coincidence output signal upon receipt of said clock pulse (.phi.), a third flip-flop (F.sub.3) for storing output of said second flip-flop (F.sub.2) upon receipt of said clock pulse (.phi.), an AND circuit (G.sub.1) for providing logical product of reverse output (Q.sub.1) of said first flip-flop (F.sub.

Abstract: A method and apparatus are provided for protecting computer software using an active coded hardware apparatus which is adapted to be connected by an interface connector to a communications port of a computer. The computer is directed by a coded software program in which a small section of the code of the computer software interrogates the communications port periodically to determine if the active coded hardware device is present and connected. The active coded hardware device has a permanently established preset code on an active presettable counter circuit which code is transmitted when interrogated. If the active coded hardware device is present when interrogated and the correct code returned through the communications port of the computer, the program is permitted to continue insuring that the software is properly protected at all times. The active coded hardware device with its particular code and circuitry are sealed in epoxy as a deterrent against tampering.

Abstract: Safety device between a system for the control of a safety actuator and a logic circuit for controlling the actuator.The device comprises sequential circuit for the transmission of logic signals supplied by the control system to the logic circuit, sequential checking circuit for applying to the logic circuit actuator release signals in the case of a failure of the contol system or of the tansmission circuit, the transmission of signals between the system and the logic circuit being carried out after checking the no-failure of the transmission circuit.

Abstract: A misoperation prevention circuit for preventing the misoperation of the integrated circuit having standby made. The misoperation prevention circuit comprises an integrator for receiving a control signal for controlling the operational mode of the oscillator and first and second gates in the LSI circuit for receiving the output of the integrator, with the output of the first gate being coupled to the oscillator and the output of the second gate being coupled to the internal logic circuit. A first threshold voltage of the first gate is lower than a second threshold voltage of the second gate. The oscillation is triggered when output voltage of the integrator exceeds the first threshold voltage but the internal logic circuits are maintained in a standby mode by the second gate until the output voltage of the integrator exceeds the second threshold voltage.

Abstract: A circuit for controlling the application of a timing pulse to a count down chain where the contents of the count down chain are read-out in stages and asynchronously with respect to the application of the timing pulse. The control circuit ensures that a timing pulse is not applied during the read-out of the contents of the count down chain.

Abstract: The housing of a tape cassette is provided with mechanical or electrical structure for recording the number of times the cassette housing is withdrawn from a video cassette recorder. A display window on the cassette displays indicia representative of the number of removals of the cassette from such recorder whereby a rental fee may be charged based on said indicia.

Abstract: A digital frequency relay for use in protecting an electrical power transmission line in the event of frequency deviations indicative of a fault condition, including an input device for receiving AC electric signals, and an oscillator for generating a reference frequency, which are connected to respective first and second counters which respectively count the number of output pulses from the oscillator during the AC electric signal positive half-cycle, and during the AC electric signal negative half-cycle. The resultant output from the first and second counters is added and compared with a set value to produce a trip signal for the frequency relay.

Abstract: A remote meter reading system includes a dial register encoder and a pulse encoder both coupled to the same rotary disc of our induction watthour meter. A first electronic data register stores the non-volatile dial register encoder output, and a second electronic data register stores a value consisting of an initial value set by the dial register encoder at start-up time continuously augmented by the output of the pulse encoder since start up. Comparison and selective readout of the two electronic data registers reduces erroneous meter reading outputs.

Abstract: An electronic up-down counter system including a directional discriminator for accepting input pulses and for generating sequences of pulses which represent up-count and down-count signals. The count signals are applied to a reversible up-down counter having separate inputs for up-count pulses and down-count pulses. The directional discriminator is embodied in a read-only memory (ROM), which accepts the source input pulses to be counted and several inputs having predetermined phase relationships with the source pulse train. The ROM determines from the phase relation whether the count is up or down and generates the appropriate output pulse sequence for application to the reversible up-down counter. The ROM may be logically adapted to be sensitive to a change in sign when the up-down counter passes through a "zero" count.

Abstract: In order to improve the operable frequency of a programmable counter circuit which serves as an N-step counter by loading an initial value N, load terminals of flip-flops of respective stages forming the counter circuit are sequentially cascade-connected via buffers and a load signal is applied to each of the load terminals from a load signal generator circuit. The load signal generator circuit includes a detector circuit which detects a specified value which is provided a short time before the initial value loading of the counter circuit and generates a detected output signal. The detected output signal is shifted by a shift register included in the load signal generator circuit which operates on the same clock signal as that which drives the counter circuit, thereby generating the load signal at the moment of the initial value loading of the counter circuit.