Abstract: A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage VP and a negative supply VN, wherein VDD>Vp>Vn>Vgnd; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple VP and VN to the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating VP and VN such that VDD>VP>VN>Vgnd; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling VP and VN to the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.

Abstract: Systems and methods for managing content in a flash memory. A locking data structure is used to control access to data structures and the locking data structure is implemented in flash memory. The locking data structure is updated by overwriting the data such that the associated data structure is identified as locked or unlocked.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: One or more gray code counters, counter arrangements, and phase-locked loop (PLL) circuits are provided. A gray code counter comprises a set of cells, such as standard cells, that output a gray code signal. The gray code counter comprises a pre-ready cell that provides an early signal, generated based upon an early clock, to one or more cells to reduce delay. A counter arrangement comprises one or more counter groups configured to provide pixel count levels for pixels, such as pixels of an image sensor array. A counter group comprises a gray code counter configured to provide a gray code signal to latch counter arrangements of the counter group. A PPL circuit comprises a gray code counter configured to generate a gray code signal used by a digital filter to adjust an oscillator. The gray code signal provides n-bit early/late information to the digital filter for adjustment of the oscillator.

Abstract: Apparatuses, systems and methods associated with bidirectional Gray code counter design are disclosed herein. In embodiments, a bidirectional Gray code counter may include a sequential logic element to store a Gray code value and logic circuitry. The logic circuitry may be to determine, based on a bidirectional indicator signal, whether to increment or decrement the Gray code value update, through performance of an increment or a decrement of the Gray code value based on the determination of whether to increment or decrement the Gray code value, the Gray code value to be a sequential Gray code value and replace the Gray code value stored in the sequential logic element with the updated Gray code value. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein provide a method for correcting a propagation delay induced error in an output of an asynchronous counter. An input clock is applied to the asynchronous counter. A gray-code count is generated by the asynchronous counter. The gray-code count is mapped to a binary count. An error component, indicative of a counting error induced by a propagation delay between the input clock and the binary count, is generated by taking an exclusive-OR operation over the gray-code count and the input clock. The error component is added to the binary count to generate an error-corrected binary count. The error-corrected binary count is output.

Abstract: A counter includes a buffer unit and a ripple counter. The buffer unit generates at least one least significant signal of a count by buffering at least one clock signal until a termination time point. The ripple counter generates at least one most significant signal of the count by sequentially toggling in response to at least one of the least significant signal. The counter performs multiple data rate counting with enhanced operation speed and reduced power consumption.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: A Gray code counter has multiple two-bit Gray code counter modules, clock gated integrated cells (CGICs), and a parity bit generator. The CGICs gate clock signals provided to the two-bit counter modules, which reduces dynamic power consumption. The parity bit generator generates a parity bit that indicates a count of binary ones in a counting state.

Abstract: A binary-to-Gray converting circuit includes a buffer unit and a conversion unit. The buffer unit generates a data code of n bits in response to a power supply voltage and a second binary bit signal through an nth binary bit signal except for a first binary bit signal corresponding to a least significant bit of a binary code of n bits. The conversion unit generates a Gray code of n bits based on the binary code and the data code, and generates a kth Gray bit signal of the Gray code by latching a kth data bit signal of the data code in response to a kth binary bit signal of the binary code. A logic level of the kth Gray bit signal is determined corresponding to a logic level of the kth data bit signal.

Abstract: The method includes generating coded bits by encoding information bits, dividing the coded bits into a first bit-stream and a second bit-stream, generating a first data symbol by performing anti-gray mapping on the first bit-stream, generating a second data symbol by performing gray mapping on the second bit-stream, and transmitting the first data symbol and the second data symbol.

Abstract: The present invention discloses a vMOS based multi-valued counter unit. The counter unit includes a vMOS source follower and at least a control gate connected the vMOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the vMOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the vMOS follower. The present invention applies the asynchronous carry-over concept to implement the multi-digit multi-value counter, and it also has been verified by the simulation of P Simulation Program with Integrated Circuit Emphasis (SPICE).

Abstract: A decoder for a layered modulation system can be configured to independently and concurrently decode each of a base and enhancement layer. The base layer decoder and enhancement layer decoder can be configured substantially in parallel and can each operate concurrently on the same received layered modulation symbol. Each of the base and enhancement layer decoders can be configured with a bit metric module that is configured to determine a signal quality metric based on the received symbol. In systems having turbo encoded data, the bit metric module can be configured to determine a log likelihood ratio. The ratio is based in part on a channel estimate and an energy ratio used in the layered modulation constellation.

Abstract: The present invention discloses a neuron MOS based multi-valued counter unit. The counter unit includes a neuron MOS source follower and at least a control gate connected the neuron MOS source follower. The control gate includes a first dual-value D flip-flop, a second dual-value D flip-flop, an AND gate, and an OR gate. The present invention utilizes the neuron MOS to replace the complicated threshold value operations of the multi-value logic. The current invention implements the true multi-value logic and a multi-base multi-value counter by increasing the number of the dual-value D flip-flop, and connecting the dual-value D flip-flop to the input control gate of the neuron MOS follower. Comparing to the conventional multi-value counter, the present invention reduces the necessary components in constructing the counter, and it also reduces the cost and power consumption.

Abstract: A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.

Abstract: A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit is configured to detect at least first and second values of the sequence. The detection logic is further configured to generate the active output signal and switch to detecting the second value in response to detecting the first value and generate the active output signal and switch to detecting the first value in response to detecting the second value. The first and second values are separated by N counts.

Abstract: A modular Gray code counter of arbitrary bit length having identical Gray code counter cells in every bit position. Each cell comprises a Toggle Flop and logic which triggers the Toggle Flop and sets the state of the Gray code counter cell. The two outputs of a cell feed two inputs of the next more significant cell. A parity flip-flop provides odd parity, and as a third input to the cell together with the other two inputs determines the state of the cell.

Abstract: Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.

Abstract: There is offered a Gray code counter with which a delay time of a critical path is reduced and a fast operation is made possible. A first Gray code bit Q0 is obtained by outputting an output signal Q0o of an RDFF 2 through an RDFF 31 to synchronize with a clock CLK. A second Gray code bit Q1 is obtained by outputting an output signal Q1o of an RDFF 2 through an RDFF 32 to synchronize with the clock CLK. A third Gray code bit Q2 is obtained by delaying an output signal Q2o of an RDFF 4 with a selection circuit 21 and outputting it through an RDFF 33 to synchronize with the clock CLK. A fourth Gray code bit Q3 is obtained by delaying an output signal Q3o of an RDFF 5 with an AND circuit 11 and a selection circuit 22 and outputting it through an RDFF 34 to synchronize with the clock CLK. Higher bits of the Gray code are similarly generated.

Abstract: A counting device includes a set of memory cells, which are configured to store respective bits of a count code. A controller is coupled to the memory cells so as to increment, in response to occurrences of a count input, the count code in the set of the memory cells from an initial value up to a preset bound in each of a plurality of successive iterations, and to shift the bits of the count code that are respectively stored in the memory cells in each of the iterations relative to a preceding iteration.

Abstract: A counting device includes a set of memory cells, including multiple groups of the memory cells configured to store count words of a count code, which include a less significant word and a more significant word. A controller assigns first and second groups of the memory cells to store the less significant word and the more significant word. The controller increments the less significant word from an initial value up to a first limit in each plurality of successive first iterations and increments the more significant word from an initial value up to a second limit in each of a plurality of successive second iterations in response to reaching the first limit. Upon reaching the second limit, the controller makes a new assignment of the groups of the memory cells that are to store the less significant word and the more significant word.

Abstract: An L-bit gray-code input value can change by more N bits at a time. The lower N bits of the input are stored as a received least-significant-bits (LSB) while the upper bits are stored as a received most-significant-bits (MSB). A stored register holds the corrected, stored MSB and LSB for use by the receiver. When the received and stored MSB's mis-match, the new MSB is stored and the stored LSB is generated so that the stored register contains the smallest possible value with the new MSB. When the received and stored MSB's match, the full L bits are compared. When the received word is larger than the stored word, the largest mis-matching bit in the LSB is found, and bits above this are copied from the received LSB to the stored register, while lower bits are generated to produce the lowest value. Repeating the process converges the result.

Abstract: A data interface includes a network interface processor, a transmitter, and a receiver. The network interface processor is operably coupled to transceive parallel data via a network connection. The transmitter is operably coupled to convert outbound parallel data from the network interface processor into serial transmit data. The receiver is operably coupled to convert serial receive data into inbound parallel data, wherein the receiver provides the inbound parallel data to the network interface processor.

Abstract: An integrated circuit, such as a programmable logic device, implements a single bit transition counter in logic. The counter preferably comprises a first stage receiving a clock signal having a first clock rate and generating a least significant bit in a count. A plurality of intermediate stages are coupled to the first stage, where each intermediate stage receives an output from the immediate previous stage and an inverted output of each other previous intermediate stage, and generates a next most significant bit in a count. Finally, a last stage of the counter receives an inverted output of each previous intermediate stage except the immediate intermediate previous stage and generating a most significant bit in a count.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: Conventionally, it is difficult to design the logic of a Gray code counter that can be used in interlaced counting. Even though interlaced counting is possible with a Gray code counter, the number of simultaneously changing bits increases greatly depending on the number of counts skipped at a time. To overcome these problems, a Gray code counter according to the present invention has a consecutively counting Gray code counter that counts in increments or decrements of one, and an output value converter circuit that converts the Gray code data output from the consecutively counting Gray code counter into a Gray code corresponding to decimal counts as obtained by counting with (2 raised to a particular power minus 1) counts skipped at a time.

Abstract: A state machine, a counter, and related method for gating redundant triggering clocks according to the initial states is provided. The state machine includes a plurality of state units and a clock gating circuit. Each of the state unit is triggered by a clock to generate a corresponding varying state, and the clock gating circuit is capable of selectively withholding a triggering clock to at least one state unit according only to an initial state, such that the selected state unit(s) will not be triggered by the triggering clock while the rest of the state units are triggered by the triggering clock to update their corresponding states.

Abstract: A gray code is produced from a minimum of gate logic by making available and monitoring master outputs of master-slave latch pairs, where the latch pairs are arranged to form a cascading chain of toggle flip-flop stages. The least significant bit through one less than the most significant bit in the gray code is supplied by the master latch outputs and the most significant gray code bit is supplied by the slave latch output of the last toggle stage in the chain.

Abstract: A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives the gray code signals from the holding circuit and converts the received gray code signals into first binary code signals. The operation circuit applies a logical operation to the first binary code signals so as to generate second binary code signals. The second conversion circuit receives the second binary code signals and converts the received second binary code signals into the gray code signals. The second conversion circuit outputs the gray code signals to the holding circuit.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: A non-integer frequency divider is disclosed. The non-integer frequency divider circuit includes several base stages connected to each other. The non-integer frequency divider circuit also includes a clocking circuit for passing an enable bit from one of the base stages to another such that only one of the base stages is enabled at any give time. The enable bit has a pulse width of one clock cycle. The outputs from the base stages are grouped together by an OR gate to generate a single output that is a fraction of an input clock signal.

Abstract: First-in/first-out (“FIFO”) memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.

Abstract: An apparatus and method for controlling an asynchronous First-In-First-Out (FIFO) memory. The asynchronous FIFO has separate, free running read and write clocks. A number of n-bit circular Gray code counters are used to handshake the operation between read and write parts of the FIFO, wherein n is any integer more than one. Additional binary counters are used to accumulate the read and write overflows for the circular Gray code counters. When any circular Gray code counter is overflow, the read or write count is transferred to the respective binary counter for recording the FIFO accesses.

Abstract: A method for establishing a Gray code count sequence having N code words includes determining a first bit switch sequence having 2M−1 elements and a bit switching sequence property according to a first Gray code count sequence having 2M code words and where 2M is larger than N.A second bit switch sequence is determined having N−1 elements and the bit switching sequence property according to the first bit switch sequence. A second Gray code count sequence is determined according to the second bit switch sequence.

Abstract: A digital counter that uses non-volatile memories as storage cells, wherein the storage cells are sub-divided into two groups, one for the implementation of a rotary counter that keeps track of the less significant part of the count and a binary counter that keeps track of the more significant part of the count. The rotary counter implements a counting method that maximizes the count that can be obtained before the endurance limit of the memory is reached by making sure that each change of state of each cell is recorded as one count and that all cells in the rotary counter experience two change of state in every cycle. The binary counter records the number of cycles the rotary counter has gone through.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: A non-power-of-two modulo N Gray-code counter (the “Gray-code counter”) and a binary incrementer-decrementer algorithm are disclosed.

Abstract: An asynchronous up-down counter includes a plurality of counter blocks. Each of the counter blocks has a counter output, an up-down control output, and an up-down control input. A counter signal output from each of the counter blocks has at least two bits. The asynchronous up-down counter also includes a signal bus coupling the up-down control output of a first counter block counting lesser significant bits to the up-down control input of a second counter block counting more significant bits. An up-down control signal output from each of the counter blocks has at least two bits. The up-down control signal may include a first control signal enabling counting operation of the second counter block and a second control signal indicating counting-up and counting-down.

Abstract: A machine used for digital counting which can provide multiple output counts. The machine is particularly useful in analog-to-digital (A/D) converters and in digital-to-analog (D/A) converters. The multiple output counts can change in different directions or in the same direction, and are generated using shared circuitry. The invention exploits properties of counting systems to allow A/D and D/A conversions in convenient digital number formats or in multiple different formats. The invention can be used in integrating converters to help eliminate errors such as comparator offset and dielectric absorption while converting and to increase the conversion rate.

Abstract: The present invention comprises a method of Gray encoding/decoding of binary and Gray code sequences that are less than full-length, resulting in a geometrically reduced storage requirement.

Abstract: A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.

Abstract: A conventional up/down Gray code counter has both a logic circuit section for up counting and a logic circuit section for down counting, and thus has a large circuit scale. To overcome this inconvenience, an up/down Gray code counter of the invention has a one-way Gray code counter that can count only in one, up or down, direction and a highest bit selecting circuit that receives the highest bit of the data output from the one-way Gray code counter and that then outputs the bit selectively either intact or after inverting it.

Abstract: A Gray code counter includes a holding circuit, first and second conversin circuit and an operation circuit. The holding circuit stores gray code signals and outputs the stored gray code signals in response to a clock signal. The first conversion circuit receives the gray code signals from the holding circuit and converts the received gray code signals into first binary code signals. The operation circuit applies a logical operation to the first binary code signals so as to generate second binary code signals. The second conversion circuit receives the second binary code signals and converts the received second binary code signals into the gray code signals. The second conversion circuit outputs the gray code signals to the holding circuit.

Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.

Abstract: A structure and method for operating an asynchronous first in, first out (FIFO) memory system in which the full or empty condition of the memory is determined by comparing a currently-generated write address with a currently-generated read address and a next-to-be-used read address. The current write address and current read address are transmitted from a write address counter and a read address counter, respectively, to a flag control circuit. The flag control circuit includes registers for storing Gray-code versions of the current write address, the current read address, and the next-to-be-used read address, which is determined from the current read address. The flag control circuit generates intermediate ALMOST_EMPTY and ALMOST_FULL signals when the FIFO memory is one data value from being “empty” and “full”, respectively.

Abstract: A gray-code counter system (AP1) for a RAM-based FIFO comprises a read pointer (10), a write pointer (20), and a detector (30). The read pointer includes a gray-code decoder (11), a binary incrementer (12), a gray-code encoder (13), and a register (14) that holds the pointer count). The binary incrementer increments by 1 except when the input is 0110 (decimal 6) or 1110 (decimal 14); in these cases, it increments by 3. The result is a 4-bit modulo-12 gray-code sequence with the twelve allowed gray-code values being distributed among the sixteen possible 4-bit gray code values with translational and reflective bilateral symmetry. The write pointer is similar. Because of the translational symmetry, detectors that work with counters with modulo numbers that are power of two work with the corresponding non-power-of-two counter to provide “full” and “empty” indications.

Abstract: Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code by a Gray-to-binary-code counter. The resulting binary count is incremented by an N-bit incrementer that skips certain binary values by toggling least-significant bits in unison when indicated by certain most-significant binary bits. The result is converted to Gray-code by a binary-to-Gray-code translator. The translated result is stored in the register as the next count. An algorithm is disclosed for designing such a Gray-code counter for any even modulo. The modulo is expressed as a sum of positive and negative terms, each term being a power of two. The exponents of the terms determine the counter design.

Abstract: A low power counter for cycling through a predetermined sequence of states in response to pulses on an input line includes a number of counter blocks, corresponding to the number of bits of the counter, connected in series. The low power counter blocks include memory devices consuming a minimum of power when they are disabled and activated only when the value of the respective data output connection has to be changed.

Abstract: A system and method of implementing a digit counter having a plurality of digits, ranging from a least significant digit (LSD) to a maximum positional digit (MDP), is described. In one embodiment, the system comprises switching a single digit for each increment from the LSD to the MPD. Further, after the MPD is switched, for the next increment, resetting the digits from the LSD to the MPD, and moving the LSD and the MPD by one digit, such that the original LSD becomes a higher precedence digit.

Abstract: A digital counter and method for counting are implemented which minimize fatigue-related failure in the storage element for the count value. The counting sequence is chosen such that the transitions within individual storage elements are the same for each element within a complete counting cycle. The invention extends to software or microcontroller implemented methods for counting, including encoding and decoding applications.