Abstract: A programmable time-intervals generator comprising first and second digital counters, a memory, a digital divider and a digital adder. On the occurrence of a first event, the first counter starts counting, and on the occurrence of a second event, only the most significant bits of the number counted up to then are stored, thereby providing a division by truncation. From the stored number, at least two discrete fractions are obtained by the divider, whereafter said fractions are summed at the adder which operates on strings of bits. The second counter counts down the sum number and, on becoming cleared, generates a signal.

Abstract: A race-free arithmetic operation circuit is disclosed. The circuit comprises a register file array, an arithmetic logic unit (ALU), and apparatus for controlling the input and/or the output signal of the ALU. The apparatus for controlling can be two level-sensitive latches, located before and after the ALU, or one master-slave flip-flop, located either before or after the ALU.

Abstract: A divider circuit provides an output signal having a frequency which is equal to the frequency of an input signal divided by an odd integer. This is achieved by feeding back the output from a binary counter through an AND gate, delay flip-flop and an OR gate so that one cycle is added the output of the binary counter.

Abstract: An integrated circuit temperature detector (thermometer) uses a temperature dependent oscillator to count up to a fixed number and thereby generate a time interval indicative of the temperature (a temperature-to-time converter). The time-to-number converter provides a numeric temperature output. Counting oscillations of a relatively temperature independent oscillator for the time interval may digitize the temperature measurement. Calibration and successive approximation iterations permit simple hardware to achieve good accuracy.

Abstract: The disclosure relates to counters that require the counting to be done under conditions of high security. In such a counter, starting from a number represented by a certain number of bits, the stages of the counter are successively forced, one after the other, to represent the final number in an order such that at no instant do the contents of the counter represent a number smaller than the initial number. A particular structure is used to count very big numbers while, when the technology is of the EEPROM type. This prevents the stage that changes its state most frequently from being subjected to action more than is physically permitted by the technology used. The disclosed method makes it possible, in chip cards, to prevent the diminishing of memorized values representing substantial values which are, for example, monetary values.

Abstract: A high resolution counter circuit measures the time interval between the occurrence of an initial and a subsequent electrical pulse to two nanoseconds resolution using an eight megahertz clock. The circuit includes a main counter for receiving electrical pulses and generating a binary word--a measure of the number of eight megahertz clock pulses occurring between the signals. A pair of first and second pulse stretchers receive the signal and generate a pair of output signals whose widths are approximately sixty-four times the time between the receipt of the signals by the respective pulse stretchers and the receipt by the respective pulse stretchers of a second subsequent clock pulse. Output signals are thereafter supplied to a pair of start and stop counters operable to generate a pair of binary output words representative of the measure of the width of the pulses to a resolution of two nanoseconds.

Abstract: Apparatus for determining the number of cycles occurring in a frequency modulated signal during a sample period, including not only the number of full cycles but any portion of a cycle, by determining the number of whole cycles and adding to this a value obtained by counting the number of high frequency clock cycles occurring between the time of the last rising edge of a full cycle and the end of the sample period, and the number of high frequency clock cycles occurring from the last rising edge prior to the start of the sample period and the start of the sample period and the number of high frequency clock cycles in a whole cycle.

Abstract: A precision, high-resolution, absolute, multi-revolution encoder which allows a multi-revolution position value of a shaft to be detected with high reliability, using only a single revolution detector, and makes multi-revolution detection indirectly related to the accuracy of a rotary angle position signal. The output signal from the single multi-revolution detector is used, together with an inverted output signal, to increment and decrement corresponding up/down counters, based on the direction of rotation of the shaft. Each of the up/down counters is incremented or decremented at different points or zones of the shaft rotation so that the rotational value can be determined unambiguously. A conventional grey-code detector provides accurate angle values. The counters may exist as discrete hardware or integrated software embodiments.

Abstract: A circuit for producing output signals which indicate a fraction of a series of input signals including apparatus for furnishing a first value equivalent to the value of a numerator of the fraction, apparatus for furnishing a second value equivalent to the value of the difference between a numerator of the fraction and a denominator of the fraction, apparatus for sequentially subtracting the second value from the first value with each input signal of the series until a result of zero or less is produced, apparatus for sequentially adding the first value to the result with each input signal of the series until a result of greater than zero is produced, and apparatus for utilizing the value of the result to indicate whether each signal of the series of input signals is to be utilized.

Abstract: A pulse generator circuit includes an adder, a count register which holds the result of addition provided by the adder in order for the addition-result for recursive addition in the adder, a constant register holding a constant required for making said adder continue to perform count-up/count-down operation until a carry/borrow occurs, a parameter register for applying to said adder a correction value for changing, during a normal count-up/count-down operation, the time when carry/borrow occurs, a selector for selecting one of said constant and parameter registers for applying the value held in the selected register to said adder, and a shift register responsive to a carry/borrow occuring in the addition-result from said adder for shifting the content thereof.

Abstract: The performance of some chips (e.g., VLSI processors) may be increased by running the internal circuits at higher clock rates, but use of a higher clock rate is limited by the heat-dissipation ability of the chip's package. Apparatus and a method is described for estimating the total heat accumulated for dissipation at any given time. For the periods that the chip is idle, the clock rate is decreased to reduce heat generation. The heat saved while the chip is idling is available for use later to increase the clock rate above normal, provided that the total heat generated does not exceed the heat-dissipation capacity of the package.

Abstract: A counter/divider dividing an input frequency (F1) by 2.sup.q+n +1/2, comprises a first divider by 2.sup.q (30) receiving the signal to divide of a frequency F1 and provides 2.sup.q+1 outputs at the frequency F1/2.sup.q out of phase the ones to the others of 360.degree./2.sup.q+1 ; a multiplexer (32) having a control terminal (34) and sequentially providng at its output (33) each of said 2.sup.q+1 outputs each time a control signal is applied; and a second divider by 2.sup.n (31) receiving the output (33) of the multiplexer and providing the desired output (34) of the counter/divider, this output being applied to the control terminal of the multiplexer.

Abstract: An absolute position detecting device in which the number of revolutions of a drive shaft adapted to drive an object to be controlled is counted with a counter for detecting an absolute position of the object. When a predetermined point on the object returns to an initial position after making one or more revolutions, the drive shaft is returned to an initial rotational angular position. A data rewriting operation is performed to rewrite, as necessary, the count value of the counter into a value obtained by subtracting a count value therefrom which is obtained during the one or more revolutions of the predetermined point.

Abstract: A nine bit Gray code counter is constructed as a single integrated circuit such as a PLA and comprises D flip-flops, AND gates and Exclusive-OR gates. The array is programmed to provide a nine bit Gray code count at its outputs. The Q output of each flip-flop provides one bit in the Gray code count. The D input to each flip-flop is determined by the significance of the bit and the following equations: D0=A XOR Q0; D1=(A.multidot.Q0) XOR Q1; Dn=(A.multidot. . . . .multidot.Qn-2.multidot.Qn--1) XOR Qn; and Dmsb=(A.multidot.Q0.multidot.Q1.multidot. . . . .multidot.Qmsb-2 XOR Qmsb.

Abstract: A decimetor circuit is constructed to execute an FIR filtering of "n" taps for input data sampled with a sampling frequency "f" and then to resample an output of the FIR filter at a frequency of "f/m". A first counter of a "divided-by-n/m" type is driven with a clock having a frequency of "n/m" of the sampling frequency "f" and selectively operates either in a first counting condition in which the first counter is incremented by one count with each clock pulse of the clock or in a second counting condition in which the first counter is incremented by two counts with each clock pulse of the clock. A second counter of a "divided-by-n" type is driven with the clock and incremented by one count with each clock pulse of the clock. A first decoder is coupled to the second counter for decoding a content of the second counter so as to bring the first counter either into the first counting condition or into the second counting condition.

Abstract: In systems requiring multiple identical digital correlators the original m-bit counter for each correlator can be replaced by an n-bit multi-channel counter. The most significant bit of each n-bit counter is sampled every 2.sup.n-1 clock cycles and the results are stored in dual port memory. Stored input counter samples are converted into a series of binary words which are multiplexed to one of two signal outputs. The dual port memory allows current samples from the input counters to be written on port A, while previously written samples are time multiplexed and read to the output counters on port B. This design not only reduces the number of parts needed for counters but also the buffers needed for so many counters to appear on the same computer bus. In addition, the maximum delay between the sampling of any correlator is greatly reduced.

Abstract: A system, for counting the occurrence of a plurality of system events and for prioritizing the order in which count values are to be incremented, receives a plurality of data signals (15) where each signal is associated with a system event. The data signals (15) are stored in a storage register (16). A memory device (12) stores a plurality of count values, where one count value is associated with each system event to be counted. Each count value is stored in a preselected memory location. The storage register (16) also receives a feedback signal (32) to update the signals (15) stored in the register (16). The storage register (16) generates a plurality of signals (19) which are input to a priority decoder (14) and the priority decoder (14) generates a priority signal (32) to address the location in the memory device (12) where the count value to be accessed is stored.

Abstract: A frequency conversion system for converting a pulse period into a frequency value by calculating a reciprocal value of a binary digit value of a pulse period from a remote period counter. The system uses the binary digit as a divisor and successively adds the divisor until a running sum results in (1) greater than a chosen dividend value or (2) the number of additions needed to reach a chosen dividend value is reached. A second embodiment is included which contains a local period counter.

Abstract: Digital ratiometer and amplitude analyzer using such a ratiometer.It is possible to solve the problems of the calculation and display of the ratio of two or more quantities, provided that the latter are converted into frequencies. Counting registers are used for evaluating these quantities. The filling of these counting registers (6,13) is prevented by bringing about a shift to the right (10,19) of all the registers as soon as (15) one of them is filled.

Abstract: The frequency of the signal is determined by counting the period of the signal. A round-off circuit increments the count if the end of the signal occurs after the midpoint between counts.

Abstract: A method for modifying the frequency of a clock signal includes the steps of producing a clock signal having voltage pulses which occur at a first frequency and producing a control signal having voltage pulses which occur at a lower frequency. The frequency of the voltage pulses in the control signal is incremented in successive time intervals and the clock signal and control signal are combined such that one voltage pulse in the clock signal is deleted for each voltage pulse in the control signal. This results in a modified clock signal having a frequency which may be ramped up or down depending upon the initial frequency of the control signal and the direction in which the frequency of the control signal is incremented.

Abstract: A frequency divider circuit is responsive to first and second digital input signals and an input clock signal for providing an output clock signal operating at a frequency equal to that of the input clock signal divided by the ratio of the first and second digital input signals. A register is initialized to a predetermined digital value for providing a first digital output signal. The first digital input signal is subtracted from the first digital output signal to form a second digital output signal for the first logic state of a digital control signal; otherwise the second digital output signal is set equal to a least significant portion of the first digital input signal for the second logic state of the digital control signal. The second digital output signal and the second digital input signal are added together for providing the next value of the first digital output signal which is stored back in the register to repeat the cycle.

Abstract: The sheets of a stream of partially overlapping sheets are counted during transport past a generator of ultrasonic waves which is operated by a control unit at a frequency such that each sheet reflects a series of successive waves. The resulting echoes are directed toward two discrete signal generators which transmit signals to an evaluating circuit by way of the control unit. The signals denote the length of intervals of propagation of waves from the source to the respective signal generators, and the circuit processes such signals to furnish information denoting the number of sheets which are conveyed past the locus of impingement of waves upon the sheets.

Abstract: The track counter for optical disk in accordance with the present invention, that counts the number of tracks a light beam passes upon when an optical head moves over an optical disk in the radial direction, comprises a passage signal generating circuit for detecting based on a reflected light of the light beam from the optical disk, that the light beam passed upon a track and for releasing a passage signal on that occasion, a counter that counts the passage signals released by the passage signal generating circuit, a count suspending circuit for forecasting that the light beam will pass upon a specific position of a track and for suspending the count by the aforementioned counter of the passage signals during this forecasted period, and a count value compensating circuit for assuming, when the count of the passage signals is suspended by the count suspending circuit, the number of tracks the light beam passed upon during that period, and for adding this assumed number to the count value of the counter.

Abstract: A frequency divider circuit, especially for use in frequency synthesizers, in which the frequency divider is provided with whole-number division factors, permits intergrator, differentiator and/or phase accumulations to be used to generate the successive values of the division factor which average, over time to allow fractional frequency division.

Abstract: High speed complex logic circuitry powered solely by clock signals. Such circuitry may be implemented in optical, electrical or other means, involving any medium or substrate as desired.

Abstract: A digital frequency divider capable of providing output pulses of frequency f.sub.out related by Y/X to the frequency of the input pulses f.sub.in, where X and Y are positive whole numbers and O<Y/X.ltoreq.1. The circuit is particularly suited for high frequency digital applications. The X and Y values may be fixed or individually variable. Truncation errors decrease with time to provide a best estimate output frequency. In a preferred arrangement, iterative summations of residual and incremental values are latched and recycled as feedback in synchronism with the rate of the input frequency.

Abstract: A threshold detection logic circuit of simple and economical design is disclosed that indicates when the difference in the number of first operations to be counted and the number of second operations to be counted is either greater than or equal to a threshold value, or less than or equal to a threshold value. The threshold detection logic circuit employs the use of an overflow bit of a counter, which has a counting range of 2.sup.N+1 for a threshold range of 2.sup.N, in order to generate a threshold interrupt signal. In addition, the disclosed threshold detection logic circuit permits the threshold value to be programmed to any desired value.

Abstract: A device for the measurement of an event or occurrence, including a summing counter which is actuated from a divider circuit. The device includes a divider circuit constituted of a series circuit of counting steps, and wherein a transfer circuit for the counting pulses of the counting steps is arranged intermediate the summing counter and the divider circuit.

Abstract: A phase detection circuit for detecting the phase shift of an input signal. An A/D converter converts the input signal into first, second and third digital data according to successive three sampling points. A first subtractor subtracts the third data from the second data to produce a first subtraction signal. A second subtractor subtracts the first data from the second data to produce a second subtraction signal. A third subtractor subtracts the second subtraction signal from the first subtraction signal to produce a signal representing the phase shift. An adder adds the first and second subtraction signals together to produce a signal representing the amplitude of the input signal. A converter converts the signal representing the phase shift into a signal representing the absolute value of the phase shift according to the signals representing the phase shift and the amplitude.

Abstract: A signal distinction circuit comprises a clock signal generating circuit for generating a clock signal whose frequency is longer than that of a pulse signal corresponding to a discrimination signal applied to a counter as an actuating signal; and an arithmetic circuit for operating the pulse signal and the clock signal, and generating an output signal according to the presence or non-presence of the discrimination signal so as to forcibly drive a detecting circuit to which an output signal of the counter is applied, whereby the detecting circuit can be forcibly driven irrespective of the condition of the counter when the discrimination signal is not applied thereto.

Abstract: A frequency of a signal, particularly a frequency, partly varied as time passes, of a signal is counted in real time by producing a delay signal by delaying the signal as much as a predetermined time, detecting delayed zero-cross pulses from the delayed signal, detecting zero-cross pulses from the non-delayed signal, counting a first number of the delayed zero-cross pulses after the predetermined time is over, counting a second number of the zero-cross pulses during and after the predetermined time, producing a number difference between the first number and the second number by subtracting the first number from the second number and halving the number difference. The predetermined time is designated longer than a half period of the signal frequency to be counted. When the predetermined time is set long, the average frequency of the signal is counted, and when that is set short comparing with the partly varied interval of the signal frequency, the partly varied frequency of the signal is counted in real time.

Abstract: At the start of measurement by a length measuring device, a calibration coil in which the temperature characteristics are known, is connected to an oscillator. The oscillation frequency of the oscillator at this time is counted by a counter and is given to microcomputer. Microcomputer obtains temperature information corresponding to counted numbers with reference to a table of counted numbers versus temperature information which has already stored temperature information corresponding to a plurality of counted numbers and stores the obtained temperature information in a data storage area. In measurement mode, measured values subjected to temperature compensation are obtained according to the temperature information stored in the data storage area.

Abstract: A frequency divider for dividing input pulses by a predetermined number is formed of an input means for receiving input pulses, a plural number of counters, each having a series connection of stages through which a count signal is respectively shifted in response to the input pulses. The numbers of series stages being selected so that they do not have any common divisor and have a minimum common multiple larger than the predetermined number pulse one. The frequency divider also includes a detecting means for detecting common occurrence of said count signals at selected stages of respective counters, and an output means for producing an output pulse in response to the detection by the detecting means.

Abstract: A bit-serial integrator includes the cascade combination of a bit-serial adder, a first bit-serial register and a second bit-serial register. Input signal is applied to one input of the adder and the output terminal of the second bit-serial register is coupled to a second input of the adder. A transparent latch is coupled to an output of the first bit-serial register and is conditioned to pass a predetermined number of sample bits and then to latch and output a particular sample bit for the duration of a sample period. The output of the latch is an integrated, scaled and truncated representation of the input signal.

Abstract: A circuit arrangement for monitoring a binary signal having at least one level shift within a characteristic waiting time, such circuit including two flip-flops which receive control pulses at intervals at least as long as the characteristic waiting time. In order to enable the two flip-flops to employ the same clock pulses, a gate circuit is assigned to each of them, the output of which is connected to the data input of the assigned flip-flop. If a control pulse is present, the first gate circuit ensures that the first flip-flop can switch to its set state, while the second gate ensures that the state of the second flip-flop is switched to the inverse of the state of the first flip-flop. If a control pulse is not present, the first flip-flop can only be switched to its reset state when the binary signal to be monitored has the binary value 1, while the second flip-flop cannot switch from its existing state.

Abstract: A method of determining the rate of change of frequency of a plurality of randomly occurring events begins by counting the number of random events which occur within a plurality of predetermined sampling intervals to obtain a plurality of count values, each corresponding to one of the sampling intervals. These count values are stored in a memory table and the count values which correspond to the most recent set of N of the sampling intervals is summed to obtain a first accumulated count. A second accumulated count is obtained by summing the count values which correspond to a second set of N of the sampling intervals, preceding the most recent set. The rate of change of event frequency is then calculated by dividing the logarithm of (S.sub.1 /S.sub.2) by the number N. The value of the number N is dynamically adjusted for subsequent calculations based on the incoming frequency of random events.

Abstract: A high-speed counter using radix-N Signed-Digit redundancy adders, an initial value generator and an interim value generator for each digit. The initial value is selected based upon a desired count. The transfer digit and interim value for each digit are generated to eliminate a carry propagation from a lower digit position. The high-speed counter reaches a desired count with a certain delay time regardless of the starting count value.

Abstract: A method of counting a plurality of pulses representative of randomly occurring events includes the steps of counting the number of pulses, having an amplitude exceeding a first threshold amplitude, which occur during a predetermined sampling period to obtain a first count and counting the number of pulses, having an amplitude exceeding a second threshold amplitude, which occur during the sampling period to obtain a second count. The second count is compared to a predetermined number and the counts for that sampling period are rejected if the second count is too large. If the second count is not too large, the true count is calculated by subtracting the second count from the first count. This counting procedure is repeated for a preselected number of successive sampling periods. After the final sampling period, all of the true counts are added to obtain an accumulated count and the accumulated count is multiplied by a scaling factor to obtain an output count.

Abstract: A device for counting objects being transported by transport equipment includesa light projector for projecting a light beam onto the objects being transported,a light receptor for receiving the light beam reflected from the objects being transported and focusing the beam to a point, anda pulse generating means for generating pulses in accordance with the abrupt shift of the focused point of the reflected light beam caused by the ends of the objects being transported.The objects being transported are counted on the basis of the pulses generated by the pulse generating means.

Abstract: A Gray code counter employs modules of binary bits to form expressions or numbers. The count is sequenced from one expression to the next by changing only one binary bit in one location of an expression. The Gray code counter can be an incrementing counter or an increment/decrement counter. The counter can operate with expressions of several bits, and employs a minimal number of D type flip-flops and logic gates.

Abstract: A multi-digit, mixed-base or mixed-radix counter of the type used in digital computing devices wherein the value of each digit of the counter is stored in two parts: a first part being the normal numerical value except in certain exceptional cases; and a second part which is zero except in the exceptional cases in which it is a binary one. The exceptional case is when the value to be represented by the counter digit is a terminal digit value, i.e., a maximum digit value when the counter is incrementing or zero value when the counter is decrementing. In the case of a decrementing counter where the normal terminal digit value is a zero, each zero value is replaced with the corresponding maximum digit value for that digit in the first part of the counter, but the second part of the counter identifies in which (if any) of the digits of the first part of the counter such a substitution has been made.

Abstract: The root mean square value of sensed current within a protected circuit is calculated. A frequency multiplying circuit produces a pulse stream having a frequency proportional to the square of the amplitude of an analog signal representation of the circuit current. A root mean square value over a prescribed interval is developed from the squared current value.

Abstract: Basic block shift registers are cascaded to form a fully programmable linear feedback shift register. Each of the basic block shift registers comprises a plurality of flip-flops, each of which includes control logic circuits. A polynomial equation is first fed into the linear feedback shift register for setting the respective flip-flops into predetermined logic states, which are used to encode messages to be shifted by the programmable linear feedback shift register. The number of flip-flops in the programmable linear feedback shift register can be varied, in accordance to the polynomial equation. Likewise, the polynomial equation also determines the number of times the programmable linear feedback shift register is to circulate the encoded messages.

Abstract: A method and apparatus for dividing a clock pulse frequency Cl in a ratio A/B, where the quotient between B and A is the whole number C and the remainder D. A pulse train is generated, which includes (A-D) half pulses with a pulse length of C clock pulses and also includes D half pulses with a length of (C+1) clock pulse lengths. The difference between C and (C+1) is the deviation in pulse length of the divided clock pulse frequency.

Abstract: A divider-by-factor frequency divider circuit is described. The rate-multiplier principle of eliminating pulses as regularly as possible from a number of pulses of the signal to be frequency-divided is modified so that low-frequency variations in the frequency-divided signal are reduced at the expense of an increase in higher-frequency variations. This modification is achieved through the addition of a second accumulator, a pair of adders, a subtracter and a presettable counter to the accumulator of a frequency divider circuit. A rate multiplier with a coloring characteristic inverse to pink noise is thereby obtained.

Abstract: The invention relates to a process for using a binary register with n bistable cells making it possible to determine the ratio of two frequencies and an apparatus for performing the process. This use process consists of supplying to a counting input of the binary register with n bistable cells a first pulse signal S.sub.1 of frequency F.sub.1 and to a shift input of said register a second pulse signal S.sub.2 of frequency F.sub.2 with F.sub.1 >>F.sub.2, the register content being incremented at each pulse of the first signal S.sub.1 and divided by two at each pulse of the second signal S.sub.2, whereby the register content can also be loaded into a buffer register at each pulse of the second signal S.sub.2. The invention more particularly applies frequency discrimination, the determination of an unknown frequency on the basis of a known frequency and to the control of analog display means of the logarithm to base two of the ratio of two frequencies.

Abstract: A serial pulse frequency converter is disclosed of the type which counts high frequency clock pulses between input pulses, multiplies each successive count by first and second proportionally constants and downcounts the products by high frequency clock pulses to produce output pulses at a new, proportional frequency. A first serial register is used to both count the high frequency pulses between input pulses and hold the count during the multiplication process. It is loaded at the end of multiplication with the a number representing the "lost counts" as it is switched to its counting mode. A second serial register accumulates the sum of partial products of the count and the proportionality constants. The gain circuit serially provides a first proportionality constant and then a second, but may selectively substitute a binary number representing a constant unity for the second.

Abstract: The digital frequency divider (or synthesizer) produces non-integral submultiples of an input frequency by alternately dividing its input by two integers by means of two integral digital frequency dividers, one of which produces an output higher than the desired non-integral submultiple and the other of which produces an output lower than the desired non-integral submultiple. The desired non-integral submultiple is obtained by alternately switching the circuit output to two integral digital dividers, the duty cycle of the switch determines the precise output frequency obtained. The concept can be implemented with programmable digital counters and logic circuitry. The circuitry can be used to implement a novel method of duplicating an accurate signal with improved stability. A circuit useful in practicing the method measures the ratio of two frequencies.

Abstract: In combination with apparatus for printing indicia on a sheet, and a microcomputer for controlling the indicia printing apparatus to cause the indicia to be printed a predetermined marginal distance from an edge of the sheet, there is provided an improvement for changing the marginal distance. The improvement comprises: operator-controlled apparatus for providing at least one signal representative of at least one increment of distance; and programming the microcomputer for processing the at least one signal to provide a changed marginal distance, wherein the changed marginal distance includes the predetermined distance changed by the at least one increment of distance.