Abstract: Techniques for monitoring the individual feed and water intake and pharmaceutical use and unmetabolized residual alerting in the livestock industry. Livestock have sensors installed on or in their bodies to detect consumption of feed and water for each animal in an environment where multiple animals are present. Sensors communicate data regarding the duration and timing of individual animals feeding habits. Health and efficiency status data is recorded per animal and analyzed to determine whether to issue an alert indicating problems with individual animals. The system tracks the health and efficiency data for each animal, pen or farm and generates statistical information regarding the sensor data. The system communicates with user interface to display notifications and statistical data. In addition, the pharmaceutical monitoring system alerts when any unmetabolized residual pharmaceuticals are still in the animals when the animal is being readied for shipping to a packing plant.

Abstract: The invention provides a detection circuit for detecting light-off modes performed by a silicon-controlled dimmer which comprises a voltage detection circuit receiving an output signal and generating a voltage detection signal according to the output signal, and a delay circuit connected to the voltage detection circuit, receiving the voltage detection signal, and delaying the voltage detection signal in order to output a detection signal. The invention detects the output signal through the voltage detection circuit, and delays the detected voltage detection signal to output the corresponding detection signal, and then the detection signal effectively distinguishes the light-off modes performed by the silicon-controlled dimmer to meet requirements of users.

Abstract: An object detection system compensates for variations in transmission characteristics within an object passageway caused by, for example, dust or dirt. An object detection device includes a plurality of electromagnetic radiation emitters and detectors arranged in rows on opposite sides of a passageway. First lenses focus radiation from the emitters into a semi-columnated beams of radiation that together create a plane of semi-columnated electromagnetic radiation that spans substantially across a width of the passageway. Second lenses focus the received electromagnetic radiation onto corresponding ones of the plurality of radiation detectors. A controller receives a radiation intensity signal from the detectors, determines that its value is outside of a predetermined range, and adjusts an amount of electrical power supplied to the plurality of radiation emitters so that the value of the radiation intensity signal changes to become within the predetermined range.

Abstract: Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes in a non-bit-sequential format. The method includes reordering the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format.

Abstract: An input signal is segmented by a first data latch into 2 bit segments according to rising and falling edges of a clock signal clk, and latched. When the input signal is an RSDS signal, 2 sets worth of 2 bit data are latched according to rising and falling edges of a clock signal clkx2, using a first output section, a first data holding section, and a second output section. When the input signal is a mini-LVDS signal, 4 clock cycles worth of data are held according to the rising and falling edges of the clock signal clkx2 using the first data holding section and the second output section. One set's worth of 8 bit data is then latched according to a rising edge of a clock signal clkx4 using the first output section, a third output section, a fourth output section, and a fifth output section.

Abstract: A method of fetching digital data and writing the digital data into a memory of a logic analyzer, which comprises the steps: designate at least a first region and a second region in a memory; set a first triggering condition and a second triggering condition; fetch digital data continuously and write it into the memory while analyzing; and then write first test data which have an identification to satisfy the first triggering condition into the first region, and write second test data which have an identification to satisfy the second triggering condition into the second region. And once the first test data or the second test data are found, stop writing the digital data into the corresponding regions.

Abstract: An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed.

Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.

Abstract: Disclosed is a high speed counter apparatus. The high speed counter apparatus includes a first counter configured to perform a count on the lower bits of the final output signal in response to a first clock signal, a second counter configured to perform a count on the upper bits of the final output signal in response to a second clock signal, and a clock signal generator configured to generate the second clock signal from the first clock signal. In accordance with the present invention, power consumption and a bottleneck phenomenon in an upper bit counter can be reduced because a second clock signal for operating the upper bit counter is synchronized with a first clock signal for operating the lower bit counter at a frequency lower than that of the clock signal for operating the lower bit counter.

Abstract: An input circuit in high speed counter module for PLC is provided, the input circuit being configured such that various types of pulse signals are changed to a single type of pulse signal and transmitted to an MPU, whereby the type of input pulse is checked or an operation of checking addition/deduction is omitted to increase an interrupt process speed.

Abstract: In a double data rate (DDR) counter and counting method used in, for example, an analog-to-digital conversion in, for example, a CMOS image sensor and method, a first stage of the counter generates a least significant bit (LSB) of the value in the counter. The counter includes at least one second stage for generating another bit of the value in the counter. An input clock signal is applied to a data input of the first stage and a clock input of the second stage.

Abstract: In some embodiments, a new DTS implementation, which employs the conventional Vbe/?Vbe temperature dependent principles but substitutes a voltage-to-frequency (V/F) based ratio meter for the DAC based approach. This new approach can result in a more simplified circuit that may be more variation tolerant and can require less power and area.

Abstract: A signal detection circuit comprising: a differential amplifier to which an output voltage of a detection coil of a magnetic sensor is to be applied; a comparator to output a digital signal being at one logic level in a period between two spike-shaped voltages adjacent to each other in the output voltage of the differential amplifier; and a count circuit to perform a count operation in a period during which the comparator outputs the digital signal of the one logic level, the count circuit including a first counter to count a first clock having a predetermined frequency, a second counter to count a second clock being equal in frequency to and different in phase from the first clock, the second counter having the same number of bits as the number of bits of the first counter, and an adder to add count values of the first and the second counter.

Abstract: A control unit that outputs a plurality of control signals in response to the input of a plurality of counter enable signals allocated into the numerical value of a multiple of 2 is provided. An operating unit increments or decrements by a multiple of 2 in response to input of the plurality of control signals and count up-down signals.

Abstract: An asynchronous counter that is capable of switching count mode includes flip-flops, and three-input single-output tri-value switches respectively provided between the adjacent pairs of the flip-flops. The tri-value switches switch among three values, namely, non-inverting outputs and inverting outputs of the flip-flops and a power supply level. Each of the tri-value switches switch among the three input signals according to two-bit control signals, and input a selected signal to a clock terminal of a subsequent flip-flop. When count mode is switched according to the control signals, a count value immediately before the mode switching is set as an initial value, and counting after the mode switching is started from the initial value.

Abstract: Methods and systems for automatic generation of an at-speed binary counter are described. The binary counter includes a slow counter that increments when a fast counter overflows to keep up with a fast clock. A framework to automatically generate a Hardware Description Language (HDL) for an at-speed binary counter is also described.

Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

Abstract: A shared counter performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit provides counter output data based on the counter initialization data. An output circuit provides the counter output data to K destination circuits in the electronic circuit. The output circuit provides only one of the K destination circuits with the counter output data at a given time.

Abstract: An output buffer with a slew rate that is load independent is comprised of an output buffer (14) that is connected to an output terminal (12). The output buffer (14) is controlled such that it can drive a load (18) with different drive levels by changing the transconductance internal thereto. The transition on the input to the buffer (14) is passed through an intrinsic delay block (34) and variable delay block (40) to provide a delay signal on a node (42). A first phase detector latch (50) with a first threshold voltage compares this transition with the transition on the output terminal (12). A second phase detector latch (60) with a second threshold voltage, also compares this delayed transition with that on the output terminal (12). If both of the latches (50) and (60) indicate that the delayed transition occurred after the transition on the output terminal (12), a control signal on a line (78) is changed by incrementing a counter (74). This will increase the drive to a load (18).

Abstract: The invention provides a counting device and a direct memory access system using the counting device. In the counting device, a carry/borrow signal to be supplied from a predetermined one-bit counter among a plurality of one-bit counters to another one-bit counter in the subsequent stage is inputted to an input/cutoff element such as an AND circuit. The input/cutoff element is also supplied with a control signal for controlling the input/cutoff of the carry/borrow signal. Thus, the range of the values to be counted can be changed.

Abstract: A programmable burst sequence counter is described. The counter is capable of counting sequences of binary numbers in a linear burst sequence or interleaved burst sequence starting from a initial binary number that is presented to the inputs of the counter. The programmable burst sequence counter is applicable to the generation of addresses for the storage and retrieval of digital data from memory arrays.

Abstract: A counter system has a first counter seeded by several input signals and a second counter seeded by at least a first output from the first counter. A selection signal is input to the second counter to select the use of either an interleaved count sequence or a sequential count sequence.

Abstract: A synchronous counter performing a count operation in response to an input of a clock having a fixed frequency. The synchronous counter including a first transmission gate receiving a counter initialization signal and transferring the counter output signal to a carry output node when the counter initialization signal is received during a time period in which the external address signal is not received, and a second transmission gate receiving the counter initialization signal and transferring an address signal to the carry output node when said counter initialization signal is received during a time period in which the external address signal is received.

Abstract: A pulse counter circuit has an invertor which inverts a pulse signal input thereto to form an inverted signal. One of the pulse signal and the inverted signal is selected in response to a selecting signal, and the selected signal is delivered as an output signal. Changeover of a signal to be selected between the pulse signal and the inverted signal is effected at timing of a change in level of the pulse signal. A counter counts pulses of the output signal. A pulse signal changeover circuit selects one of a pulse signal and an inverted signal obtained by inverting the pulse signal, in response to a selecting signal, and the selected signal is delivered as an output signal. The pulse signal is masked by being held at a predetermined level within a predetermined time period, and the inverted signal is masked by being held at the predetermined level within the predetermined time period.

Abstract: An input clock delay circuit includes an up counter for estimating the approximate number of internal clock cycles that occur during one cycle of the input clock signal and another up counter for determining the portion of each cycle of the input clock signal that is high. A clock manipulation circuit receives each counter's value, and may be set to perform a fixed transform on the input clock signal, such as clock delay/advance, duty cycle shifting, and frequency multiplication/division. The clock manipulation circuit output values are loaded into two down counters that are also clocked by the internal clock. On the rising edge of the input clock signal, the first down counter starts decrementing until the counter reaches zero, indicating that the desired delay interval has passed, at which point the delayed output clock signal is taken high. The second down counter then starts decrementing for an interval that is equal to the desired duty cycle of the output clock signal.

Abstract: It is an object to accurately obtain the period of the horizontal synchronizing signal in the video signal. The number of internal pulses are measured in a predetermined measurement period defined by the horizontal synchronizing signal. It is assumed that the periods of the horizontal synchronizing signal and the internal pulse are denoted as T.sub.H and T.sub.S, and the measurement period is defined by one period of a divided signal NS which is obtained by N-dividing the horizontal synchronizing signal. In this case, the length of the measurement period is N.multidot.T.sub.H. The period of the horizontal synchronizing signal is obtained when the internal pulse is activated K times in the measurement period. After the measurement period is started, the divided signal NS transits between the Kth activation of the internal pulse and the (K+1)th activation, and the measurement period is ended. Accordingly, there is the relation of T.sub.S .multidot.K<N.multidot.T.sub.H <T.sub.S .multidot.(K+1). The error .

Abstract: A method and apparatus as provided that simplifies the software required for modifying the contents of a register. By adding one gate to the register, a single command can be written to the register to modify the states of multiple bits. The system reduces software overhead significantly when multiple registers must be modified.

Abstract: A counter circuit selectively generates counting sequences in binary and interleave counting modes. A counter is formed by 3 toggle flip-flops. The toggle signals are provided by a toggle control circuit which contains logic gates that are enabled or disabled based on the state of a mode select signal. In binary mode, output bits are permitted to be used to toggle higher order count stages. In interleave mode, the binary toggle signals are blocked, and another counter circuit counts toggle signals in the interleave sequence, which signals are passed by the toggle control circuit to toggle inputs of the main counter. The other counter circuit can be reset in response to a reset signal applied to a load enable input.

Abstract: A timer has a function of compensation calculation and includes a compensation value register 1 for holding a compensation value and an arithmetic unit 2 which adds or subtracts a compensation value ".alpha." held in the compensation value register 1 and a value "CC" of a count value C of a counter 3 at that time point, and by loading the operation result of the arithmetic unit 2 to the counter 3. Such a timer reduces a burden on a CPU and is capable of compensating the count value correctly regardless of a remaining time.

Abstract: A memory device for recording a time factor of data includes a threshold element, coupling capacitance, an RC-circuit, and a digital counter. A reference voltage is input to the RC-circuit. The output of the RC-circuit and an input voltage are each input to the coupling capacitance. The output of the coupling capacitance is input to the threshold element. When the voltage received by the threshold element reaches a threshold voltage level, the threshold element generates an output voltage. The digital counter receives the threshold element output voltage and the reference voltage. The digital counter is triggered by the reference voltage to begin counting clock pulses generated by a reference clock. The digital counter is then triggered by the threshold element output voltage to stop counting the clock pulses.

Abstract: An actuator movement detector (10) indicates proper engagement of a solenoid (12). The current flowing through a field coil (16) is converted to a sense voltage that exponentially increases and then follows a dip before increases again to a steady state value greater than the first peak value. The exponentially increasing sense voltage is stored across a capacitor (24). Any AC variation about the stored sense voltage sets the output state of comparators (30, 32) and determines a first peak value of the sense voltage. After the first peak, a counter (44) must count to a predetermined value during the low peak before the sense voltage returns to its first peak value. If the counter reaches at least the predetermined count value before returning to its first peak value and count back down to zero before reaching steady state, then the solenoid is considered engaged.

Abstract: An asynchronous counter includes a plurality of flip-flops, cascade connected to one another, the plurality of flip-flops serially receiving successive pulse trains having varying numbers of pulses per pulse train. Switching circuitry, coupled to the plurality of flip-flops, inverts the state of each flip-flop between a first set of pulse trains and a second set of pulse trains (or first and second consecutive pulse trains) so that the counter computes a difference between the number of pulses in the first set of pulse trains and the number of pulses in the second set of pulse trains (or a difference between the number of pulses of the first pulse train and the number of the second pulse train). Initialization circuitry, coupled to the plurality of flip-flops, initializes all of the flip-flops at each predetermined even number of pulse trains.

Abstract: A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Abstract: A reload-timer/counter circuit provides a reload-timer function and a counter function commonly and selectively. The circuit is comprised of first, second, third, and fourth registers. The third and fourth registers act as a control status register and a mode register, respectively. The first and second registers act as, in the reload-timer mode a data register and a counter register, respectively, while in the counter mode, the first and second registers act as the counter registers.

Abstract: A signal generating circuit includes a counter for counting up input clock pulses to output a trigger signal when counting up to a predetermined number of pulses, a CPU for outputting a mask request of a first trigger signal, a first flip-flop for storing the mask request of the CPU, a second flip-flop for latching a normal output signal of the first flip-flop by the trigger signal of the counter, and an AND circuit for calculating a logical sum of a mask request signal output from the second flip-flop and the trigger signal output from the counter. Thus, the trigger signal generating circuit masks the first trigger signal output from the counter and prevents the output of a superfluous trigger signal when a timing of a trigger signal generation is delayed.

Abstract: A counter circuit includes counting stages of n bits where n is a natural number. The counter circuit also includes a logic decoding circuit for determining the inputs of the counting stages, a logic circuit for adjusting the number of simultaneous changes so that the number of simultaneous changes of the logic decoding circuit can be made uniform, and a logic circuit for adjusting the load capacitance of the counting stages so that the load capacitance can be made uniform. The counter circuit may also include a test logic circuit for creating a test wave form on the basis of the outputs from the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance. Accordingly, it is possible to detect a failure of the logic circuits for adjusting the number of simultaneous changes and the logic circuits for adjusting the load capacitance which does not effect the counting output.

Abstract: The invention provides a pulse generating circuit including a single timer or counter which conducts both a event base count and a subsequent time base count according to clock signals about the event and time base counts, any one of which is selected by a selector. A pulse signal is generated from a RS flip-flop circuit. When the time base count follows the event base count, during the event base count, the output signal from the flip-flop is a 0 signal. During the time base count, the output signal from the flip-flop is a 1 signal. The event base count defines a delay of a pulse generated from RS flip-flop circuit and the time base count defines a width of the pulse.

Abstract: A method and circuitry are provided for modularized single transition counting. A count signal is provided on a count line (436). A single transition count is modified in response to the count signal. The single transition count has a plurality of bits (418, 416) provided by at least one first module (404) and at least one second module (406). The first (404) and second (406) modules are alternately coupled in series to an input module (402) so that one (404) of the first and second modules has an input (460a, 466a) coupled to an output (420, 468) of the input module (402) and so that each additional one (406) of the first and second modules has an input (482a, 488a) coupled to an output (472a, 478a) of an associated one (404) of the second and first modules, respectively.

Abstract: In the transmission of variable length data blocks, where data and addresses share the same bus lines, one of the other signals, which are present anyway (chip-select, CS-, read, write), indicates the block length. The first time slot following the setting of this signal is designated for an address (starting address), all subsequent time slots are designated for data, until the signal is reset. In this way, the length of the data block need not be known at the beginning of the transfer.

Abstract: A counter circuit includes a plurality of one-bit counters connected in series. The counter circuit includes first and second input terminals which are supplied with a predetermined signal, respectively, in an operational test mode. The counter circuit further includes a unit for alternately supplying a carry signal to a carry signal input of each one-bit counter in series when the predetermined signals are applied thereto. The unit may be composed of a plurality of OR circuits. Each OR circuit is provided with one input connected to the carry signal output of a one-bit counter at the preceding stage of the series, the other input connected to either the first input terminal or the second input terminal, and an output connected to the one-bit counter at the next stage.

Abstract: A display driving circuit includes a latch circuit provided with a resetting terminal for receiving a pulse signal having a constant period and a setting terminal, a logic product circuit for receiving an output signal of the latch circuit and the pulse signal, a counting circuit having a resetting terminal for receiving an output signal of the logic product circuit and a counting terminal for receiving a clock signal, the counting circuit outputting a data pulse every time a number of pulses of the clock signals reaches a preset constant value from a reception of the output signal of the logic product circuit; and a shift register for receiving the data pulse of the counting circuit at a data signal input terminal thereof and receiving the clock signal at a clock input terminal thereof, the latch circuit being adapted to receive the data pulse of the counting circuit at said setting terminal thereof.

Abstract: A circuit configuration includes k linking cells each generating one of k output states from two of k input states. Each of the linking cells have two counters. Each of the counters have a serial data input, a serial data output, and a serial counting width input. The counters increase a counter state loaded through the data input and represent the respectively assigned input state by a value input through the counting width input. Comparators are each connected to the data outputs of two of the counters for serially comparing the two counter states with one another. Multiplexers are each connected to the data outputs of two of the counters for outputting one of the two counter states as an output state under the control of the comparator.

Abstract: The invention includes a data memory having sequentially stored N-bit words that are each a binary description of a time at which an event is to occur. Also stored is a K-bit word, associated with each N-bit word, that is a binary description of what the scheduled event is to be. The invention utilizes a free-running clock and clock circuitry to gauge when an event should occur. The clock circuitry tallies an N-bit description of running time. M-bits of the N-bit description of running time are specified by a single fast synchronous counter. The remaining N-M bits are specified by two slow counters each of N-M bit capacity. Because incrementation of slow counters creates count settling times that may significantly affect accurate event sequencing, the slow counters are alternately incremented and a multiplexer is used to switch to the counter that will provide a "steady state" count at a scheduled event time.

Abstract: A digitalization assembly of the over-sampling type includes an analog to digital converter (2) producing at a frequency F=kf small-format p samples and a digital filter (3) which, through the summation of a certain number n of over-samples, produces validated larger P-format samples at the frequency f, at instants fixed by a clock. In order to readjust the sampling instants in relation to an outside event which can occur at any time, a temporary memory store (5) is inserted between the converter (2) and the filter (3) and, according to the instant of arrival of this event, the appropriate samples to be sent towards the filter for their summation are selected.

Abstract: A circuit having a delay circuit provided with a gate for converting the output signal of an SR flip-flop into a signal with a delay equal to or more than the clock pulse width enough for count operation and leading the logical addition between the signal and system clock and the logical multiplication between the signal and counter write signal to the direct reset input of a transparent latch 7 and for realizing read-on-the-fly or write-on-the-fly operation even if timer input does not synchronize with the system clock.

Abstract: A precise digitally-controlled variable attenuation circuit for adjusting e attenuation of a signal in an external circuit includes a signal magnitude detector, a resistance adjustment control, and a resistance divider network. The signal magnitude detector has lower and upper threshold limits representing a desired range of attenuation and is operable to receive and compare a control signal with the lower and upper threshold limits, and, in response thereto, produce either a first signal if the control signal is less than the lower threshold limit or a second signal if the control signal is greater than the upper threshold limit. The adjustment control is capable of receiving the first and second signals and is operable to produce either a digital count-down signal in response to the first signal or a digital count-up signal in response to the second signal. The resistance divider network has a fixed resistance and a digitally-adjustable device with a variable resistance.

Abstract: An electrical apparatus (e.g., copying apparatus) equipped with a counter for counting the number of specific cycles. Allowance or prevention of an operation cycle is controlled in accordance with voltage changes at a predetermined position of the controlling circuitry supplying a driving voltage to the counter. A specific operation of the electrical apparatus is enabled by connection of counter.

Abstract: A digital counting method and device for evaluating a digital signal (S.sub.S) using a digital counter (Z) applies the digital signal (S.sub.s) that is received by the input (ZE) of the digital counter (Z) as an output signal (N+1) to represent another binary position, in addition to the output signals (N) from the digital counter (Z).

Abstract: A reload timer circuit comprises an n-bit up/down counter circuit for receiving input data of n bits and providing up/down count data of n bits; an n-bit timer circuit for receiving the n-bit up/down count data and providing timer data of n bits; and a timer period setting means for generating a timer period signal in response to an overflow signal of the n-bit timer data and providing the n-bit up/down counter circuit with the timer period signal. This reload timer circuit automatically sets a reload value by hardware without relying on software, thereby reducing the load on a central processing unit.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.