Abstract: An object is to provide an imaging device in which a circuit for reading a signal is provided in a pixel region. The imaging device includes a first pixel and a second pixel. The first pixel is capable of outputting a first signal output from a pixel circuit included in the first pixel or a second signal input from the first pixel in the previous stage, to the first pixel or the second pixel in the next stage. The second pixel is capable of outputting, to the outside, the first signal or the second signal, which is input from the first pixel in the previous stage, or a third signal output from a pixel circuit included in the second pixel.

Abstract: An image sensor may include an imaging pixel, readout circuitry, and amplification circuitry coupled between the imaging pixel and the readout circuitry. Correlated double sampling may be used to sample a reset voltage and a signal voltage from the imaging pixel. The difference between the reset voltage and the signal voltage may reflect the amount of light received by the imaging pixel during an integration time. The amplification circuitry may amplify the difference between the reset voltage and the signal voltage. The amplification circuitry may include a source follower transistor coupled between first and second capacitors, with the second capacitor having a greater capacitance than the first capacitor. The amplification circuitry may be formed only from n-type metal-oxide-semiconductor transistors. The amplification circuitry may consume power dynamically as opposed to consuming static power for minimal power consumption requirements.

Abstract: Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.

Abstract: A method for detecting damage to a converter device of a lighting apparatus is provided. The method may include irradiating the converter device with input light, detecting a useful light portion emitted principally by a first section of the converter device by means of a first sensor element. A first detection signal is obtained, detecting a useful light portion emitted principally by a second section of the converter device, said second section being different than the first section, by means of a second sensor element. A second detection signal is obtained. The method further may include automatically obtaining damage information about the converter device from a ratio or a difference of the first detection signal with respect to either the second detection signal or a comparison signal formed therefrom.

Abstract: Pixel arrangements in time-of-flight sensors are presented that include sensing elements that establish charges related to incident light, charge storage elements that accumulate integrated charges transferred from the sensing elements, and diffusion nodes configured to establish measurement voltages representative of the integrated charges that are dumped from the charge storage elements. The pixel arrangement includes analog domain output circuitry comprising a measurement capacitance element that stores the measurement voltage, and a reset capacitance element that stores a reset voltage established at the diffusion node during a reset phase performed prior to a measurement phase. The analog domain output circuitry subtracts the stored reset voltage from the stored measurement voltage for processing into a pixel output voltage that at least partially reduces readout voltage uncertainty of the pixel arrangement.

Abstract: When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus m.

Abstract: A dual sensitivity image sensor provides a standard mode and a high-sensitivity mode of operation via iSoC integration. In addition to boosting sensitivity, the high sensitivity mode also reduces temporal noise thereby optimally boosting the Signal-to-Noise Ratio (SNR) of the image sensor. The circuit does not significantly increase pixel complexity and requires minimal changes to the support circuits in the iSoC including the addition of support and control circuitry to facilitate seamless mode change.

Abstract: An imaging device includes a first electrode for generating an electric field storing signal charges, a charge multiplication section for multiplying the stored signal charges, a second electrode for generating the electric field in the charge multiplication section, a voltage conversion portion for converting the signal charges into a voltage, a third electrode for transferring the signal charges to the voltage conversion portion, provided between the first electrode and the voltage conversion portion, wherein the second electrode is provided on a side opposite to the third electrode and the voltage conversion portion with respect to the first electrode.

Abstract: A system of taking images of different sensitivities at the same time uses both an image sensor, and an auxiliary part to the image sensor. The image sensor element can be a photogate, and the auxiliary part can be the floating diffusion associated with the photogate. Both the photogate and the floating diffusion accumulate charge. Both are sampled at different times. The floating diffusion provides a lower sensitivity amount of charge than the photogate itself. The system can have a photogate and floating diffusion in each pixel along with a select transistor, a reset transistor, and a follower transistor. All of this circuitry can be formed of CMOS for example. The system can also operate in a column/parallel mode, where each column of the photo sensor array can have a column signal processor which samples and holds the reset signal, the floating diffusion signal and the photogate signal.

Abstract: A charge multiplication amplifier device comprises a series arrangement of a first separation barrier facility, a temporary storage well for charge carriers, a second charge transfer barrier facility, an impact ionization facility that is operative through electric field strength effective on mobile charge carriers, and a charge collection well for receiving charge carriers so multiplied. Advantageously, the device comprises a charge collection and transfer facility (32) that is geometrically disposed next to the impact ionization facility (31) whereas impact ionization facility is controlled at a substantially static electric potential (DC1, DC2) for controlling the electric field strength. Advantageously, another embodiment of this device comprises charge collection and transfer facilities (41, 42) implemented as two (or more) independently clocked signals ?1, ?2 that require nearly two times less swing to achieve same effect.

Abstract: Methods and apparatus for imaging light are disclosed. Light is imaged by collecting light, converting the collected light into a electrical charge signal, multiplying the electrical charge signal to produce multiple electrical charge signals with associated levels of gain, converting the electrical charge signals to voltage signals, and developing an output signal from one or more of the voltage signals that represents the collected light. The electrical charge signal may be multiplied using an electron multiplication device associated with multiple taps to produce the electrical charge signal with different levels of gain.

Abstract: A mixing of color that follows mixing of horizontally adjoining information charges corresponding to different colors is minimized during an operation for adding information charges of a plurality of pixels in a horizontal direction and during a high-speed horizontal transfer operation in a horizontal CCD shift register of a CCD image sensor. An impurity is used for forming barrier regions having a shallow channel potential among the barrier regions and storage regions that constitute transfer stages of the horizontal CCD shift register. The concentration of the impurity is established separately in a main portion, which is composed of transfer stages that are connected to the output ends of vertical CCD shift registers, and in a dummy portion, which connects the main portion with an output section and has a width that gradually decreases towards the output section. The barrier potential is therefore also established separately in the main portion and the dummy portion.

Abstract: The present invention provides permutation instructions usable in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform permutations by a sequence of instructions with each sequence specifying the position in the source for each bit in the destination. In the PPERM instruction bits in the destination register that change are updated and bits in the destination register that do not change are set to zero. In the PPERM3R instruction bits in the destination register that change are updated and bits in the destination register that do not change are copied from intermediate result of previous PPERM3R instructions. Both PPERM and PPERM3R instructions can individually do permutation with bit repetition. Both PPERM and PPERM3R instructions can individually do permutation of bits stored in more than one register. In an alternate embodiment, a GRP instruction is defined to perform permutations.

Abstract: A photo-detector generated signal is measured as a sample set comprising a long signal and a short signal. The short signal is scaled to the value of the long signal if the long signal exceeds a dynamic range associated with the photo detector. In one embodiment, the short signal is obtained during a short time interval that is at the approximate middle of a long time interval such that the short and long intervals share a common median time value. Given such symmetry, an approximately linear signal yields a proportionality parameter between the long and short signals thereby allowing the short signal to be scaled. The proportionality parameter facilitates determination of an integration independent component of the photo detector signal that should be removed from the measured long and short signals before scaling. A plurality of sample sets can also be processed such that each sample set overlaps with its neighboring sample set, thereby increasing the effective number of sample sets.

Abstract: This invention controls the signal amplification rate in a simple way with high precision in a CMD or CMD-carrying CCD device. CMD 12 has plural sections, such as M sections (U1-UM), each of which is a CMD unit U that can perform a charge multiplication operation, set in series. Each section of CMD unit Ui has plural (such as 4) electrodes G1, G2, G3, G4 set in a row via an insulating film, such as silicon oxide film 100, on a silicon insulating film. Among driving voltages P1, P2, P3, P4 applied on the electrodes G1, G2, G3 and G4, P1 and P2 are applied in the same cycle as the transfer clock, P4 for impact ionization is applied in intermittent cycles with respect to P1 and P2, and P3 is applied as a DC voltage at a prescribed level.

Abstract: There is provided a register system of a microcomputer having a register that includes at least one register bit and having an additional storage arrangement allocated to the register and on which the data content of the register is able to be intermediately stored. To reduce the computing time for saving the data content of the register, while keeping the silicon surface required for the register system as small as possible, the additional storage arrangement includes at least one shift register having at least two shift register cells, the content of an arbitrary shift register cell being transferable into a register bit, and, conversely, the content of a register bit being transferable into an arbitrary shift register cell.

Abstract: A charge transfer device of the present invention includes: a floating diffusion amplifier type charge detecting portion containing a reset gate and a reset drain; and a source follower circuit including a detecting transistor having substantially the same potential profile as a potential profile of the reset gate of the charge detecting portion and a load transistor connected to the detecting transistor, wherein an output from the source follower circuit is supplied to the reset drain of the charge detecting portion, a first voltage, which is generated by resistance-dividing a power-supply voltage to be supplied to a drain of the source follower circuit, is commonly applied to each gate of the detecting transistor and the load transistor, a second voltage, which is generated by resistance-dividing the power-supply voltage, is applied to the reset gate of the charge detecting portion via a clamp circuit, whereby the charge transfer device is controlled in such a manner that a reset operation is always perform

Abstract: A phase-locked loop (PLL) includes a down counter having a detection circuit configured to determine when the counter reaches its terminal count. The down counter also includes a control line configured to alter the terminal count detected by the detection circuit by an off-set.

Abstract: In a molecule detection system and method, a sample containing target molecules is added to an array of test sites, with each test site containing distinct probe molecules. The probe molecules bind with the target molecules in the sample to form bound complexes. A source illuminates the array of test sites with incident electromagnetic radiation, and an active pixel sensor detects the electromagnetic radiation from the array. To detect the presence of target molecules in the sample, the active pixel sensor detects changes in the optical properties of the test sites that result, either directly or indirectly, from their binding of the probe molecules with the target molecules. The target molecules may also be characterized on the basis of which probe molecules bind to them.

Abstract: A method for reducing dark current within a charge coupled device includes the steps of providing three or more phases of gates separated by an insulating layer from a buried channel of the first conductivity type in a well or substrate of the second conductivity type, and a clock driver for causing the transfer of charge through the charge coupled device; providing a barrier for separating charge packets when in accumulation state; applying, at a first time period, voltages to all phases of gates sufficient to cause the surface of the first conductivity type to be accumulated by dark current reducing charge carriers; after the first time period, applying, at each gate phase n having a capacitance Cn to the layer of the second conductivity type, a voltage change on the gate phase n given by &Dgr;Vn such that the sum of products of the capacitances and voltage changes is substantially zero ∑ n ⁢   ⁢

Abstract: By providing a semiconductor device including a charge transfer channel to one end of which electric charges supplied from a charge supply unit are input, and which includes a plurality of branching regions at an intermediate portion, a plurality of gate electrodes provided on the corresponding branching regions of the charge transfer channel via insulating films, an input-signal supply unit for supplying each of the gate electrodes with an input signal, a transfer electrode, provided on the charge transfer channel via a gate insulating film, for performing control so that the electric charges are transferred in a predetermined direction within the charge transfer channel, a conversion unit for coverting the transferred electric charges into a voltage, and a sense amplifier to which an output signal from the conversion unit is input, and by providing a semiconductor circuit which includes such a device, it is possible to reduce the scale of circuitry, increase the calculation speed, and reduce electric power

Abstract: An image obtaining method and apparatus for an endoscope, wherein the S/N ratio of an observation image formed from the image signal obtained by a solid state image obtaining element equipped with a charge multiplying shift resistor is improved. A signal charge representing a fluorescent image is obtained of the fluorescent image formed of the fluorescent light emitted from a target subject upon the irradiation thereof by an excitation light emitted from an illuminating means, by a charge multiplying shift resistor. A readout means reads out the signal charge and outputs an image signal based on the read out signal charge. In obtaining an observation image signal based on the read out image signal, a computing means subtracts the dark noise image signal component from the read out image signal to obtain the observation image signal.

Abstract: A pixel sensor cell for use in a CMOS imager exhibiting improved storage capacitance. The source follower transistor is formed with a large gate that has an area from about 0.3 &mgr;m2 to about 10 &mgr;m2. The large size of the source follower gate enables the photocharge collector area to be kept small, thereby permitting use of the pixel cell in dense arrays, and maintaining low leakage levels. Methods for forming the source follower transistor and pixel cell are also disclosed.

Abstract: The first present invention provides a circuit for processing charge detecting signal transferred to a floating diffusion amplifier from a charge coupled device. The circuit comprises: a first node connected to the floating diffusion amplifier; a first enhancement type field effect transistor being connected in series between a first fixed-voltage supply line for supplying a first fixed voltage and an output terminal, and the first enhancement type field effect transistor having a first gate connected to the first node; and a second enhancement type field effect transistor being connected in series between a second fixed-voltage supply line for supplying a second fixed voltage and the output terminal, wherein the second enhancement type field effect transistor has a second gate supplied with a third fixed voltage which is different in potential from the second fixed voltage.

Abstract: A charge transferring device includes a detection MOSFET for detecting a signal charge, a reset MOSFET for removing the signal charge after the signal charge is detected. The reset MOSFET includes a floating diffusion layer to which the signal charge is transferred, an impurity layer to which a reset voltage is applied, and a reset gate electrode to which a reset signal is supplied. The detection MOSFET includes a detection gate electrode connected with the floating diffusion layer. The floating diffusion layer includes a first semiconductor region and a second semiconductor region whose impurity concentration is lower than that of the first semiconductor region. The impurity concentration of the first semiconductor region is set to a concentration such that the first semiconductor region is not depleted in a voltage lower than the reset voltage when the reset signal is supplied to the reset gate electrode.

Abstract: The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.

Abstract: A circuit technique to reduce the input capacitance line of a charge integrator is described. This approach is particularly tailored for embedded read-out circuits in solid-state integrated sensors. An integrated charge amplifier described herein includes a generic amplifier element and a high speed buffer which drives a metal shield placed underneath the input line. The metal shield therefore follows the potential of the input line and thereby reduces the capacitance between the input line and ground.

Abstract: A charge-coupled device has a first P-type well layer which forms a charge transfer section and a second P-type well layer which forms a floating diffusion layer section and within which the first P-type well layer is formed. The second P-type well layer below the floating diffusion layer section has an impurity concentration lower than that of the first P-type well layer whereby a depletion layer formed therein by a PN-junction flares in the direction to the second P-type well layer. With this arrangement, it is made possible to reduce the floating diffusion capacitance and to maintain a large output voltage with respect to a signal electron charge.

Abstract: There is provided a solid-state image sensor including (a) a photoelectric converter which converts light into electric charges, (b) a transfer section which transfers the electric charges, (c) a floating diffusion layer which converts the transferred electric charges into a voltage, and (d) a multi-staged source follower circuit which amplifies and then outputs the voltage, a distance L2 between a wiring through which drain potential is supplied and a gate electrode in a first-stage MOSFET being longer than the same in second or later MOSFETs. In accordance with the solid-state image sensor, it is possible to reduce a capacity of a gate electrode in a first-stage MOSFET, which ensures high sensitivity even in a solid-state image sensor having small-sized pixels which deal with a small quantity of electric charges.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: A solid-state photographic element that can perform electronic shutter action simultaneously for all pixels is disclosed. Each pixel includes a photoelectric converter (such as a photodiode), a first transfer gate, a charge storage element, a second transfer gate, an amplifier, and a reset element. All photodiodes are first reset, then the first transfer gates selected OFF at the same time and charges accumulate in all photodiodes simultaneously. After a predetermined shutter time has elapsed, the first transfer gates are selected ON at the same time and charges that accumulated in the photodiodes are transferred to the corresponding charge storage elements. Thereafter, first transfer gates are selected OFF. A vertical scanning circuit may then select second transfer gates ON sequentially for each row, so that charges accumulated in the charge storage elements are transferred to control regions of corresponding amplifiers.

Abstract: A method and device for the electrolytic formation of a deposit on a group of electrodes of an electrolysis support. The support has a plurality of electrodes. Electric charges are selectively deposited on chosen electrodes. The support is placed in the presence of an electrolyte to produce the deposit on the chosen electrodes by electrolysis. The electric charges deposited on the electrodes provide an electrolysis current for each chosen electrode. The formed device may be used as a biological sensor.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor Integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Abstract: A system and method is described for increasing effective integration time of an optical sensor including holding a first signal within each pixel cell, proportional to light integrated by the pixel cell over the previous frame period, generating a second signal within each pixel cell proportional to light integrated by the pixel cell over the current frame period, and summing the first signal and the second signal from each pixel, thereby producing an output signal representing the light integrated by each pixel over two frame periods.

Abstract: The present invention is embodied in a charge coupled device (CCD)/charge injection device (CID) architecture capable of performing a Fourier transform by simultaneous matrix vector multiplication (MVM) operations in respective plural CCD/CID arrays in parallel in O(1) steps. For example, in one embodiment, a first CCD/CID array stores charge packets representing a first matrix operator based upon permutations of a Hartley transform and computes the Fourier transform of an incoming vector. A second CCD/CID array stores charge packets representing a second matrix operator based upon different permutations of a Hartley transform and computes the Fourier transform of an incoming vector. The incoming vector is applied to the inputs of the two CCD/CID arrays simultaneously, and the real and imaginary parts of the Fourier transform are produced simultaneously in the time required to perform a single MVM operation in a CCD/CID array.

Abstract: An interline sensor is constructed using photocapacitors. The vertical shift register of the interline sensor is operated in a uniphase mode, i.e., holding one of the two phase (.O slashed.2) at a D.C. potential while fluctuating the other phase (.O slashed.1) between a voltage that is sufficiently above and below that D.C. potential to facilitate transfer of charge from one phase to the next. The uniphase mode is facilitated by a single electrode that covers both the phase that is held at a constant D.C. potential and the photodetector having photocapacitor charges. The single electrode in the preferred embodiment is an indium tin oxide electrode. The charges are transferred from the photocapacitors to the vertical shift register by a third level clock into .O slashed.1 adjacent the photodetectors.It is also proposed that the same ITO electrode be utilized to for phase 2 of both the vertical and horizontal CCD shift registers.

Abstract: A charge transfer device comprising charge transfer means for transferring charges, a floating diffusion layer for accumulating the charges transferred from said charge transfer means, a floating gate electrode formed on said floating diffusion layer via an insulating layer, charge detection means connected to the floating gate electrode for outputting a voltage corresponding to an amount of charges accumulated in the floating diffusion layer, first precharge means connected to the floating gate electrode, the first precharge means starting precharging of the floating gate electrode responsive to transition of a first pulse voltage from a first state to a second state, the first precharge means terminating precharging of the floating gate electrode responsive to transition of the first pulse voltage from the second state to the first state, second precharge means connected to the floating diffusion layer, the second precharge means starting precharging of the floating diffusion layer responsive to transition

Abstract: An interline sensor is constructed using photocapacitors. The vertical shift register of the interline sensor is operated in a uniphase mode, i.e., holding one of the two phase (.phi.2) at a D.C. potential while fluctuating the other phase (.phi.1) between a voltage that is sufficiently above and below that D.C. potential to facilitate transfer of charge from one phase to the next. The uniphase mode is facilitated by a single electrode, an indium tin oxide electrode, that covers both the phase that is held at a constant D.C. potential and the photodetector having photocapacitor charges. The charges are transferred from the photocapacitors to the vertical shift register by a third level clock into (.phi.1) adjacent the photodetectors utilizing the same ITO electrode for phase 2 of both the vertical and horizontal CCD shift registers is also proposed.

Abstract: In a charge coupled device including a semiconductor substrate having a semiconductor region, a plurality of nonactive barrier electrodes, a plurality of first electrodes and a plurality of second electrodes arranged between the nonactive barrier electrodes, an outermost one of the nonactive barrier electrodes is electrically isolated from the others of the nonactive barrier electrodes.

Abstract: A general absolute value circuit for developing a true, symmetric or bipolar, absolute value output signal from an input charge signal, compact enough to be used on a sensor chip incorporated into (or used in combination with) a pixel processor of the type used in imaging and other systems that collect electromagnetic radiation as part of on-chip circuitry, includes a balanced differential amplifier combined with a merged dual shelf transistor structure. The balanced differential amplifier, in response to an input charge signal, drives the merged dual shelf transistor structure which in turn generates the desired true absolute value output signal. Such circuitry may be used in imaging systems to implement focal-plane processing algorithms or may be used for performing a single read true absolute value computation by a pixel processor located on a sensor chip. The merged dual shelf transistor structure enhances performance and speed of the processor in which it is incorporated.

Abstract: The charge coupled device (CCD) charge detection system includes a first CCD register having N non-destructive charge readouts where N is an integer greater than one, and N second CCD registers coupled to the N non-destructive charge readouts where each of the N second CCD registers is coupled to a corresponding one of the N non-destructive charge readouts.

Abstract: A supply-voltage-monitoring circuit, for low-power integrated circuits, in which charge-sharing through a switched-capacitor chain is used to couple the supply voltage to a dynamic sensing node. The dynamic sensing node drives a half-latch, which is stable in a no-alarm condition.

Abstract: A charge transfer apparatus which is capable of reliably improving the transfer efficiency of an output gate section while preventing the occurrence of coupling to output waveforms. A two-phase driving-type charge transfer apparatus is constructed as follows. Transfer clock .phi.H2 used for driving the stage one prior to the final stage of a charge transfer section is divided at a predetermined ratio through the use of two resistors. This causes the generation of drive pulse .phi.OG in phase with and of a smaller amplitude than transfer clock .phi.H2. A gate electrode of an output gate section is driven by this drive pulse .phi.OG.

Abstract: A switched CCD electrode photodetector includes a substrate made of first semi-conductor type, a drain made of a second semi-conductor type formed in the substrate, a collection well made of the second semi-conductor type formed in the substrate, and a switched CCD electrode resistor formed between the drain and the collection well. The collection well is operable in cooperation with a photosensitive region. The switched CCD electrode resistor includes a channel region defined in the substrate and having a first end disposed adjacent to the collection well and a second end disposed adjacent to the drain. The switched CCD electrode resistor also includes a first electrode insulatively spaced from and disposed over the first end and a second electrode insulatively spaced from and disposed over the second end.

Abstract: A time-multiplexed floating diffusion output amplifier provides two output signals with different gains for each signal charge packet by dynamically controlling the floating diffusion capacitance using two external reset clocks. Two correlated double sampling circuits separately remove the noise components associated with resetting the two different floating diffusion capacitance values.

Abstract: The image sensor charge detection amplifier has a charge storage well 60, a charge sensor 32 for sensing charge levels in the charge storage well 60, a charge drain 28 adjacent to the charge storage well 60, and charge transfer structures for transferring charge from the charge storage well 60 to the charge drain 28.

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: A charge transfer device formed on a semiconductor substrate comprising: a charge transfer section formed on the semiconductor substrate for transferring charges, a floating gate having a floating gate diffusion layer formed on the semiconductor substrate for accumulating the charges transferred from the charge transfer section, an output gate section formed between the charge transfer section and the floating gate on the semiconductor substrate, and a charge detecting circuit electrically connected to the floating gate for outputting a voltage corresponding to the amount of the charges accumulated in the floating gate diffusion layer, the output gate section having a first output gate region adjacent to the charge transfer means and a second output gate region adjacent to the floating gate diffusion layer, the first output gate region having a first output gate electrode formed thereon with an insulating film therebetween, the second output gate region having a second output gate electrode formed thereon wit

Abstract: Described is a new high performance CCD image sensor technology which can be used to build a versatile image sensor family with the sensors that have high resolution and high pixel density. The described sensor architectures are based on a new charge super sweep concept which was developed to overcome such common problems as blooming and the image smear. The charge super sweep takes place in very narrow vertical channels located between the photosites similar to the Interline Transfer CCD devices. The difference here is that the charge is never stored in these regions for any significant length of time and is swept out using a new resistive gate traveling wave sweeping technique. The charge super sweep approach also allows the fast charge transfer of several lines of data from the photosites located anywhere in the array into the buffer storage during a single horizontal blanking interval.

Abstract: A CCD linear sensor as a solid-state imaging device has a photosensor and a pair of CCD registers connected to the photosensor. One of the CCD registers is supplied with first two-phase transfer clock signals for transferring electric charges from the photosensor to a first signal converter, and the other CCD register is supplied with second two-phase transfer clock signals for transferring electric charges from the photosensor to a second signal converter. The second two-phase transfer clock signals are shifted a 1/2 clock period from the first two-phase transfer clock signals. The CCD registers have the same number of dummy registers on their output ends for transferring the electric charges therethrough to the first and second signal converters, which convert the transferred electric charges into output signals that are in phase with each other. The periods of the output signals and the negative-going edges, i.e.