Abstract: A shift operation circuit includes: shift circuits respectively coupled internal buses whose bit numbers partially overlap, each shift circuit receiving one of sets of divided data obtained by dividing input data and one of shift amount signals and outputting the corresponding divided data to a range shifted based on a shift amount represented by the corresponding shift amount signal from a reference bit position in the corresponding internal bus; a shift control circuit configured to output, during a first mode, shift amount signals whose shift amounts are common to the shift circuits, and configured to convert, during a second mode, a shift amount signal for each shift circuit, into a shift amount signal representing a shift range whose bit numbers do not overlap in the internal buses; and a bit selecting circuit configured to select valid divided data from bits whose bit numbers overlap in the internal buses.

Abstract: The present invention provides a shift register and a method for driving the same, a gate driving circuit and a display device, the shift register includes a NOR gate circuit, a latch circuit and an output control circuit. First to fourth input terminals of the NOR gate circuit are connected to a clock control signal terminal, a signal input terminal, a high-level power supply terminal and a low-level power supply terminal, respectively, and an output terminal thereof is connected to a first input terminal of the latch circuit; second to fourth input terminals of the latch circuit are connected to the signal input terminal, the high-level power supply terminal and the low-level power supply terminal, respectively, and first and second output terminals thereof are both connected to the output control circuit, which is connected to the clock control signal terminal, the low-level power supply terminal and a signal output terminal.

Abstract: A display device including various portions, circuits and other arrangements for outputting various pulses and triggers, for controlling forward shift and backward shift operations.

Abstract: A plurality of cascaded unit register circuits which comprises a bidirectional shift register include main stages and dummy stages at the top before the main stages and dummy stages at the bottom after the main stages. A k-th stage outputs a pulse Pk in synchronization with a clock signal with a reference point N1 being at H level. The main stages include terminals NSF and NSB for setting N1 to H to which Pk?1 and Pk+1 are input, respectively, and terminals NRB and NRF for setting N1 to L level to which Pk?2 and Pk+2 are input, respectively. The order of generation of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched. Top dummy stages do not have NRB. Bottom dummy stages do not have NRF.

Abstract: A bidirectional shift register outputs pulses from a plurality of cascaded unit register circuits in a shift order which is one of a forward direction and a reverse direction. A ?th stage of unit register circuit (38) has two set terminals connected to respective outputs of (??1)th and (?+1)th stages and two reset terminals connected to respective outputs of (?+2)th and (??2)th stages. The unit register circuit (38) sets, when a pulse is input to any one of the set terminals, a reference point N1 to an H level, and, when a pulse is input to any one of the reset terminals, N1 to an L level. The order of phase change of clock signals is reversed according to the direction of a shift, and whether a start trigger signal is applied to a top stage or a bottom stage is switched.

Abstract: A driving device of a liquid crystal display (LCD) utilized for preventing noises of a clock signal from causing error operation of a shift register is disclosed. The driving device includes a shift register, a reception terminal, a noise elimination circuit and a control signal generation circuit. The reception terminal is utilized for receiving a first clock signal. The noise elimination circuit is coupled to the reception terminal, and is utilized for eliminating noises of the first clock signal and delaying the first clock signal for a preset time to generate a second clock signal. The control signal generation circuit is coupled to the reception terminal, the noise elimination circuit and the shift register, and is utilized for generating a first control signal and a second control signal to control the shift register.

Abstract: A sensor scan driver may include a shift register unit for driving photodiodes, a transmission gate unit for changing a voltage range of sensor scan signals generated by the shift register unit, and a buffer unit for supplying the sensor scan signals supplied from the transmission gate unit to the photodiodes, wherein the transmission gate unit includes first and second transmission gates, each including an electrode adapted to receive an output signal of the shift register unit, another electrode adapted to receive the inverted output signal of the shift register unit, an input terminal coupled to first and second power sources, respectively, and an output terminal coupled to an output terminal of the transmission gate unit.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: A signal output circuit of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.

Abstract: A system for displaying images includes a display device. The display device includes a timing control circuit, a display matrix, a horizontal driving circuit and a horizontal signal processing circuit. The timing control circuit generates a plurality of timing signals. The display matrix includes a plurality of display elements arranged in a matrix, wherein the display elements are vertically divided into N banks to be updated sequentially. The horizontal driving circuit is coupled to the timing control circuit for generating a plurality of switch signals according to the timing signals and sequentially turning on the banks. The horizontal signal processing circuit is coupled to the timing control circuit, the horizontal driving circuit and the display matrix for determining a turning-on period for each bank according to the timing signals and the switch signals.

Abstract: A driving circuit applied in an electronic display apparatus is provided. The driving circuit includes a first exchange circuit and a first buffer. The first buffer includes first and second input stages, a second exchange circuit and first and second output stages. The first exchange circuit selectively couples a first input signal and a first output signal outputted from the first output stage to one of the first and the second input stages; and selectively couples a second input signal and a second output signal outputted from the second output stage to the other of the first and the second input stages. The second exchange circuit selectively couples the first input stage to one of the first and the second output stages and selectively couples the second input stage to the other of the first and the second output stages.

Abstract: The present invention relates to a shift register and a liquid crystal display using the same. The liquid crystal display includes a liquid crystal panel, a data driving circuit and a scanning driving circuit. The data driving circuit and the scanning driving circuit each include a shift register. The shift register includes a plurality of shift register units. Two adjacent shift register units respectively receive two inverse clock signals and a VGL signal. Each shift register unit includes a signal output circuit, a signal input circuit, a first logic converting circuit, and a second logic converting circuit. The present shift register and a liquid crystal display have simple structure.

Abstract: An exemplary shift register includes a plurality of shift register units, each of which includes an output circuit, an input circuit, and a logic circuit. The output circuit includes a clock transistor, a voltage stabilizing transistor, and an input circuit for receiving signals output by a previous shift register unit. The logic circuit receives signals output by the input circuit. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal.

Abstract: A control section prepares a control signal and supplies the control signal to a control terminal of a first switching element, the control signal causing the first switching element to turn on in accordance with a non-active voltage level of a storage node and an active voltage level of a second clock signal which active voltage level is obtained in a period in which the second clock signal is active.

Abstract: An asynchronous logic family of circuits which communicate on delay-insensitive flow-controlled channels with 4-phase handshakes and 1 of N encoding, compute output data directly from input data using domino logic, and use the state-holding ability of the domino logic to implement pipelining without additional latches.

Abstract: A shift register capable of reducing power consumption is provided. The shift register includes: a clock signal supply line for supplying a clock signal; a plurality of selectors coupled to the clock signal supply line to generate driving signals in response to sampling signals; and a plurality of stages respectively coupled to the selectors to generate the sampling signals in response to the driving signals, wherein at least one of the selectors is adapted to generate at least one of the driving signals in response to a previous one of the sampling signals supplied from a previous one of the stages and a next one of the sampling signals supplied from a next one of the stages.

Abstract: It is provided a method of controlling a shift register in which a plurality of transfer unit circuits, each having a storage unit and a writing unit, are connected in series. The storage unit has a hold gate and stores a logical level of a pulse when the hold gate is in an active state, and the writing unit has a writing gate and stores a pulse in the storage unit when the writing gate is in an active state.

Abstract: A shift register circuit includes plural stages of signal holding circuits which are cascade-connected to hold a signal based on a supplied input signal, to output an output signal based on the held signal, and to supply the output signal as an input signal to a subsequent stage. Each of the plural stages of signal holding circuits includes an output circuit which is supplied with two types of clock signals consisting of a first clock signal and a second clock signal. A timing of the second clock signal is delayed by a predetermined delay time with respect to a timing of applying the input signal, which is supplied with a signal at a timing delayed by the delay time of the second clock signal from the timing of applying the input signal, and which outputs the output signal at a timing responsive to the first clock signal.

Abstract: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

Abstract: A display having a shift register circuit capable of suppressing increase of power consumption is provided. This display comprises a shift register circuit including a shift register circuit portion including a first circuit portion having a second transistor turned on in response to a first signal and a second circuit portion having a sixth transistor turned on in response to a second signal providing an ON-state period not overlapping with an ON-state period of the second transistor and an input signal switching circuit portion for switching the first and second signals supplied to the second and sixth transistors respectively.

Abstract: A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal.

Abstract: A semiconductor integrated circuit apparatus includes a periodic signal generation circuit connected with N logical circuits, wherein the N is a natural number, outputting a periodic signal. The periodic signal generation circuit includes a reset circuit outputting a reset signal initializing according to outputs from a first stage logic circuit to N?1th logic circuit.

Abstract: A radiation device includes a detector connected to a multi-functional radiation identifying and processing application specific integrated circuit. The detector includes a plurality of individual imaging cells, each imaging cell generating a charge in response to incident radiation events and outputting the generated charge at an imaging cell output. The application specific integrated circuit includes a different circuit connected respectively to a corresponding one of the imaging cell outputs, each circuit receiving and processing the generated charge received from the corresponding one imaging cell output. Each circuit includes a preamplifier for generating a voltage or current amplitude in response to the received charge, a counter, and a mode logic configured for setting the counter to perform, selectively, at least two of a) photon counting, b) analog to digital conversion of the one of the voltage amplitude and the current amplitude, and c) timing measurement of incident radiation events.

Abstract: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

Abstract: A high voltage shift register stage which directly accepts low voltage clock signal inputs without using clock buffers. In particular, a shift register stage circuit is adapted to operate with a low voltage swing clock signal, with the stage circuit having a single state node, a, driven directly. This arrangement allows for reduced power consumption and higher operating speeds.

Abstract: A shift register including a plurality of stage circuits is provided. Each of the stage circuits has a shift circuit for receiving an input signal and providing an output signal. The output signal is obtained through the logic calculation and delaying of the input signal. Each of the stage circuits, except the first one, further includes a logic circuit used to produce at least one control signal according to the internal signals of the containing stage circuit, so as to replace at least one of the required clock signals during the operation of the corresponding shift circuit.

Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Abstract: The shift register, which is an n-th shift register of a shift register chain, includes a first multiplexer, a second multiplexer, and a latch block, wherein n is a positive integer. The first multiplexer selects one of output data of the (n?1)-th shift register or output data of the (n+1)-th shift register and outputs the selected data to be used as a reset signal in the latch block. The second multiplexer selects one of the output data of the (n?1)-th shift register or the output data of the (n+1)-th shift register and outputs the selected data to be used as input data of the latch block. The latch block stores the output data of the second multiplexer in response to the clock control signal, the inverted clock control signal and the reset voltage, and outputs the stored data.

Abstract: A dynamic sequential device is provided that is adapted for scan control and observation. The dynamic sequential device may be scanned in-circuit as part of a scan chain in a VLSI device or it may be scanned as a discrete device. The dynamic sequential device maintains performance with respect to speed while allowing control and observation of its internal machine states.

Abstract: A clock generating circuit of a semiconductor integrated circuit device includes a plurality of stages of frequency-dividing circuits connected in series, of which a first stage receives a reference clock signal, each frequency-dividing circuit requiring no reset signal; and a plurality of buffers respectively transmitting a reference clock signal and output clock signals of the plurality of frequency-dividing circuits to an internal circuit of the semiconductor integrated circuit device. Therefore, a plurality of clock signals having different frequencies with aligned edges can be generated without the need for separately providing an external pin for inputting the reset signal or a circuit for generating the reset signal.

Abstract: A shift register with low power consumption has memory circuits 151-15N connected in series, gate circuits in memory circuits 152n−1 in the odd-numbered locations become conductive when clock signal CK is high, and gate circuits in memory circuits 152n in the even-numbered locations become conductive when clock signal CK is low, wherein data signals S input are latched for output when the gate circuits are shut off. The circuit configuration is simplified. The Shift register operates every one half of the cycle of clock signal CK, allowing the frequency of clock signal to be reduced by half, resulting in reduced power consumption.

Abstract: A circuit for limiting loss in a second circuit. The circuit may include a first timer, a second timer and one or more logic gates. The first timer may produce a first output in a given state if the duration of a pulse for use with the second circuit reaches a first predetermined amount of time, where the first predetermined amount of time is related to a parameter of the second circuit. The second timer may produce a second output in the given state if the first timer does not produce the first output in the given state when the duration of the pulse reaches a second predetermined amount of time. The one or more logic gates may have an output that is the same as the pulse unless and until the output of the first timer or the second timer is in the given state, at which time, the output of the one or more logic gates is forced to a non-pulsed state.

Abstract: A command buffer for use in packetized DRAM includes a four stage shift register for shifting for sequentially storing four 10-bit command words. The shift register combines the four 10-bit command words into a single 40-bit command word and transfer the 40-bit command word to a storage register for processing by the DRAM. The shift register may then continue to receive and store subsequent 10-bit command words. The command buffer also includes circuitry for determining whether a command packet is intended for the memory device containing the command buffer or whether it is intended for another memory device. Specifically, a portion of the 40-bit command word from the storage register is compared to identifying data stored in an identifying latch. In the event of a match, a chip select signal is generated to cause the memory device to perform the function corresponding to other portions of the 40-bit command word.

Abstract: A shift register includes a plurality of shift register stages having inputs and outputs coupled to form a chain. Each stage includes enable and disable control inputs, with an output of a selected one of the stages coupled to the enable input of a stage a selected number of stages ahead in the chain and to the disable input of a stage a selected number of stages behind in the chain.

Abstract: A circuit for providing a function of a plurality of consecutive bits in a shift register is provided. The circuit includes a 2-input logic gate having a first input terminal connected to receive a bit being shifted into the shift register, and a second input terminal coupled to receive a bit being shifted out of the shift register. The circuit further includes a sequential logic device having an input terminal coupled to an output terminal of the 2-input logic gate, an output terminal that provides the function, and a control terminal coupled to receive a control signal for resetting the sequential logic device. In one embodiment, the 2-input logic gate is an exclusive OR gate, and the sequential logic device is a toggle flip-flop. In this embodiment, the function is a logical exclusive OR of the consecutive bits in the shift register. The function is implemented by initializing an output signal of the sequential logic device when the consecutive bits of the shift register have a predetermined value.

Abstract: A balanced dual-edge triggered bit shifting circuit includes a clock circuit to generate low skew, or edge-aligned, complementary clock signals, and a shift register that shifts a data bit in response to the complementary clock signals. The clock circuit is formed from two clock generators, each of which generates the edge-aligned complementary clock signals by alternatively coupling the input terminals of two buffer circuits to a voltage supply terminal and a ground terminal. Transfer gates coordinate the coupling of the input terminals of the buffer circuits so that the resulting output clock signals generated by each clock generator have clock transitions that are substantially simultaneous. The shift register is formed from at least one shift register stage that receives the edge-aligned complementary clock signals. The shift register stage includes two latching stages, each latching stage having an inverter with an output coupled to a latch circuit.

Abstract: A pseudorandom sequence generator including a first feedback shift register having at least one input and at least one output and a first controller having an output in communication with the at least one input of the first feedback shift register; the first feedback shift register operating at a first speed S1 and the first controller operating at a second speed S2. In one embodiment the first speed S1 of the first feedback shift register is an integer multiple of the second speed S2 of the first controller. In another embodiment the first feedback shift register includes a shift register having an input, an output, and at least one tap; and a feedback function generator having a first input in communication with the at least one tap of the shift register, a second input in communication with the output of the first controller, and an output in communication with the input of the shift register; the feedback function generator includes at least one feedback function.

Abstract: A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

Abstract: In order to implement the Digital Video Broadcasting descrambling algorithm in the context of MPEG compressed data streams containing interleaved sections of scrambled and unscrambled data, at a data rate of 60 MBits/sec with a clock of 2.7 MHz, a stream cipher has an input to receive scrambled video data, and an output coupled to a block cipher for providing descrambled data, the stream cipher comprises shift register means for holding input data coupled to a first mapping logic mechanism comprising at least a first logic means and a second logic means coupled in sequence and arranged to carry out similar logical steps, and the block cipher means comprising shift register means for holding the output of the stream cipher means and a second logic mapping mechanism, comprising at least a first logic means, a second logic means, a third logic means and a fourth logic means coupled in sequence being arranged to carry out similar logical steps.

Abstract: A programmable n stage shift counter divider circuit includes a plurality of n flip-flops arranged in cascade from a first stage to an nth stage. The data inputs of each of the flip flops are coupled with the output of the next preceding stage through corresponding OR gates. A source of preload signals is coupled with the second inputs of the OR gates; and a combined trap detector and terminal count detector has inputs coupled with the outputs of the last n-1 stages of the shift counter circuit and an output coupled with the source of pre-load signals to operate it.

Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a bit-operator configured to selectively transpose the bit pattern; a shifter configured to shift the bit pattern following the transposition of the bit pattern; and the bit-operator being configured to transpose the bit pattern following the shift of the bit pattern. The present invention additionally provides a barrel shifter and a method for manipulating a bit pattern.

Abstract: A new class of shift registers that shift the contents of a 2.sup.n bit length register up to 2.sup.n -1 positions in n cycles. Shift registers according to the present invention can be constructed to shift left, shift right, or to shift either left or right. A general implementation of this class of shift registers comprises the following hardware: 2.sup.n D flip-flops or D latches for the data register positions of the shift register; logic for each of the 2.sup.

Abstract: A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or ground (i.e., shorted to a logical 1 or logical 0) and the precise location of the short. Circuitry in the flip-flops (or other sequential elements) forming the scan chain allows the scan output of each flip-flop to be set or reset by switching a scan enable signal between logic states. If there is a fault in the scan chain where a node is stuck at a logical 1, then resetting the scan outputs of the flip-flops to 0 and clocking the flip-flops will result in a logical 1 being output from the last flip-flop after a number of clock pulses. The number of clock pulses indicates the position of the flip-flop in the scan chain which is associated with the fault. A similar technique detects a stuck-at-0 fault by setting the flip-flops to 1.

Abstract: A register using a single pin to provide two or more control signals (e.g., clock and data signals). The present invention decodes a three state input waveform to generate a clock/write signal and uses a three state clock waveform to generate a clock/read data signal. The present invention generally comprises a three-level receiver, a latch and an output driver to form a one-pin bidirectional interface used with a shift register. To write, the interface converts a three-level input signal into separate clock and data signals which drive the shift register. To read, the interface converts a bi-level input signal into a three-level output signal representing the output of the shift register. As a result, the present invention allows the programming of a device such as an erasable programmable read only memory (EPROM) in a clock chip while utilizing the fewest number of pins.

Abstract: A large number of frequent events may be accurately counted by employing a shift register. The values of several bit positions within the shift register are logically combined to generate an input to the shift register. The input is shifted in to alter the register contents whenever an event to be counted occurs. The bit positions for generating the input are selected to produce the longest sequence of nonrepeating patterns possible. The event counter may be implemented in a small area, allowing a large number of event counters to be implemented in an array like structure within a single device and to operate as extremely high frequencies.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying application of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: A parallel architecture for implementing a digital sequence generator is provided, which contains taps connected to selected fixed memory cells and the taps of the logic circuitry are switched among the cells. The architecture disclosed and claimed herein generates an identical sequence while consuming substantially less power than a linear feedback shift register implementation. The parallel architecture may also be used to implement a parallel shift register in other applications.

Abstract: A data shift control circuit for a shift register in response to a logic operation command code is disclosed. The shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion. The circuit includes a first decoder for decoding the first portion to transmit a move signal; a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action; and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the move register to execute a second action.

Abstract: Apparatus and method to logically process signals representative of multiple bits of multiple-bit numbers include successively delaying applications of the bit-representative signals to logical processing stages from associated input registers by a delay interval between input registers that is substantially equal to the processing delay interval per bit-level processing stage. In this way, successively more significant bits of each of plural numbers being logically processed are validly available for processing at each bit-level logic stage after a delay that is substantially equal to the processing delay interval of a preceding bit-level logic stage.

Abstract: As multiphase clocks to be supplied to a first gate driver that drives odd-numbered scanning lines in a liquid crystal display region and a second gate driver that drives even-numbered scanning lines, clocks, which are effective within an effective period of the image signal just before an image signal starts to be supplied to display elements for each scanning line of the liquid crystal display region, is generated and the first and second gate drivers drive switching elements in the effective period of the clock.