Abstract: An exemplary shift register includes a control circuit and an output transistor. The control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and includes a first control transistor and a second control transistor. The output transistor is electrically coupled to the first control transistor and includes a gate driving signal output terminal and a second clock pulse signal input terminal. Moreover, the first control transistor, the second control transistor and the output transistor all are negative threshold voltage transistors.

Abstract: A shift register and a display driver thereof are provided. The display driver submitted by the present invention can be directly disposed on a glass substrate of a liquid crystal display (LCD) panel to replace a scan driver commonly used in prior art, so that the cost of the liquid crystal display can be reduced. In addition, the stress taken by the output stage transistor of each shift register stage within the display driver submitted by the present invention can be reduced. Thus, each shift register stage has the highest reliability, and may consequently avoid the erroneous actions when each shift register stage is operated for a long time.

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit and a pull-up unit. The pull-up unit is utilized for pulling up a gate signal according to a system clock and a driving control voltage. The input unit is employed for outputting the driving control voltage according to a control signal and an input signal. The input unit includes a switch device having a first transistor and a second transistor. The first transistor has a first end for receiving the input signal, a gate end for receiving the control signal, and a second end. The second transistor has a first end electrically connected to the second end of the first transistor, a gate end electrically connected to the first end of the first transistor, and a second end for outputting the driving control voltage.

Abstract: A shift register comprises many stages, and each of stages comprises a first, a second and a third level control unit and a first and a second control unit is provided. The first and the second level control unit respectively provides a first clock signal and a voltage to an output terminal. The first driving unit and the level control unit are coupled to a first node. The first driving unit turns on and turns off the first level control unit in response to an input signal, a second control signal and a first control signal of the next stage. The second driving unit turns on and turns off the second level control unit in response to the first control signal. The third level control unit provides a first voltage to the output terminal in response to the second control signal and the first control signal.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. The Nth shift register stage of the shift register stages includes an input unit, a pull-up unit and a pull-down unit. The input unit is put in use for outputting an Nth driving control voltage according to an (N?1)th gate signal and an (N?2)th driving control voltage which are generated respectively by the (N?1) th shift register stage and the (N?2) th shift register stage of the shift register stages. The pull-up unit pulls up an Nth gate signal according to the Nth driving control voltage and a system clock. The pull-down unit pulls down the Nth gate signal and the Nth driving control voltage according to an (N+2)th gate signal generated by the (N+2)th shift register stage of the shift register stages.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: An embodiment of the present invention discloses a shift register unit and a gate drive device for a liquid crystal display. The shift register unit, on the basis of a structure of 12 transistors and 1 capacitor in the prior art, enables both the drain of the seventh thin film transistor and the gate and the drain of the ninth thin film transistor being connected to the second clock signal input terminal, such that a leakage current would not be generated among the seventh thin film transistor, the eighth thin film transistor, the ninth thin film transistor and the tenth thin film transistor when a high level signal is outputted from the shift register unit, thus power consumption of the shift register unit may be reduced.

Abstract: An exemplary shift register includes a control circuit and an output transistor. The control circuit has a start pulse signal input terminal, a first clock pulse signal input terminal and a power supply voltage input terminal and includes a first control transistor and a second control transistor. The output transistor is electrically coupled to the first control transistor and includes a gate driving signal output terminal and a second clock pulse signal input terminal. Moreover, the first control transistor, the second control transistor and the output transistor all are negative threshold voltage transistors.

Abstract: A shift register comprising a plurality of shift register stages {SN}. Each shift register stage comprises a first input, a second input, a third input for receiving a first clock signal, a fourth input for receiving a second clock signal, an output for providing an output signal OUT(N), therefrom. The stages is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N?1)-th shift register stage SN?1 for receiving an output signal OUT(N?1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage SN+1 for providing the output signal OUT(N+1) thereto.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit, a pull-up unit, a pull-down unit, a control unit and an auxiliary pull-down unit. The input unit is put in use for outputting a driving control voltage according to at least one first input signal. The pull-up unit pulls up a corresponding gate signal according to the driving control voltage and a system clock. The pull-down unit pulls down the corresponding gate signal to a first power voltage according to a control signal. The control unit is utilized for generating the control signal according to the corresponding gate signal. The auxiliary pull-down unit pulls down the driving control voltage to a second power voltage according to a second input signal.

Abstract: A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.

Abstract: A shift register unit. gate drive circuit. and display apparatus. The shift register unit comprises: input module for inputting first and second clock signals. frame start signal. high and low voltage signals, the first clock signal is identical with phase-inverted signal of the second clock signal within one frame; a processing module comprising multiple TFTs, for generating gate drive signal according to the first and second clock signals and frame start signal, controlling voltage of first node formed by TFTs lower than the low level of power supply signal during evaluation period of shift register unit, and resetting second node formed by TFTs to cut off transient DC path formed by input terminals of the high and low voltage signals, and at least one TFT in time; an output module for sending gate drive signal generated by the processing module.

Abstract: A low power consumption shift register which inputs a CK signal with a low voltage with almost no effect of variation in characteristics of transistors. In the invention, an input portion of an inverter is set at a threshold voltage thereof and a CK signal is inputted to the input portion of the inverter through a capacitor means. In this mariner, the CK signal is amplified, which is sent to the shift register. That is, by obtaining the threshold potential of the inverter, the shift register which operates with almost no effect of variation in characteristics of transistors can be provided. A level shifter of the CK signal is generated from an output pulse of the shift register, therefore, the low power consumption shift register having the level shifter which flows a shoot-through current for a short period can be provided.

Abstract: A shift register comprising a plurality of shift register stages {SN}. Each shift register stage comprises a first input, a second input, a third input for receiving a first clock signal, a fourth input for receiving a second clock signal, an output for providing an output signal OUT(N), therefrom. The stages is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N?1)-th shift register stage SN?1 for receiving an output signal OUT(N?1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage SN+1 for providing the output signal OUT(N+1) thereto.

Abstract: A shift register includes multiple cascade-connected stages. Each stage generates an output signal in response to a clock signal and a first control signal. Each stage includes a pull-up module, a pull-up driving module, a first pull-down module, a second pull-down module, and a third pull-down module. The pull-up module is used for providing the output signal based on the clock signal. The pull-up driving module turns on the pull-up module in response to a first control signal. The first pull-down module adjusts voltage level on the first node to a first supply voltage in response to a second control signal. The second pull-down module adjusts voltage level on the output end to a second supply voltage in response to the second control signal. The third pull-down module adjusts voltage level on the second node to a third supply voltage in response to a third control signal.

Abstract: A touch device includes gate lines, pixels, sense control lines and sense units. Each pixel is connected to one of the gate lines and is decided whether to receive data according to a voltage on the gate line. Each the sense unit is connected to one of the sense control lines and is decided whether to perform a touch sense operation according to a voltage on the sense control line. The touch device further includes a shift register string including cascade-connected shift registers. Each shift register has first and second output terminals. The first output terminal provides an output to one of the gate lines according to a first clock signal to control the voltage on the gate line. The second output terminal provides an output to one of the sense control lines according to a second clock signal to control the voltage on the detection control line.

Abstract: The present invention provides a shift register unit, a gate driving device and a liquid crystal display, wherein the shift register unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor and a fourth thin film transistor, and further includes a pull-down unit and a driving unit. Since the shift register unit includes the pull-down unit and the driving unit, it is possible to assure that the output gate driving signal keeps at a low level stably when the shift register unit needs to output a low level, and the pull-down unit operates under the driving of an alternating current signal, which can prevent the threshold voltage of the thin film transistor of the pull-down unit from offsetting largely.

Abstract: A display device is implemented that can suppress degradation in display quality caused by crosstalk, without causing an increase in frame size or an increase in power consumption. In an embodiment, each bistable circuit includes an output terminal that outputs a state signal; a thin film transistor having a drain terminal to which a high-level potential is provided, and a source terminal to which the output terminal is connected; a thin film transistor having a source tee urinal connected to a region netA connected to a gate terminal of the thin film transistor, and a gate terminal to which a clock is provided; a thin film transistor for increasing the potential of a region netZ connected to a drain terminal of the thin film transistor; and thin film transistors for decreasing the potentials of the netA, the netZ, and the output terminal, respectively.

Abstract: A shift register includes a plurality of serially-coupled shift register units each including a first node, a second node, an input circuit, a pull-up circuit and a pull-down circuit. The shift register unit receives an input voltage at an input end, and provides an output voltage at an output end. The input circuit controls the signal transmission path between a first clock signal and the first node according to the input voltage. The pull-up circuit controls the signal transmission path between a second clock signal and the output end according to the voltage level of the first node. The voltage level of the first node or the output end is maintained according to the voltage level of the second node. The voltage level of the second node is maintained according to the first clock signal, the second clock signal and the voltage level of the first node.

Abstract: A shift register circuit includes a plurality of shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes an input unit, a first pull-up unit, a second pull-up unit, a pull-down unit and an auxiliary pull-down unit. The input unit inputs a first gate signal generated by a preceding shift register stage to become a driving control voltage. The first pull-up unit pulls up a second gate signal according to the driving control voltage and a first clock signal. The second pull-up unit pulls up a third gate signal according to the driving control voltage and a second clock signal. The auxiliary pull-down unit is employed to pull down the driving control voltage according to a fourth gate signal generated by a subsequent shift register stage. The pull-down unit pulls down the first and second gate signals according to the driving control voltage.

Abstract: The present invention relates to a shift register and a gate driver therefor.

Abstract: A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.

Abstract: A shift register comprising a plurality of shift register stages {SN}, N=1, 2, . . . , M, M being a nonzero positive integer. Each of the plurality of shift register stages, SN, comprises a first input, a second input, a third input for receiving a first clock signal CK, a fourth input for receiving a second clock signal XCK, an output for providing an output signal OUT(N), therefrom. The plurality of stages {SN} is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N?1)-th shift register stage SN?1 for receiving an output signal OUT(N?1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage, SN+1 for providing the output signal OUT(N+1) thereto.

Abstract: Disclosed are a shift register and a display device which can suppress noise of output of each stage without causing an increase in circuit scale. Each stage (Xi) of the shift register includes a first output transistor (M5), a second output transistor (M7), a first capacitor (C1), a second capacitor (C2), an input gate (M1), a first switching element (M2), a second switching element (M3), a third switching element (M4), a fourth switching element (M6), and a fifth switching element (M8).

Abstract: An exemplary shift register includes a control circuit and an output circuit. The control circuit is electrically coupled to receive a start pulse signal, a first clock pulse signal and a power supply voltage and for generating an enable signal according to the start pulse signal and the first clock pulse signal. A logic low level of the first clock pulse signal is lower than a level of the power supply voltage. The output circuit is subjected to the control of the enable signal and for generating a gate driving signal according to a second clock pulse signal. The second clock pulse signal and the first clock pulse signal are phase-inverted with respect to each other, and a logic low level of the second clock pulse signal is higher than the level of the power supply voltage.

Abstract: Disclosed is a dual shift register that includes a first shift register configured to include a plurality of stages which sequentially output scan pulses using at least two clock signals with sequential and circular phases, and a second shift register configured to a plurality of stages which form pair with the respective stages of the first shift register and sequentially output the scan pulses using at least two clock signals. Each stage includes: a scan direction controller configured to respond to the scan pulses from previous and next stages and to selectively output forward and reverse direction voltages with opposite electric potentials to each other; and an output portion configured to respond to the output signal of the scan direction controller, to generate two sequential scan pulses using two of the at least two clock signals, and to distribute the sequential scan pulses to the previous and next stages.

Abstract: An exemplary shift register includes a plurality of shift register units, each of which includes an output circuit, an input circuit, and a logic circuit. The output circuit includes a clock transistor, a voltage stabilizing transistor, and an input circuit for receiving signals output by a previous shift register unit. The logic circuit receives signals output by the input circuit. When the input circuit outputs signals to switch on the clock transistor, the logic circuit outputs a low level voltage signal to shut off the voltage stabilizing transistor. Thus, the output circuit outputs signals via the clock circuit. On the other hand, when the input circuit outputs signals to shut off the clock transistor, the logic circuit outputs a high level voltage signal to turn on the voltage stabilizing transistor, so as to maintain the output circuit to output low level voltage signal.

Abstract: A digital logic circuit includes a plurality of transistors of a same conduction type. In at least one embodiment, a first transistor has a source, gate and drain connected to a first circuit node, a second circuit node and a first power supply line, respectively. A second transistor has a source, gate and drain connected to the second node, the first node and the first supply line, respectively. A third transistor has a drain connected to the first node. A fourth transistor has a gate and drain connected to a third circuit node and the second circuit node, respectively. A fifth transistor has a gate and drain connected to the first and third nodes, respectively. Such a circuit may be used, for example, as a latch in a shift register of an active matrix addressing arrangement.

Abstract: A shift register comprises stages connected to each other, in which each stage generates an output signal in response to any one of clock signals and an output from each of two different stages. Each clock signal has a duty ratio of less than 50% and a different phase from each of the other clock signals. A display device includes pixels, signal lines, and first and second shift registers each having stages connected to each other and generating output signals to signal lines. Each stage includes a set terminal, a reset terminal, a clock terminal, and first and second output terminals.

Abstract: A shift register circuit with waveform-shaping function includes plural shift register stages. Each shift register stage includes a first input unit, a pull-up unit, a pull-down circuit, a second input unit, a control unit and a waveform-shaping unit. The first input unit is utilized for outputting a first driving control voltage in response to a first gate signal. The pull-up unit pulls up a second gate signal in response to the first driving control voltage. The pull-down circuit is employed to pull down the first driving control voltage and the second gate signal. The second input unit is utilized for outputting a second driving control voltage in response to the first gate signal. The control unit provides a control signal in response to the second driving control voltage and an auxiliary signal. The waveform-shaping unit performs a waveform-shaping operation on the second gate signal in response to the control signal.

Abstract: A shift register includes a control circuit, a pull-up circuit and a pull-down circuit. The control circuit generates a control signal according to a start pulse signal during being enabled. The pull-up circuit produces a gate pulse signal according to a clock signal during being enabled by the control signal. The pull-up circuit includes a dual-gate transistor. A first gate of the dual-gate transistor is electrically coupled to the control signal, a second gate of the dual-gate transistor is electrically coupled to a predetermined voltage, the source/drain of the dual-gate transistor serves as an output terminal for the gate pulse signal, and the drain/source of the dual-gate transistor is electrically coupled to the clock signal. The pull-down circuit pulls a potential at the first gate and another potential at the output terminal down to a power supply potential during the pull-up circuit is disabled.

Abstract: A gate driving circuit includes cascaded stages, each including a pull-up part, a carry part, a pull-up driving part, a holding part and an inverter. The pull-up part pulls up a gate voltage to an input clock. The carry part pulls up a carry voltage to the input clock. The pull-up driving part is connected to a control terminal (Q-node) common to the carry part and the pull-up part, and receives a previous carry voltage from a previous stage to turn on the pull-up part and the carry part. The holding part holds the gate voltage at an off-voltage, and the inverter controls at least one of turning on the holding part and turning off the holding part based on an inverter clock. A high level of the inverter clock in a given horizontal period (1H) temporally precedes a high level of the input clock by a predetermined time interval.

Abstract: A shift register comprising a plurality of shift register stages {SN}, N=1, 2, . . . , M, M being a nonzero positive integer. Each of the plurality of shift register stages, SN, comprises a first input, a second input, a third input for receiving a first clock signal CK, a fourth input for receiving a second clock signal XCK, an output for providing an output signal OUT(N), therefrom. The plurality of stages {SN} is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N?1)-th shift register stage SN?1 for receiving an output signal OUT(N?1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage, SN+1 for providing the output signal OUT(N+1) thereto.

Abstract: A shift register of an LCD device includes a plurality of shift register units coupled in series. Each shift register unit includes an input circuit and a pull-down circuit having symmetric structures which enable the LCD device to function in a forward-scan mode and a reverse-scan mode.

Abstract: The present invention relates to a shift register and GOA architecture of the same in a display panel comprising a substrate and a plurality of pixels spatially formed on the substrate defining a number of pixel rows, each pixel row having a height of H. The shift register has the plurality of shift register stages disposed spatially and sequentially on the substrate in such a way that the layout of each shift register stage has a height of (j*H), j being an integer greater than one. Each shift register stages is configured to generate j scanning signals for driving j neighboring pixel rows, respectively.

Abstract: A shift register includes a plurality of electrically connected shift units. Each shift unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit outputs a first signal to an output node according to the first signal and a voltage of a driving node. The pull-up driving drives the pull-up circuit according to an output voltage of the previous shift unit. The pull-down driving circuit outputs a low level voltage to the driving node and the output node according to the first signal and a second signal. The pull-down circuit resets the pull-up driving circuit according to the voltage of the output node and outputs the low level voltage to the output node and the driving node according to a third signal and a fourth signal.

Abstract: A shift register circuit includes a plurality of shift register stages for providing plural gate signals to plural gate lines. Each shift register stage includes an input unit, a first pull-up unit, a second pull-up unit, a pull-down unit and an auxiliary pull-down unit. The input unit inputs a first gate signal generated by a preceding shift register stage to become a driving control voltage. The first pull-up unit pulls up a second gate signal according to the driving control voltage and a first clock signal. The second pull-up unit pulls up a third gate signal according to the driving control voltage and a second clock signal. The auxiliary pull-down unit is employed to pull down the driving control voltage according to a fourth gate signal generated by a subsequent shift register stage. The pull-down unit pulls down the first and second gate signals according to the driving control voltage.

Abstract: The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T4, T5, T6 and T7 electrically coupled to each other. The release circuit is adapted for causing the transistor T5 to be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.

Abstract: An exemplary shift register circuit includes a shift register, a first switching circuit and a second switching circuit. The shift register has a start pulse signal input terminal and a start pulse signal output terminal. The first switching circuit includes a first input switch unit and a second output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. The second switching circuit includes a second input switch unit and a first output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. Moreover, on-off states of the first input and first output switch units are opposite to on-off states of the second input and second output switch units. Moreover, a gate driving circuit using the above-mentioned shift register and switching circuits also is provided.

Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).

Abstract: A shift register comprising a plurality of shift register stages {SN}, N=1, 2, . . . , M, M being a nonzero positive integer. Each of the plurality of shift register stages, SN, comprises a first input, a second input, a third input for receiving a first clock signal CK, a fourth input for receiving a second clock signal XCK, an output for providing an output signal OUT(N), therefrom. The plurality of stages {SN} is electrically connected to each other in serial such that the first input of the shift register stage SN is electrically connected to the output of the (N?1)-th shift register stage SN?1 for receiving an output signal OUT(N?1) therefrom, the second input of the shift register stage SN is electrically connected to the output of the (N+1)-th shift register stage SN+1 for receiving an output signal OUT(N+1) therefrom, and the output of the shift register stage SN is electrically connected to the first input of the (N+1)-th shift register stage, SN+1 for providing the output signal OUT(N+1) thereto.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a first inverter (37) connected between the first common node and the second common node, and a second inverter (39) connected between the output terminal and the reverse output terminal.

Abstract: An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an input terminal (VIN), a first output terminal (VOUT1), a second output terminal (VOUT2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a nor gate, an inverter, and an and gate.

Abstract: The present invention relates to a shift register in which a structure of a switching device of an output buffer unit is changed for reducing power consumption. The shift register includes a plurality of stages each having a plurality of switching devices, for forwarding a scan pulse in succession, wherein the at least one of the plurality of switching device has a first area at which a gate electrode thereof overlaps with a first electrode thereof with a size different from a second area at which the gate electrode overlaps with a second electrode thereof.

Abstract: A shift register which is capable of simultaneously driving gate lines is disclosed. The shift register includes a plurality of stages for simultaneously supplying all-drive signals to gate lines for an all-drive period and sequentially supplying scan pulses to the gate lines for a scan period.

Abstract: A shift register circuit is provided that can suppress a decrease in a drive capability when a frequency of a clock signal increases. A unit shift register includes a first transistor for supplying a clock signal to an output terminal, a pull-up driving circuit for driving the first transistor, a second transistor for discharging the output terminal, and a pull-down driving circuit for driving the second transistor. In the pull-up driving circuit, the gate of a third transistor charging the gate of the first transistor is charged in accordance with activation of an output signal of preceding stage, and the potential at the gate of the third transistor is increased with a capacitive element. As a result, the third transistor operates in the non-saturated region.

Abstract: A shift register comprises a plurality of stages, {Sn}, n=1, 2, . . . , N, N being a positive integer.

Abstract: In at least one embodiment, under a non-load condition of a first supply line for a first clock signal and a second supply line for a second clock signal, a fall time of a clock pulse of the first clock signal, which is supplied to the first supply line, is longer than that of the second clock signal, which is supplied to the second supply line.