Abstract: A display panel includes a first panel region (FPR) including (n?1)-th and n-th pixel rows ((n?1)PR and nPR), and a second panel region (SPR) dividing the nPR to propagate an optical signal. The display panel includes a circuit element layer (CEL) and a display element layer (DEL). The CEL includes a signal line (SL), a pixel driving circuit (PDC), and first to third regions. The SL and the PDC are in the first region. The second region (SR) corresponds to the SPR. The SL and the PDC are not in the SR. The third region (TR) corresponds to the SPR and is along a periphery of the SR. The SL is in the TR, and includes an (n?1)-th scan line ((n?1)SL) connected to the (n?1)PR, an n-th reset line (nRL) connected to the nPR, and a first row connection line in the TR and connecting the (n?1)SL and the nRL.

Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.

Abstract: A pseudo-complementary logic network according to this embodiment includes a first logic stage including a first pull-up circuit of an N-type transistor and a first pull-down circuit and a second logic stage including a second pull-up circuit and a second pull-down circuit of an N-type transistor, wherein an output signal of the second logic stage is provided as an input of the first pull-down circuit, and the first pull-up circuit includes the second pull-down circuit.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: Disclosed is a shift register including a first input sub-circuit, configured to receive a first input signal from a first input terminal and output a blanking output control signal to a first node in a blanking period of time of a frame; a second input sub-circuit, configured to receive a second input signal from a second input terminal and output a display output control signal to the first node in a display period of time of the frame; an output sub-circuit, configured to output a composite output signal via an output terminal under control of the first node, the composite output signal including a display output signal outputted in a display period of time and a blanking output signal outputted in a blanking period of time which are independent of each other.

Abstract: Disclosed are a shift register unit and a method for driving the same, a gate drive circuit, and a display device. The pull-down control circuit in the shift register unit is capable of controlling a potential of a second pull-up node under control of the input signal provided by an input signal terminal. The pull-down circuit is capable of performing noise reduction on a first pull-up node and an output terminal under control of the second pull-up node. Since the potential of the second pull-up node is not pulled up due to the bootstrap effect, the threshold voltages of transistors in the pull-down circuit are less shifted, and the service life of the shift register unit is relatively long.

Abstract: A planar insulating spacer layer is formed over a substrate, and a vertical stack of a gate electrode, a gate dielectric layer, and a first semiconducting metal oxide layer may be formed thereabove. The first semiconducting metal oxide layer includes atoms of a first n-type dopant at a first average dopant concentration. A second semiconducting metal oxide layer is formed over the first semiconducting metal oxide layer. Portions of the second semiconducting metal oxide layer are doped with the second n-type dopant to provide a source-side n-doped region and a drain-side n-doped region that include atoms of the second n-type dopant at a second average dopant concentration that is greater than the first average dopant concentration. Various dopants may be introduced to enhance performance of the thin film transistor.

Abstract: A semiconductor device or the like with a novel structure that can change the orientation of the display is provided. A semiconductor device or the like with a novel structure, in which a degradation in transistor characteristics can be suppressed, is provided. A semiconductor device or the like with a novel structure, in which operation speed can be increased, is provided. A semiconductor device or the like with a novel structure, in which a dielectric breakdown of a transistor can be suppressed, is provided. The semiconductor device or the like has a circuit configuration capable of switching between a first operation and a second operation by changing the potentials of wirings. By switching between these two operations, the scan direction is easily changed. The semiconductor device is configured to change the scan direction.

Abstract: The present disclosure provides a display panel including: gate lines; data lines insulated from and intersecting with gate lines; pixel units; first and second clock signal lines; first and second power signal lines; gate driving units; and virtual driving units. Each gate driving unit has an output terminal electrically connected to gate lines, a first clock signal input terminal electrically connected to first clock signal line, and a second clock signal input terminal electrically connected to second clock signal line. Each virtual driving unit has an output terminal insulated from gate lines, a first clock signal input terminal insulated from first and second clock signal lines, and a second clock signal input terminal insulated from first and second clock signal lines. At least one virtual driving unit is disposed within the rounded angle region and located between two gate driving units.

Abstract: The present application discloses a scanning driving circuit and a display apparatus. The scanning driving circuit includes a scanning signal output terminal to output a scanning signal; a pull-up circuit for receiving a first clock signal and controlling the scanning signal output terminal to output a high level scanning signal; a transmission circuit for outputting a stage transmission signal of a current stage; a pull-up control circuit receiving a stage transmission signal of a previous stage and a second clock signal to charge the pull-up control signal point; a pull-down maintenance circuit receiving the second clock signal to maintain low levels of the pull-up control signal point, and the scanning signal output terminal; and a bootstrap circuit for raising the potential of the pull-up control signal point, to solve the problem that the power consumption of the scanning driving circuit increases due to the leakage of the controllable switch.

Abstract: The present application discloses a scanning driving circuit and a display apparatus. The scanning driving circuit includes a scanning signal output terminal; a pull-up circuit controlling the scanning signal output terminal to output a high level scanning signal; a transmission circuit for outputting a stage transmission signal of a current stage; a pull-up control circuit to charge the pull-up control signal point; a pull-down maintaining circuit maintains the low level of the pull-up control signal point and the scanning signal output terminal and releases the high potential of the pull-up control signal point; a bootstrap circuit raises the potential of the pull-up control signal point; a pull-down circuit controls the scanning signal output terminal to output a low level, thereby solving the problem of the large current generated when the display device is turned on and off.

Abstract: The present disclosure relates to a scanning driving circuit and a flat display device. The scanning driving circuit includes a plurality of cascaded-connected scanning driving units respectively arranged at two lateral sides of a flat display device. With respect to the same level, the scanning driving unit at both sides connect to two the same scanning lines. Each of the scanning driving units includes: an input circuit configured to charge a pull-up and a pull-down control signal points; a latch circuit configured to latch signals received from the input circuit; a reset circuit configured to reset a level of the pull-up control signal point; an output circuit configured to generate scanning driving signals; and a clock control circuit configured to selectively output the scanning driving signals to the first scanning line or the second scanning line via third clock signals or fourth clock signals.

Abstract: A shift register, a driving method of a display panel and related device. The shift register adds a selection output unit and a selection control signal terminal to the current shift register; the output terminal of the selection output unit outputs a signal that is same as the signal of the driving signal output terminal when the selection control signal terminal receives a selection control signal. Then whether there is a scan signal outputted from the selection driving output terminal is determined by the control of the selection control signal terminal and the selection output unit. Further, in using the gate-driving circuit consisting of the above shift register, selectively outputting scan signal to certain gate lines can be achieved.

Abstract: The invention provides a scanning driving circuit and a liquid crystal display apparatus. The scanning driving circuit including a latch module to receive and calculate an upper level control signal, a first and a second clock signal and a reset signal to get a first control signal, and latch and output the first control signal; a logic control module receive and calculate the first and the second control signal and the third clock signal to get a logic control signal, and output the logic control signal; an output module receive and calculate the logic control signal and the second control signal to get and output a scanning driving signal, and a scan line connected to the output module to transmit the scanning driving signal to a pixel unit and to achieve the special function of the liquid crystal display apparatus.

Abstract: The invention provides a GOA circuit and a liquid crystal display device each including multiple cascade connected GOA units. An nth-stage GOA unit is for charging an nth-stage horizontal scan line in a display area. The nth-stage GOA unit includes a pull-up control circuit, a pull-up circuit, a transfer circuit, a first pull-down control circuit, a first pull-down circuit, a second pull-down control circuit, a second pull-down circuit and a main pull-down circuit, where n is a positive integer. The invention can improve the stage-transfer efficiency of GOA circuit, improve the output quality of scan drive signal so as to increase charging ratio of LCD tubes and also can accelerate the pull-down speed of scan drive signal.

Abstract: A GOA circuit applied to a liquid crystal display is disclosed, which comprises a plurality of cascaded shift register units, an (N)th level shift register unit is controlled to charge an (N)th level scanning line accordingly. The (N)th level shift register unit includes a pull-up circuit, a pull-down circuit, a pull-down sustain circuit, a pull-up control circuit, a down transfer circuit, and an bootstrap capacitor, and a display device is also disclosed herein. By replacing scanning lines with a constant voltage VDD or two voltages to accomplish the function of down transfer, the loading of scanning lines and the risk which comes with wiring step-by-step are decreased, forward-scanning operation and backward-scanning operation are accomplished accordingly.

Abstract: A display apparatus and a method for generating gate signal thereof are provided. The display apparatus includes a timing controller and a display panel. The timing controller is used for providing a plurality of timing signals. The display panel includes a pixel array and a gate drive circuit. The pixel array has a plurality of pixels. The gate drive circuit is electrically connected to the timing controller and the pixel array and including a plurality of shift register circuits. The shift register circuit includes a first shift register and a second shift register. The first shift register is configured for generating a corresponding primary gate signal. The second shift register is configured for generating a corresponding secondary gate signal. The timing controller adjusts overlapping relations of the timing signals according to a frame rate of the display apparatus.

Abstract: The present invention relates to a liquid crystal display (LCD) device. More particularly, the present invention relates to an LCD device including a thin film transistor (TFT) compensation circuit in an LCD device which implements a driving circuit by using an oxide TFT, the LCD device capable of compensating for degraded characteristics of a TFT due to threshold voltage shift. As the compensation circuit including a dummy TFT is formed on a non-active area of the LC panel, the degree of threshold voltage shift of the DT due to a DC voltage can be sensed. Based on the sensed result, a threshold voltage of a second TFT can be compensated. This can reduce lowering of a device characteristic.

Abstract: The present disclosure relates to a field of display. Particularly, embodiments of the present invention disclose a shift register unit, a shift register, an array substrate and a display apparatus that enable the respective shift register units to be reset independently. The shift register unit includes a sampling part, an output part and a reset part, wherein the sampling part includes a first switching transistor and a second switching transistor, the output part includes a fifth switching transistor, a sixth switching transistor, a first capacitor and a second capacitor, and the reset part includes a third switching transistor and a fourth transistor.

Abstract: A semiconductor device includes first and second transistors having the same conductivity type and a circuit. One of a source and a drain of the first transistor is electrically connected to that of the second transistor. First and third potentials are supplied to the circuit through respective wirings. A second potential and a first clock signal are supplied to the others of the sources and the drains of the first and second transistors, respectively. A second clock signal is supplied to the circuit. The third potential is higher than the second potential which is higher than the first potential. A fourth potential is equal to or higher than the third potential. The first clock signal alternates the second and fourth potentials and the second clock signal alternates the first and third potentials. The circuit controls electrical connections between gates of the first and second transistors and the wirings.

Abstract: Disclosed herein is a shift register which is capable of preventing leakage of charges at a set node which occurs when the duty ratio of a scan pulse is small, so as to normally output a scan pulse. The shift register includes a plurality of stages for sequentially generating outputs thereof. Each of the stages includes a carry output unit for outputting a carry pulse to drive at least one of a downstream stage and an upstream stage, and a scan output unit for outputting a scan pulse to drive a gate line. Each of the outputs generated from the stages includes the carry pulse and the scan pulse. The carry pulse and the scan pulse are paired to correspond to each other. The paired carry pulse and scan pulse have different durations.

Abstract: Disclosed is a shift register (200, 400) comprising an input (205), an output (230) and a plurality of register cells (210) serially connected between the input and the output, each register cell being connected to a neighboring cell via a node, wherein at least some of said nodes comprise a multiplexer (220) having an output coupled to the downstream register cell and a plurality of inputs, each of said plurality of inputs being coupled to a different upstream register cell such that different length sections of the shift register can be selectively bypassed, the shift register further comprising a set of parallel IO channels (230, 410) facilitating conversion between interleaved and de-interleaved data, each of said channels being coupled to a different one of said nodes, the number of parallel IO channels being smaller than the total number of register cells in the shift register.

Abstract: A shift register includes a plurality of stages each having a pull-up transistor, a pull-down transistor and a flip-flop, the plurality of stages outputting high level output voltages sequentially for one horizontal period in response to at least one clock signal and a start signal, and an AH control circuit connected to input terminals and output terminals of the plurality of stages to control output signals of all the stages into a high level for one frame.

Abstract: A shift register includes an input terminal, an output terminal, a first clock signal terminal, a second clock signal terminal, a first level signal terminal, a second level terminal, a first capacitor and a second capacitor, and five transistors. The five transistors are controlled by first and second clock signals applied to the respective first and second signal terminals to shift a signal received from the input terminal to the output terminal with a half cycle period delay while maintaining a stable level of the shifted signal at the output terminal.

Abstract: A gated-clock shift register including a series of clocked flip-flops with preceding outputs connected to subsequent inputs as a horizontal digital shift register. Each flip-flop (or other state holding device) includes a clock buffer between the respective flip-flop's clock, and the global clock. Each clock buffer propagates the clock signal when it determines the associated flip-flop will have a state change during that clock cycle (e.g., via an XOR of the flip-flops input and output signals). In the absence of a state change, that buffer does not propagate the clock signal, essentially only clocking the relevant flip-flops. Further, the clock buffer may be implemented with only NMOS devices (or alternatively, only PMOS devices), which offers power savings over an otherwise required CMOS implementation.

Abstract: A level shifter includes: an input terminal to which an input voltage is applied; a capacitor; a first transistor provided between the input terminal and one of electrodes of the capacitor, and having a gate electrode connected to the other of the electrodes of the capacitor; a second transistor provided between the input terminal and the other electrode of the capacitor; a signal generating unit which generates a signal for switching the second transistor between conduction and non-conduction and supply the signal to the gate electrode of the second transistor, in a period when the input voltage is provided to the input terminal; and an output terminal for outputting a voltage at the other electrode of the capacitor which is level-shifted by a change in the second transistor to a non-conducting state in the period as an output voltage.

Abstract: A display panel drive device includes: a ring counter circuit that includes a first ring counter having a plurality of flipflops connected in cascade, configured to operate in synchronization with a first clock signal with a first-stage one of the plurality of flipflops being set by an initial signal, and outputs signals using outputs of the plurality of flipflops; a shift register having a plurality of flipflops connected in cascade, configured to operate in synchronization with a second clock signal lower in frequency than the first clock signal with a first-stage one of the plurality of flipflops being set by the initial signal; and an output section configured to perform a logical operation between one of outputs of the ring counter circuit and one of outputs of the shift register, to generate a scanning line drive signal for a display panel.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a driving unit, an input unit, a driving adjustment unit and a pull-down unit. The driving unit is utilized for outputting a gate signal according to a system clock and a driving control voltage. The input unit is put in use for outputting the driving control voltage according to an input control signal and a first input signal. The driving adjustment unit is employed for adjusting the driving control voltage according to a second input signal and a third input signal. The pull-down unit is used for pulling down the gate signal and the driving control voltage according to a fourth input signal.

Abstract: A low density One-Time Programmable (OTP) memory is disclosed to achieve low gate count and low overhead in the peripheral circuits to save the cost. A maximum-length Linear Feedback Shift Register (LFSR) can be used to generate 2n?1 address spaces from an n-bit address. The registers used in the address generator can have two latches. Each latch has two cross-coupled inverters with two outputs coupled to the drains of two MOS input devices, respectively. The inputs of the latch are coupled to the gates of the MOS input devices, respectively. The sources of the MOS input devices are coupled to the drains of at least one MOS device(s), whose gate(s) are coupled to a clock signal and whose source(s) are coupled to a supply voltage. The two latches can be constructed in serial with the outputs of the first latch coupled to the inputs of the second latch.

Abstract: A level shifter includes: an input terminal to which an input voltage is applied; a capacitor; a first transistor provided between the input terminal and one of electrodes of the capacitor, and having a gate electrode connected to the other of the electrodes of the capacitor; a second transistor provided between the input terminal and the other electrode of the capacitor; a signal generating unit which generates a signal for switching the second transistor between conduction and non-conduction and supply the signal to the gate electrode of the second transistor, in a period when the input voltage is provided to the input terminal; and an output terminal for outputting a voltage at the other electrode of the capacitor which is level-shifted by a change in the second transistor to a non-conducting state in the period as an output voltage.

Abstract: A method of exposing a substrate to a pattern using an exposure apparatus. The method includes performing an update of a parameter, necessary for processing in the exposure apparatus, through measurement, in which the measurement is performed for each update of the parameter, setting a validity period for the updated parameter, in which the validity period represents a period in which the updated parameter is valid for the processing, predicting a completion time for a next exposure processing segment to be performed by the exposure apparatus, determining whether the predicted completion time is after expiration of the validity period, in which the setting of the validity period is performed after the performing of the update and before the determining step, and causing the update of the parameter to be performed if it is determined in the determining step that the predicted completion time is after the expiration of the validity period.

Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.

Abstract: A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.

Abstract: A high-reliability gate driving circuit is disclosed for providing a plurality of gate signals to plural gate lines respectively. The gate driving circuit includes a plurality of shift register stages. Each shift register stage includes a pull-up unit, an energy-store unit, a buffer unit, a discharging unit, a first pull-down unit, a second pull-down unit and a control unit. The pull-up unit pulls up a gate signal according to a driving control voltage and a first clock. The buffer unit receives an input signal. The energy-store unit provides the driving control voltage through performing a charging process based on the input signal. The first pull-down unit pulls down the gate signal according to a control signal. The second pull-down unit pulls down the gate signal according to a second clock having a phase opposite to the first clock. The control unit generates the control signal based on the gate signal.

Abstract: A shift register includes a signal input unit for receiving and providing an input signal, a signal output unit for controlling whether outputting a clock signal according to the input signal provided by the signal input unit, and a plurality of stable modules. Each of the stable modules is electrically coupled to an output terminal of the signal input unit, an output terminal of the signal output unit, and a default potential. Each of the stable modules receives a corresponding operation signal and is enabled in a duty of the corresponding operation signal, such that both the output terminal of the signal input unit and the output terminal of the signal output unit are electrically coupled to the default potential when the input signal is disabled. Before one of the stable modules is disabled, another of the stable modules has already been enabled.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. The Nth shift register stage of the shift register stages includes an input unit, a pull-up unit and a pull-down unit. The input unit is put in use for outputting an Nth driving control voltage according to an (N?1)th gate signal and an (N?2)th driving control voltage which are generated respectively by the (N?1) th shift register stage and the (N?2) th shift register stage of the shift register stages. The pull-up unit pulls up an Nth gate signal according to the Nth driving control voltage and a system clock. The pull-down unit pulls down the Nth gate signal and the Nth driving control voltage according to an (N+2)th gate signal generated by the (N+2)th shift register stage of the shift register stages.

Abstract: An electronic system including a shift register is disclosed. The shift register includes a first transistor, a first trigger circuit, a second transistor, and a second trigger circuit. The first transistor receives a first input signal. The first trigger circuit is serially connected to the first transistor between a first level and a second level and is connected with the first transistor in a first node. The second transistor receives a second input signal inverted to the first input signal. The second trigger circuit receives the level of the first node, is serially connected to the second transistor between a third level and the second level, and is connected with the second transistor in a second node.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes an input unit, a pull-up unit, a pull-down unit, a control unit and an auxiliary pull-down unit. The input unit is put in use for outputting a driving control voltage according to at least one first input signal. The pull-up unit pulls up a corresponding gate signal according to the driving control voltage and a system clock. The pull-down unit pulls down the corresponding gate signal to a first power voltage according to a control signal. The control unit is utilized for generating the control signal according to the corresponding gate signal. The auxiliary pull-down unit pulls down the driving control voltage to a second power voltage according to a second input signal.

Abstract: A gate driving circuit has a first stage which includes: a pull-up driving unit which receives a first carry signal from a second stage and outputs a control signal having first, second, third and fourth voltages to a first node during a preliminary period, a gate active period, a first gate inactive period and a second gate inactive period, respectively; a pull-up unit which receives the control signal and outputs a gate-on signal to a second node during the gate active period; a carry output unit which receives the control signal and outputs a second carry signal to a third stage during the gate active period; and a pull-down unit which receives a gate-off signal and the second carry signal from the second stage and outputs the control signal having the fourth voltage level to the first node during the second gate inactive period.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A display device is implemented that does not cause abnormal operation even if a shift in threshold voltage occurs in a transistor composing a shift register. Each bistable circuit includes an output terminal that outputs a state signal; a thin film transistor having a drain terminal to which a clock signal is provided, and having a source terminal connected to the output terminal; a thin film transistor for charging a region netA connected to a gate terminal of the thin film transistor; a thin film transistor having a drain terminal connected to the netA; a thin film transistor having a drain terminal connected to the output terminal; and a second node potential control portion that detects a higher one of the threshold voltages of the thin film transistors and sets, based on the detected threshold voltage, the potential of a region netB connected to gate terminals of the thin film transistors to a relatively low-level potential and a relatively high-level potential.

Abstract: An exemplary shift register circuit includes a shift register, a first switching circuit and a second switching circuit. The shift register has a start pulse signal input terminal and a start pulse signal output terminal. The first switching circuit includes a first input switch unit and a second output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. The second switching circuit includes a second input switch unit and a first output switch unit respectively electrically coupled to the start pulse signal input terminal and the start pulse signal output terminal. Moreover, on-off states of the first input and first output switch units are opposite to on-off states of the second input and second output switch units. Moreover, a gate driving circuit using the above-mentioned shift register and switching circuits also is provided.

Abstract: A shift register includes a sampling circuit to sample an input signal in response to a start pulse and two clock signals having different duty ratios from each other, a holding circuit to hold the input signal in response to an output signal of the sampling circuit and the two clock signals, an inverter to invert the output signal of the sampling circuit or the holding circuit, and a NAND gate to receive the output signal of the sampling circuit or the holding circuit and the output signal of the inverter and perform a logical operation on the received output signals to output an output signal. The first clock signal has a duty ratio smaller than the second clock signal. The sampling circuit and the holding circuit have a three-stack structure in which three transistors are coupled with one another in series.

Abstract: A shift register circuit includes a first transistor which supplies a clock signal to an output terminal, and an inverter which drives a second transistor for discharging a gate of the first transistor. An input node of the inverter is separated from the gate of the first transistor, and the gates of the first and second transistors are charged and discharged by separate circuits, respectively.

Abstract: The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.

Abstract: Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period.

Abstract: A shift register includes a first flip-flop group composed of a plurality of cascaded first flip-flops, each first flip-flop having a first master latch and a first slave latch and having first and second transmission paths for transmitting a master clock and a slave clock, a second flip-flop group composed of a plurality of cascaded second flip-flops, each second flip-flop having a second master latch and a second slave latch which are each composed of a transistor with a relatively small transistor size and having a third transmission path connected to the first transmission path and a fourth transmission path connected to the second transmission path, and a transfer portion configured to transfer pieces of data held in the second flip-flops to one of the first master latches and the first slave latches of the first flip-flops.

Abstract: A shift register circuit includes plural shift register stages for providing plural gate signals. Each shift register stage includes a pull-up unit, a pull-up control unit, an input unit, a first pull-down unit, a second pull-down unit, and a pull-down control unit. The pull-up control unit generates a first control signal according to a driving control voltage and a first clock. The pull-up unit pulls up a corresponding gate signal according to the first control signal. The input unit is utilized for inputting the gate signal of a preceding shift register stage to become the driving control voltage according to a second clock having a phase opposite to the first clock. The pull-down control unit generates a second control signal according to the driving control voltage. The first and second pull-down units pull down the corresponding gate signal and the first control signal respectively according to the second control signal.

Abstract: A shift register includes individually connected shift register units. Each shift register unit includes a switching unit, a pre-charging unit, a pulse signal output unit, a low level voltage signal control unit, a first clock pulse signal input, a second clock pulse signal input, and an output. The first and the second clock pulse signal inputs respectively receive a first clock signal and a second clock signal, the first clock signal and the second clock signal having reverse clock pulses during each clock cycle. The switching unit receives at least one external starting signal and a high level signal, when the at least one external starting signal is high level, the switching unit is turned on and outputs the high level signal to the pre-charging unit. When the second clock signal is high level, the pre-charging unit receives the high level signal and charges, and when the first clock signal is high level, the pre-charging unit discharges.

Abstract: The invention provides a circuit that can observe data within shift registers without altering the data. The circuit includes selectors connected to the inputs and outputs of the shift registers. The selectors selectively connect the input with the output of a selected shift register to form a wiring loop for the selected shift register. A control device connected to the wiring loop uses the wiring loop to cause the data to be continually transferred from the output of the selected shift register to the input of the selected shift register and back through the selected shift register in a circular manner. The control device includes a counter used for determining the length of a selected shift register and a set of registers to store, for future use when rotating data in the shift registers, the length of each shift register. The control device also includes a data output accessible from outside the circuit.