Abstract: Techniques for routing and shielding signal lines to improve isolation between the signal lines are disclosed. In an exemplary design, an apparatus includes first, second, and third signal lines and a switch. The first, second, and third signal lines are configurable to carry first, second, and third signals, respectively. The switch is coupled between the second signal line and AC ground and is closed when the second signal line is not carrying the second signal. The second signal line isolates the first and third signal lines when the switch is closed. Adjacent signal lines are not active at the same time. A signal line may include positive and negative signal lines, which may have at least one cross over in order to cancel coupling between the positive and negative signal lines.

Abstract: A high-frequency switching assembly having a first switching state and a second switching state includes a transmitter and a switch assembly. The transmitter includes a primary side and a secondary side having a first secondary side terminal and a second secondary side terminal and is configured to transmit an HF input signal applied to its primary side to its secondary side by means of inductive coupling. The switch assembly is configured to apply, in one state, a first reference potential to the first secondary side terminal. Further, the switch assembly is implemented to apply, in another state, a second reference potential to the second secondary side terminal.

Abstract: An embodiment of a method and apparatus for determining a change in network-generated crosstalk levels caused by a multi-line phone includes determining a first crosstalk level between a first line pair and a second line pair of a multi-line phone caused by the multi-line phone, and determining a second crosstalk level between each of the first line pair and the second line pair of the multi-line phone. The second crosstalk level is determined when the first line pair and the second line pair are coupled to a first predetermined length of network line pair cable. The method further includes determining a change of network generated crosstalk levels caused by the multi-line phone by subtracting the first crosstalk level from the second crosstalk level.

Abstract: A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.

Abstract: A system and method for managing, switching, and reconfiguring physical connections of telecommunications services that provides improved cost and timeliness.

Abstract: Restoration of an inoperative network element (12) such as a digital cross-connect system is accomplished by receiving updates from each element as they occur in a local controller network (18). The local controller network forwards the updates to a DCS-Operations support system (22) that generates a restoration map for each element in its native language, and thereafter updates each map upon receipt of each update. In response to a user command, the DCS-operation system directs (transmits) the update map either to directly the inoperative element or to an intermediate element to achieve restoration.

Abstract: An automatic main distributing frame, which can easily maintain the size accuracy required to insert into a through hole of the conductive pin is provided. The main distributing frame includes a frame body, plural matrix switch boards accommodated in the frame body, each having matrix switch sections and input/output connectors on a rear section, a back wire board provided on a rear section of the frame body, having connectors connected to the input/output connectors on each rear section of the plural matrix switch boards, and plural robots, each positioned between a pair of two matrix switch board sections of the plural matrix switch boards, each having a hand section for inserting connection pins to the matrix switch sections of the two matrix switch boards.

Abstract: An Internet Protocol (IP) telephone has a constant impedance filter that is capable of being continuously attached to the physical layer of a computer chip in the IP telephone. The constant impedance filter is located outside the physical layer and is connected to a relay on the physical layer. The relay is configured using native FET devices, which are normally conductive without a supply voltage. Therefore, the relay is capable of operating during the discovery mode of IP telephone operation, where no power is applied to the substrate. Rectifier circuits rectify an incoming signal during discovery mode, and apply the rectified signal to the gate of the relay to improve conductivity of the relay. This allows for faster detection of the IP telephone during discovery mode. During normal operation mode, voltage is applied to the physical layer, and the relay is opened by grounding the native devices.

Abstract: The multi-stage interconnection network of the present invention includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Abstract: A multi-stage interconnection network includes the use of switches in the first stage that have parallel path seeking capabilities. With these switches, a directed flash-flood can be instigated from any one node wherein multiple paths through the network to a designated destination node are tried in parallel in an attempt to find a connection path therebetween. The switches in the first and second stages are interconnected such that each switch in the first stage is connected with every possible priority level to the switches of the second stage. The parallel path seeking switches and network are further configured to test for rejection of the flash-flood by monitoring all connections in combination.

Abstract: A parallel computer system comprises a number of processing elements, at least one communication element, an internal network interconnecting the communications and processing elements, at least one external network connected to the communications element, and a number of services resident in the elements. Each of the elements includes a protocol stack comprising transport, network, logical link and MAC (media access control) layers. Routing messages between services and the external network is performed in the MAC layer, rather than by a relay service at application level as in conventional systems. This improves the efficiency of the system, by obviating the need to pass messages up the stack to the routing function and then to pass them back down the stack again.

Abstract: Disclosed is a cross point mixer including a cross point switch and a mixing circuit provided on the output side. The cross point switch includes n.times.m switches arranged in a matrix manner. Each of the switches corresponds to one of a plurality of n input terminals receiving signals, and corresponds to one of a plurality of m output terminals outputting signals. When on, each of the switches forms a signal transmission path which connects a corresponding input terminal with a corresponding output terminal. The mixing circuit provided on the output side receives signals from the n switches correspondingly associated with the output terminal, and subjects the signals to mixing for output to the output terminal.

Abstract: A cross point switch mounted on a telephone-related device such as a telephone. When an alternate power source request signal is low, switches are controlled in response to external data. When the signal is high, a predetermined switch or switches are forced to be turned on and other switches are forced to be turned off. As a supply voltage obtained from a commercial power supply drops, the request signal goes high. When the request signal is high, a voltage obtained from telephone line power is supplied only to necessary electric circuits. Only the most basic functions such as talking over a telephone line can be used such that power consumption can be minimized.

Abstract: Disclosed is a cross-connect system, such as a feeder distribution interface for telecommunications. User and feeder wires are each coupled to two sides of the matrix in order to provide flexibility in the electrical path. The switches, which are of the double-pole, double-throw variety, are employed at selected crosspoints of the switch matrix in such a manner as to reduce the number of switches required.

Abstract: A circuit to find the first bit 0 or 1 in an m-bit input word from a start bit onwards, the positions of these bits being defined by an n-bit code. It includes a crosspoint matrix of m (4) rows and n (2) columns, each crosspoint including a change-over contact (ABC), with a make contact (AB) and a break contact (AC), and another make contact (AD). The rows of change-over contacts (ABC) are controlled by respective bits of the m-bit word and the break contacts (AC) of the change-over contacts (ABC) of each row are coupled to respective bits of the n-bit code identifying the bit of the m-bit word respectively controlling these break contacts. Furthermore, the make contacts (AB) of the change-over contacts (ABC) of a same column are connected in a closed loop, while the other make contacts (AD) of a same column are connected in a parallel to a same output terminal (IA, IB), the rows of these other make contacts being controlled by a single-row selection circuit (TR).

Abstract: There is described a 2.times.2 switch matrix which includes four 1.times.1 switch matrix modules. Each 1.times.1 switch matrix module consists of an active power divider switch (APDS), an active power combiner switch (APCS) and an air bridge crossover. Additional APDSs and APCSs are utilized in the matrix to compensate for path length differences between different input to output signal paths thus providing good phase and amplitude tracking. The basic switch matrix modules are utilized to form a 2.times.2 switch matrix whereby two primary input ports can be connected to any one of two primary output ports. The 2.times.2 switch matrix is utilized to formulate larger matrix arrays as N.times.M configuration. Each of the active power divider switches and power combiner switches utilize two separate dual gate FETs which are suitably interconnected, depending upon whether the circuit is to be used as a power combiner or power divider.

Abstract: A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current source (M9, M10, M11) enabled by a selection input (Sij) of the crosspoint. The outputs of the first differential amplifier are connected to a second differential amplifier (M1, M2) fed by a second current source (I) common to all the crosspoints of a same column. The outputs of the second differential amplifier are connected to the pair of conductors (Oj1, Oj2) of an output column, an extremity of this column being connected to the high voltage source (Vdd) through a resistor (R).

Abstract: In a broad band signal spaced coupling device comprising a cross point matrix whose switching matrix elements are respectively controllable by a decoder-controlled, cross point-associated memory cell, the cross points are respectively formed with a complementary metal-oxide-semiconductor transfer gate and the useful signal input of each such gate is preceded by a complementary metal-oxide-semiconductor inverter.

Abstract: A broadband signal switching equipment constructed in field effect transistor technology has gates at the inputs of the switching point matrix, and output drive circuits having threshold values at the outputs of the switching point matrix. The output signal of a connection, which preferably proceeds via a switching point residing in the center of the switching point matrix and which transmits a fixed signal during each bit through connect interval, is used to block the gates on the input side, given a change of the signal condition of the output signal, whereby a further charge reversal of the switching point matrix output lines is avoided.

Abstract: A crossbar switch is constructed in monolithic integrated circuit form together with respective memory cells controlling each of the component crosspoint switches in the crossbar switch. The memory cells permit control signals for the crosspoint switches to be supplied serially to the monolithic integrated circuit and thus permit those control signals to be supplied in coded form as orthogonal cross addressing for the memory cells. This reduces the number of bits which must be provided in parallel to the integrated circuit for controlling the crosspoint switches. In preferred embodiments of the crossbar switch, provision is made for operation as a corner-turn array for rotating bit matrices and for faster operation as a barrel shifter.

Abstract: Switches having a relatively high forward resistance are provided in a broadband signal switching equipment comprising a crosspoint matrix constructed in field effect transistor technology and provided with input drivers and output amplifiers. The output amplifiers respectively comprise an iterative network of a hysteresis-affected comparator and a D flip-flop, as well as a holding memory and a switch by way of which the holding memory is reloaded in a respective primary phase of a bit switching time interval. The reloading occurs at least approximately to the potential momentarily prevailing on the output line section leading away from the switch, this potential then continuing to be maintained at the second comparator input in the following switching phase.

Abstract: The invention is a software reconfigurable cross point switch which selectively interconnects a plurality of phone lines and a plurality of shared resources such as call progress monitors, dual tone multifrequency (DTMF) receivers, DTMF automatic dialers and automatic answer tone detectors. The invention achieves its objective of enhanced switching efficiency and greater flexibility in the connectivity between diverse communications elements, by independently switching two separate switching planes of the cross point switch so as to enable different paths to be taken by the transmit portion and the receive portion of a particular telephone connection.The cross point switch architecture invention flexibly allows for many applications, one in particular being conference summing.

Abstract: In a broadband signal space switching device comprising a cross point matrix whose switching elements are respectively controlled by holding storage cells selected by cross point-associated means in two coordinate directions by selection decoders, the holding storage cells being formed by bistable D flip-flops constructed in CMOS technology whose D inputs are connected to the respective decoder output of the row decoder charged with a cross point row address and an address clock signal and whose clock inputs are connected to the corresponding decoder output of the column decoder respectively charged with a cross point column address and an address clock signal.

Abstract: In a broadband signal space switching device comprising a crosspoint matrix constructed in FET technology whose switch elements are respectively controlled by a cross-point-associated memory cell which is decoder-controlled in two coordinate directions, the memory cell is formed by an n-channel transistor and two cross-coupled inverter circuits of which one has its input side connected to the appertaining decoder output of the one selection decoder via an n-channel transistor which, in turn, is charged at its control electrode with the corresponding output signal of the selection decoder, and of which the other leads at its output side to the control input of the appertaining switch element. The switch element is constructed from a single n-channel transistor.

Abstract: In a broadband signal space switching device, the respective switching elements are controllable by a decoder-controlled, crosspoint-associated memory cell and are respectively formed with a CMOS inverter circuit having MOS transistors of the enhancement type which lie between a switching element input and a switching element output. A further p-channel transistor, likewise of the enhancement type, is inserted between the p-channel enhancement transistor and the appertaining feed voltage source and a further n-channel transistor, likewise of the enhancement type, is inserted between the n-channel enhancement transistor and the appertaining feed voltage source. The control electrodes of the further enhancement transistors are connected to the outputs of the memory cell.

Abstract: A microwave planar switch matrix for selectively connecting various ones of M inputs to N outputs. The switch matrix includes a semi-insulative substrate on one side of which are conductors arranged in rows and columns, the interconnection of the rows and columns forming the intersections of the matrix, a plurality M.multidot.N of two-way active power dividers arranged in the rows near each intersection, respectively, and a plurality M.multidot.N of two-way power combiners arranged in the columns near the intersections, respectively, and M.multidot.N switches selectively connecting respectively one output of the power dividers to one input of the power combiners. Because the power dividers and power combiners utilize active components, net power gain through the matrix is possible. Air bridges separate the row and column conductors at the intersections.

Abstract: The invention relates to an ultra-high frequency switching matrix. Only active components, i.e. field effect transistors, are used in the integrated circuit construction of the matrix according to the invention. Coupling between an input channel and an output channel is obtained by a power divider on the input channel, which is a bi-drain transistor or a differential amplifier, a controllable switch in the form of a bi-grid transistor or two transistors in series, and a power combiner on the output channel, which is a multi-grid transistor or several transistors in series. Application is to telecommunications, particularly satellite telecommunications.

Abstract: A multi-stage switching-field formed with switching matrices containing thyristors for stored program controlled switching devices, established by reversal at the last stage, without the use of transformers or other reactive elements therein (e.g. capacitance), in the last stage a holding circuit remains invariable upon switching on, furthermore allocating and switching circuits are ordered to the coupling paths instead of the stages. Circuit arrangements of the switching-field provide the possibility for attenuation control too, and do not require voltages of opposite polarity, while at the same time provide an interface requiring uniform, short operations towards the stored program control device. The switching matrices are switched on at minimal power-level, thus the switching of each further coupling path or connection does not increase the noise level of the already existing connections.

Abstract: In a small PABX with a switching matrix that has electronic crosspoints, integrated selector components comprising multiplexers or demultiplexers in C-MOS technology are used for the switching matrix. By means of individual dialing connection points, which are determined by an appropriate control address supplied by a control computer unit, the individual subscriber lines are to be connected together in internal traffic, and the subscriber lines are to be connected with an exchange line in external traffic. The switching matrix is electrically separated from other operating units by repeating coils in the subscriber lines and in the exchange lines. Central units (tone receiver, tone generator) are connected through free dialing connection points of the multiplexers.

Abstract: A crosspoint for a switching matrix constituted by enhanced P-channel and N-channel MOS transistors. Each input line conductor (Ii1 and Ii2) is connected to an input of a first differential amplifier (M3, M4), each leg of which is associated by a current mirror circuit to a first current source (M9, M10, M11) enabled by a selection input (Sij) of the crosspoint. The outputs of the first differential amplifier are connected to a second differential amplifier (M1, M2) fed by a second current source (I) common to all the crosspoints of a same column. The outputs of the second differential amplifier are connected to the pair of conductors (Oj1, Oj2) of an output column, an extremity of this column being connected to the high voltage source (Vdd) through a resistor (R).