Abstract: Provided is a method for manufacturing a probe card which inspects electrical characteristics of a plurality of semiconductor devices in batch. The method includes: a step of forming a plurality of probes, which are to be brought into contact with external terminals of the semiconductor devices, on one side of a board which forms the base body of the probe card; a step of forming on the board, by photolithography and etching, a plurality of through-holes which reach the probes from the other side of the board; a step of forming, in the through-holes, through electrodes to be conductively connected with the probes, respectively; and a step of forming wiring, which is conductively connected with the through electrodes, on the other side of the board.

Abstract: The embodiments fill the need of improving electromigration and reducing stress-induced voids of copper interconnect by enabling deposition of a thin and conformal barrier layer, and a copper layer in the copper interconnect. The adhesion between the barrier layer and the copper layer can be improved by making the barrier layer metal-rich prior copper deposition and by limiting the amount of oxygen the barrier layer is exposed prior to copper deposition. Alternatively, a functionalization layer can be deposited over the barrier layer to enable the copper layer being deposit in the copper interconnect with good adhesion between the barrier layer and the copper layer. An exemplary method of preparing a substrate surface of a substrate to deposit a functionalization layer over a metallic barrier layer of a copper interconnect to assist deposition of a copper layer in the copper interconnect in an integrated system in order to improve electromigration performance of the copper interconnect is provided.

Abstract: Among other things, self-assembled conductive networks are formed on a surface of substrate containing through holes. The conductive network having a pattern is formed such that at least some of the conductive material in the conductive network reaches into the holes and, sometimes, even the opposite surface of the substrate through the holes. The network on the surface of the substrate electrically connects to the conductive material in the holes with good conductance.

Abstract: Disclosed is a manufacturing method of metal structure in multi-layer substrate. The manufacturing method includes following steps: coating at least one photoresist layer on a surface of a dielectric layer; exposing the photoresist dielectric layer to define a predetermined position of the metal structure; removing the photoresist layer at the predetermined position to undercut an edge of the photoresist layer adjacent to the predetermined position by a horizontal distance of at least 0.1 ?m between a top and a bottom of the edge; forming the metal structure at the predetermined position; and forming at least one top-cover metal layer to cover a top surface and two side surfaces of the metal structure. The present invention can form a cover metal layer covering the top surface and the two side surfaces by one single photomask.

Abstract: Methods for fabricating sub-lithographic, nanoscale microchannels utilizing an aqueous emulsion of an amphiphilic agent and a water-soluble, hydrogel-forming polymer, and films and devices formed from these methods are provided.

Abstract: Zero-valent silver compositions include 4-dimethylaminopyridine as stabilizers. The zero-valent silver and the 4-diemthylaminopyridine form stabilized nano-particles in solution. The zero-valent silver compositions may be used as catalysts in the metallization of non-conductive substrates.

Abstract: The invention comprises methods for filling holes in printed wiring boards and printed wiring boards produced by these methods. The methods involve plating metal conductors inside the holes of the printed wiring boards while protecting the conducting surfaces of the printed wiring boards from being plated using photoresist film. The side surfaces of a printed wiring board are covered with photoresist. The photoresist is exposed to developing light, except the photoresist covering the holes on one side of the board is masked to prevent exposure of the holes to the developing light. The undeveloped photoresist covering the holes is removed. The board is subjected to a plating process, which deposits conductive materials in the holes, but the photoresist on the conducting surfaces of the board prevents conductive materials to be plated on the surfaces of the board.

Abstract: The invention eliminates defects generated in a metal filling a through hole of a printed board by changing an angle at which a plating solution is sprayed or by changing a posture of the printed board at a time point in a process of precipitating the metal from the plating solution and filling the through hole with the precipitated metal while the plating solution or air bubbles are being sprayed onto the printed board.

Abstract: An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector.

Abstract: A plating apparatus and method to perform plating in non-through-hole openings or through-hole openings of a printed wiring board having at least either non-through holes or through-holes to form via-hole conductors or through-hole conductors. The plating method contacts a printed wiring board having the non-through holes or through-holes with a plating solution including plating ingredients, and plates metal on a surface of the printed wiring board while making contact with at least a portion of a pliable contact body.

Abstract: A method for fabricating an acoustic wave device includes the steps of forming an insulating material layer on a piezoelectric substrate, forming a patterned photoresist on the insulating material layer, patterning the insulating material layer, and forming a piezoelectric-substrate exposed depression corresponding to a region where an interdigital transducer electrode is to be formed on a first insulator layer composed of the insulating material layer, depositing a metallic material on the piezoelectric substrate to form the interdigital transducer electrode in the piezoelectric-substrate exposed depression such that the overall interdigital transducer electrode is thinner than the first insulator layer and coating the photoresist with a metallic material, removing the photoresist and the metallic material on the photoresist, and depositing a second insulator layer so as to cover the interdigital transducer electrode and the first insulator layer.

Abstract: The described embodiments may provide a method of fabricating a chemical detection device. The method may comprise forming a microwell above a CMOS device. The microwell may comprise a bottom surface and sidewalls. The method may further comprise applying a first chemical to be selectively attached to the bottom surface of the microwell, forming a metal oxide layer on the sidewalls of the microwell, and applying a second chemical to be selectively attached to the sidewalls of the microwell. The second chemical may lack an affinity to the first chemical.

Abstract: A cartridge block for screening a multilayer ceramic with a conductive paste includes a threaded paste cartridge attachment located at a top of the cartridge block, the threaded paste cartridge attachment being configured to receive a paste cartridge containing the conductive paste; a paste routing section, the paste routing section located underneath the threaded paste cartridge attachment, the paste routing section comprising a flared section located at a bottom of the cartridge block, the paste routing section being configured to receive the conductive paste from the threaded paste cartridge attachment and route the paste through the flared section.

Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

Abstract: There is provided a circuit board including a substrate having a hole. Inside the hole, a metal wiring is formed. The wiring is made of a solder alloy having a melting point of 100 to 600° C., and the metal wiring includes a polycrystalline region of the solder alloy. The metal wiring of the present invention is superior in conductivity.

Abstract: The present invention is a method for fabricating an electrode pair precursor which comprises the steps of creating on one surface of a substrate one or more indents of a depth less than approximately 10 nm and a width less than approximately 1 ?m; depositing a layer of material on the top of this structured substrate to forming a first electrode precursor; depositing another layer the first electrode precursor to form a second electrode precursor; and finally forming a third layer on top of the second electrode precursor.

Abstract: The invention relates to a method for producing a plastic molded part (9) comprising an integrated conductor path (3), which plastic molded part is used in particular as an intermediate product to be further processed into an electrically heatable mirror (1). The method steps are: a) producing a substrate (7) from a carrier body (2) made of an electrically insulating plastic material having a conductor path (3) made of an electrically conductive material on or in a surface (8) of the carrier body (2), b) flooding the surface (8) of the substrate (7) equipped with the conductor path (3) or the surface (11) of the substrate (7) opposite said surface with a liquid, electrically insulating coating material. The flooding evens out depressions due to uneven shrinkage in the thick and thin areas of the carrier body and a smooth surface can be produced, which can subsequently be covered with a reflective layer.

Abstract: A substrate processing method effectively suppresses non-uniformity in deposition degree on a surface of a substrate. The substrate processing method includes depositing a deposit on a sidewall of each opening of a resist pattern, which is formed on an antireflection film on an etching target film of the substrate and is provided with a plurality of openings, before etching the etching target film of the substrate. Plasma is generated in the depositing process by introducing a CHF-based gas into the processing chamber at a flow rate equal to or higher than about 1000 sccm while a pressure in the processing chamber is set to equal to or higher than about 100 mTorr.

Abstract: A conductive paste comprising 88-94% by mass of Ag powder having an average particle size of 3 ?m or less and 0.1-3% by mass of Pd powder, the total amount of the Ag powder and the Pd powder being 88.1-95% by mass. A multilayer ceramic substrate obtained by laminating and sintering pluralities of ceramic green sheets, and having conductor patterns and via-conductors inside, the via-conductors being formed in via-holes having diameters of 150 ?m or less after sintering, containing Ag crystal particles having a particle size of 25 ?m or more, and having a porosity of 10% or less.

Abstract: A method of forming an integrated circuit structure includes providing a substrate; forming a metal feature over the substrate; forming a dielectric layer over the metal feature; and forming an opening in the dielectric layer. At least a portion of the metal feature is exposed through the opening. An oxide layer is accordingly formed on an exposed portion of the metal feature. The method further includes, in a production tool having a vacuum environment, performing an oxide-removal process to remove the oxide layer. Between the step of forming the opening and the oxide-removal process, no additional oxide-removal process is performed to the metal feature outside the production tool. The method further includes, in the production tool, forming a diffusion barrier layer in the opening, and forming a seed layer on the diffusion barrier layer.

Abstract: Disclosed herein are a stiffener and a method for manufacturing the same. The method includes: forming a metal film on an upper surface or a lower surface of a base layer; forming a plurality of via holes penetrating the base layer and the metal film; and forming a first plating film covering an external surface including an inner surface of each of the via holes. The double-sided conductive stiffener according to the present invention can support the device by being disposed on the lower surface of the FPCB, and provide a ground structure of the device through the metal film without using the conductive bond or the conductive tape.

Abstract: The present invention provides a manufacturing method of a semiconductor device that has a rapid film formation rate and high productivity, and to provide a substrate processing apparatus.

Abstract: A wiring board includes: a first wiring layer; a first insulating layer formed on the first wiring layer and including a reinforcing material therein, the first insulating layer having a first opening; a contact layer formed on the first insulating layer and having a second opening communicated with the first opening; and a second wiring layer comprising a second via and a second wiring pattern connected to the second via. The second wiring pattern is formed on the contact layer, and the second via is filled in the first and second openings. An adhesion property between the contact layer and the second wiring pattern is higher than that between the first insulating layer and the second wiring pattern, and a thickness of the contact layer is smaller than that of the first insulating layer.

Abstract: A method of fabricating a wiring board including at least one conductor layer and at least one resin insulating layer, the method including a wiring groove forming step of forming a wiring groove in the resin insulating layer by irradiating a surface of the resin insulating layer with a laser, and a wiring layer forming step of forming the conductor layer such that at least a portion of the conductor layer is embedded in the wiring groove to form a wiring layer in the wiring groove.

Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first insulation layer, a conductive part, a second insulation layer, a seed layer and a conductive layer. The substrate has a first circuit pattern layer and a second circuit pattern layer, which are located on two opposite surfaces of the substrate respectively. The first insulation layer formed on the first circuit pattern layer has a first insulation hole, which exposes a first opening in the outer surface of the first insulation layer. The conductive part formed on the first insulation hole for electrically connecting with a chip is enclosed by the edge of the first opening. The second insulation layer formed on the second circuit pattern layer has a second insulation hole in which the seed layer is formed. The conductive layer is formed on the seed layer for electrically connecting with a circuit board.

Abstract: The present invention provides the technology for burying metal even in a fine concave portion such as trench and via. According to an embodiment of the present invention, a vapor of the metal as the objective material, a gas containing halogen for etching the metal, and a metal halide vapor made up of the metal element and the halogen element are supplied to the substrate, which thus forms a metal halide layer in the concave portion, and thereby deposits the metal under the metal halide layer. The procedure can achieve the above object.

Abstract: Providing a method for manufacturing a package capable of improving production efficiency.

Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.

Abstract: Disclosed is a method for forming a metal line. The method includes preparing a semiconductor substrate having a first metal line, performing an oxidation process with respect to the first metal line, performing an oxide removal process to remove an oxide generated in the oxidation process, forming an etch stop layer on the metal line, forming an interlayer dielectric layer on the first metal line, and forming a damascene pattern on the interlayer dielectric layer, and forming a second metal line, which is connected with the first metal line, in the damascene pattern. The oxidation process for the first metal line can include a hydrogen peroxide treatment process using a solution including oxygen. The oxide removal process can be performed by using an oxalic acid (HOOC—COOH) solution.

Abstract: An enhanced mechanism is disclosed for via stub elimination in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first and second ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first and second conductive vias are respectively plated onto the first and second through-holes. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the first and second conductive vias from extending substantially beyond the first and second internal conductive traces, respectively, and thereby prevent via stubs from being formed in the first place.

Abstract: A method for manufacturing a printed circuit board, in which an oxidant capable of polymerizing conductive polymers is selectively marked on a board using imprinting, and the monomer of a conductive polymer is filled in the selected pattern and polymerized, to provide a conductive polymer wiring pattern. With the method for manufacturing a printed circuit board, a printed circuit board can be given finer wiring widths to allow a highly integrated, highly efficient printed circuit board. Thus, a printed circuit board (PCB) or a flexible printed circuit boards (FPCB) can be manufactured that is applicable to industrial, clerical, and domestic electric electronic products, by forming conductive polymer wiring using imprinting.

Abstract: A mask film, where squeegee cleaning part has been formed at a predetermined position, and another mask film are attached to both sides of a substrate. A through-hole is formed by using a laser, and conductive paste is filled into the through-hole by using a squeezing method. As discussed above, a paste-residue can be prevented on the through-hole, so that a circuit board having high quality of connection can be obtained.

Abstract: A wiring board including a conductor post corresponding to high-density packaging is provided. The wiring board may comprise a conductor layer, a solder resist layer laminated on the conductor layer, and a conductor post that is electrically connected to a conductor layer which is disposed in a lower portion of a through-hole provided in the solder resist layer, wherein the solder resist layer comprises a thermosetting resin; the conductor post comprises tin, copper, or a solder; the conductor post includes a lower conductor post, which is located within the through-hole and includes an external side surface and a lower end surface, and an upper conductor post, which is located above the lower conductor post and is projected outside the solder resist layer; and at least a part of a lower end surface of the upper conductor post is brought into intimate contact with an outer surface of the solder resist layer.

Abstract: A system of metalization in an integrated polymer microsystem. A flexible polymer substrate is provided and conductive ink is applied to the substrate. In one embodiment the flexible polymer substrate is silicone. In another embodiment the flexible polymer substrate comprises poly(dimethylsiloxane).

Abstract: A fabrication method is capable of creating canonical metamaterial structures arrayed in a three-dimensional geometry. The method uses a membrane suspended over a cavity with predefined pattern as a directional evaporation mask. Metallic and/or dielectric material can be evaporated at high vacuum through the patterned membrane to deposit resonator structures on the interior walls of the cavity, thereby providing a unit cell of micron-scale dimension. The method can produce volumetric metamaterial structures comprising layers of such unit cells of resonator structures.

Abstract: A method for manufacturing an electro-optical device in which thin film layers are formed by drying droplets containing a thin film layer formation material, and these thin film layers are laminated to form a light emitting element, includes mixing lyophilic microparticles that are lyophilic with respect to droplets that form an upper thin film layer into droplets that form a lower thin film layer, and drying the droplets in which these lyophilic microparticles have been mixed to form the lower thin film layer, and then drying the droplets that form the upper thin film layer on the lower thin film layer to laminate the upper thin film layer over the lower thin film layer.

Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.

Abstract: The present invention provides a method for modification of microchannels of a polydimethylsiloxane (PDMS) microchip, which includes the steps of: a) mixing an alkoxysilane precursor, an alkyl alkoxysilane precursor, and a solvent to prepare a sol-gel solution; b) oxidizing microchannels of the PDMS microchip; and c) coating the oxidized microchannels with the sol-gel solution prepared in step a). The PDMS microchip modified according to the method of the present invention shows higher hydrophilicity than an unmodified PDMS microchip. And, when the modified PDMS channels are filled with an organic solvent, channel swelling can be reduced, and thus various organic solvents can be used for the modified PDMS microchip compared to an unmodified PDMS microchip. Further, it can be widely applied for various fields because absorptivity of non-polar substances can be reduced.

Abstract: In accordance with one embodiment, a method of forming a protruding post substrate package includes applying a dielectric layer to a carrier. Via apertures are formed in the dielectric layer. Carrier cavities are formed in the carrier using the dielectric layer as a mask. The carrier cavities are lined with a first metal, the first metal being selectively etchable compared to the carrier. After encapsulation of an electronic component with an encapsulant, the carrier is removed such that protruding posts including the first metal protrude outward from a first surface of the dielectric layer.

Abstract: A cartridge block for screening a multilayer ceramic with a conductive paste includes a threaded paste cartridge attachment located at a top of the cartridge block, the threaded paste cartridge attachment being configured to receive a paste cartridge containing the conductive paste; a paste routing section, the paste routing section located underneath the threaded paste cartridge attachment, the paste routing section comprising a flared section located at a bottom of the cartridge block, the paste routing section being configured to receive the conductive paste from the threaded paste cartridge attachment and route the paste through the flared section.

Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.

Abstract: Methods for fabricating integrated circuit electrical interconnects and electrical interconnects are provided. Methods include providing a substrate having a surface, the surface having a feature formed therein wherein the feature is a trench or via, depositing a metal layer, the metal of the metal layer being selected from the group consisting of Ru, Co, Pt, Ir, Pd, Re, and Rh, onto surfaces of the feature, depositing a copper seed layer wherein the copper seed layer comprises a dopant and the dopant is selected from the group consisting of Mn, Mg, MgB2. P, B, Al, Co and combinations thereof, onto the metal layer, and depositing copper into the feature. Devices comprising copper interconnects having metal liner layers are provided. Devices having liner layers comprising ruthenium are provided.

Abstract: A method of forming a single-metal film on a substrate by plasma ALD includes: contacting a surface of a substrate with a ?-diketone metal complex in a gas phase; exposing molecule-attached surface to a nitrogen-hydrogen mixed plasma; and repeating the above steps, thereby accumulating atomic layers to form a single-metal film on the substrate.

Abstract: Disclosed is an electroless plating solution exhibiting a good plating metal filling performance even for larger trenches or vias of several to one hundred and tens of ?m, in a manner free from voids or seams, and allowing maintenance of stabilized performance for prolonged time. The electroless plating solution contains at least a water-soluble metal salt, a reducing agent for reducing metal ions derived from the water-soluble metal salt, and a chelating agent. In addition, the electroless plating solution contains a sulfur-based organic compound as a leveler having at least one aliphatic cyclic group or aromatic cyclic group to which may be linked at least one optional substituent. The aliphatic cyclic group or the aromatic cyclic group contains optional numbers of carbon atoms, oxygen atoms, phosphorus atoms, sulfur atoms and nitrogen atoms.

Abstract: A first artwork layer having a first adaptable-mask section allows a graded amount of light to pass into an underlying first photoresist layer. Subsequent to developing the first photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least a lower portion of a rounded trace. A dielectric layer is laminated upon the lower portion and a second artwork layer having an second adaptable-mask section allows a graded amount of light to pass into a second photoresist layer. Subsequent to developing the second photoresist layer, the graded amount of light creates a rounded geometric void used as a mold or sidewall for the creation of at least an upper portion of a rounded trace. The photoresist and dielectric layers are removed resulting in a circuit apparatus having a rounded differential pair trace.

Abstract: A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.

Abstract: Disclosed is a method for film formation, characterized by comprising allowing a treatment gas stream containing a metal carbonyl-containing treatment gas and a carbon monoxide-containing carrier gas to flow into a region on the upper outside of the outer periphery of a substrate to be treated in a diameter direction of the substrate while avoiding the surface of the substrate and diffusing the metal carbonyl from the treatment gas stream into the surface of the substrate to form a metal film on the surface of the substrate.

Abstract: A method for placing material onto a target board by means of a transfer board comprising a plurality of blind holes, the method comprising the steps of immersing the transfer board in a material bath, wherein a first pressure acts on the material bath and a second pressure acts in the blind holes, and wherein the first pressure and the second pressure are substantially equal; generating a pressure difference between the first pressure and the second pressure, so that the blind holes of the transfer board are filled at least partially with the liquid material; extracting the transfer board from the material bath; and positioning the transfer board opposite to the target board, the material being expelled from the blind holes, such that the material touches the target board.

Abstract: Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies are provided. In one embodiment, the invention relates to a method of manufacturing a printed circuit board including providing a core subassembly including at least one metal layer, providing a plurality of one-metal layer carriers after parallel processing each of the plurality of one-metal layer carriers, and attaching at least two of the plurality of one-metal layer carriers with each other and with the core subassembly.

Abstract: There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content.