Printed Circuit Patents (Class 428/901)
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Patent number: 7736749Abstract: A process for producing a silicone polymer comprising a step of subjecting, to hydrolysis and polycondensation reaction, a silane compound mixture containing 35 to 100% by mol of a silane compound represented by the general formula (I): R?m(H)kSiX4?(m+k)??(I) (wherein X is a hydrolysable and polycondensable group, e.g., a halogen atom (e.g., chlorine or bromine) or —OR; R is an alkyl group of 1 to 4 carbon atoms or an alkyl carbonyl group of 1 to 4 carbon atoms; R? is a non-reactive group, e.g., an alkyl group of 1 to 4 carbon atoms or an aryl group (e.g., a phenyl group); “k” is 1 or 2; “m” is 0 or 1; and “m+k” is 1 or 2), and further subjecting the resultant product to hydrosilylation reaction with a hydrosilylation agent.Type: GrantFiled: September 29, 2006Date of Patent: June 15, 2010Assignee: Hitachi Chemichal Co., Ltd.Inventors: Hideo Baba, Nozomu Takano, Kazuhiro Miyauchi
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Patent number: 7691458Abstract: Numerous embodiments of a carrier substrate having thermochromatic materials are described. In one embodiment of the present invention, a carrier substrate has a visible surface, and a thermochromatic material is disposed near the carrier substrate. The thermochromatic material produces a visual change of the visible surface when an activation temperature of the thermochromatic material is reached.Type: GrantFiled: March 31, 2004Date of Patent: April 6, 2010Assignee: Intel CorporationInventors: Gary A. Brist, Patrick D. Boyd
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Patent number: 7658988Abstract: Compositions and processes for the preparation of printed circuits from epoxy compositions are provided. The epoxy compositions exhibit low viscosity in the uncured state and low coefficient of thermal expansion in the cured state. The low dielectric constant compositions of the invention are well-suited for use in multi-layer printed circuit boards.Type: GrantFiled: April 3, 2007Date of Patent: February 9, 2010Assignee: E. I. du Pont de Nemours and CompanyInventors: Pui-Yan Lin, Govindasamy Paramasivam Rajendran, George Elias Zahr
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Patent number: 7655292Abstract: An electrically conductive substrate with a high heat conductivity has an aluminum plate having multiple holes. An isolation layer is formed on the aluminum plate and inner walls of the holes. Multiple electrically conductive materials are inserted in the holes. A circuit layer is formed on the aluminum plate, electrically connects to the electrically conductive materials and has a rough surface. A graphite layer is formed on the rough surface of the circuit layer. The electric components are respectively provided on the holes, and the heat generated by the electric components is dissipated effectively by the aluminum plate.Type: GrantFiled: April 11, 2007Date of Patent: February 2, 2010Assignee: Kaylu Industrial CorporationInventor: Li-Wei Kuo
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Patent number: 7615277Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 ?m or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.Type: GrantFiled: November 15, 2004Date of Patent: November 10, 2009Assignee: Hitachi Chemical Company, Ltd.Inventors: Kenji Takai, Norio Moriike, Kenichi Kamiyama, Katsuyuki Masuda, Kiyoshi Hasegawa
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Patent number: 7579070Abstract: Methods to improve adhesion of a first material to a second material and electronics devices fabricated using such methods are described. A porous polymer layer is formed on a conductive layer. Forming the porous polymer layer leaves portions of the conductive layer exposed. A porous conductive layer is formed over the porous polymer layer and the exposed portions of the conductive layer. A continuous polymer layer is formed over the porous conductive layer. In one embodiment, the polymer layer includes a ferroelectric polymer, and the conductive layer includes a noble metal, e.g., gold.Type: GrantFiled: August 30, 2005Date of Patent: August 25, 2009Assignee: Intel CorporationInventor: Lee Rockford
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Patent number: 7572503Abstract: Directed to an insulating resin composition which comprises (A) a novolak epoxy resin having a biphenyl structure, (B) carboxylic acid-modified acrylonitrile butadiene rubber particles, (C) a triazine ring-containing cresol novolak phenolic resin, (D) a phenolic hydroxyl group-containing phosphorus compound, and (E) inorganic filler, an insulating film having a support using the same, a multilayer wiring board, and a process for producing a multilayer wiring board.Type: GrantFiled: June 24, 2005Date of Patent: August 11, 2009Assignee: Hitachi Chemical Co., Ltd.Inventors: Shin Takanezawa, Koji Morita, Takako Watanabe, Toshihisa Kumakura, Hiroyuki Fukai, Hiroaki Fujita
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Patent number: 7524388Abstract: A method of forming a dielectric substrate comprises contacting a liquid crystalline polymer fibrous web having a thickness of 5 mils (127 micrometers) or less with a resin composition to form a dielectric composite. Contacting is carried out under vacuum, followed by pressure. The dielectric substrate is useful in circuit materials, circuits, and multi-layer circuits, economical to make, and has excellent dielectric strength.Type: GrantFiled: May 10, 2006Date of Patent: April 28, 2009Assignee: World Properties, Inc.Inventors: E. Clifford Roseen, Jr., Murali Sethumadhavan
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Patent number: 7494635Abstract: Novel boron nitride agglomerated powders are provided having controlled density and fracture strength features. In addition methods for producing same are provided. One method calls for providing a feedstock powder including boron nitride agglomerates, and heat treating the feedstock powder to form a heat treated boron nitride agglomerated powder. In one embodiment the feedstock powder has a controlled crystal size. In another, the feedstock powder is derived from a bulk source.Type: GrantFiled: August 21, 2003Date of Patent: February 24, 2009Assignee: Saint-Gobain Ceramics & Plastics, Inc.Inventors: Eugene A. Pruss, Thomas M. Clere
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Patent number: 7488532Abstract: The present invention is to provide an adhesive resin composition for use in preparing an adhesive in the form of a film which is excellent in the adhesiveness at a low temperature and in the heat resistance, an adhesive in the form of a film comprising the adhesive resin composition, and a semiconductor device using the adhesive in the form of a film.Type: GrantFiled: April 13, 2004Date of Patent: February 10, 2009Assignee: Mitsui Chemicals, Inc.Inventors: Youichi Kodama, Hiroshi Maruyama, Isao Naruse
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Patent number: 7485362Abstract: A process of making a nanoporous substrate, such as the matrix in an electrical laminate, by grafting onto an organic resin backbone a thermolabile functionality by reacting hydrogen active groups of the organic resin with a compound containing thermolabile groups; then thermally degrading the thermolabile groups grafted on the organic resin to form a nanoporous laminate. Advantageously, the nanoporous electrical laminate has a low dielectric constant (Dk) because of the nanopores present in the laminate matrix.Type: GrantFiled: December 20, 2004Date of Patent: February 3, 2009Assignee: Dow Global Technologies Inc.Inventors: Ludovic L. Valette, Catherine Marestin, Regis Mercier
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Patent number: 7470461Abstract: Provided is a method of manufacturing a printed circuit board. In an embodiment, the method includes forming a prepreg layer via a reel method, forming a conductive film for forming a circuit pattern on at least one surface of the prepreg layer; and forming a predetermined circuit pattern on the conductive film. In an embodiment, the prepreg layer has a thickness of at most about 0.15 mm and contains a fiber material and a resin material. In an embodiment, the content of the resin material in the prepreg layer is about 70% or less by volume. In an embodiment, the prepreg layer is composed of at least one prepreg layer.Type: GrantFiled: October 5, 2005Date of Patent: December 30, 2008Assignee: Samsung Techwin Co., Ltd.Inventors: Chang-soo Jang, Dong-kwan Won, Hyoung-ho Roh, Jae-chul Ryu
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Patent number: 7438969Abstract: A solvent-free filling material comprising a filler, a thermosetting resin, a curing agent, and a curing catalyst, wherein the thermosetting resin is an epoxy resin, and the curing agent is a dicyandiamide curing agent; a multilayer printed wiring board comprising a substrate, a through-hole, the filling material filling the through-hole, and a conductor layer formed on an exposed surface of the filling material in the through-hole; and a process for producing the multilayer printed wiring board.Type: GrantFiled: July 9, 2003Date of Patent: October 21, 2008Assignee: NGK Spark Plug Co., Ltd.Inventors: Toshifumi Kojima, Makoto Wakazono, Toshikatu Takada
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Patent number: 7396588Abstract: A curable composition comprises an insulating resin and a halogen-free flame retardant. The halogen-free flame retardant has a particulate form, and whose primary particles have an average major axis from 0.01 to 5 ?m, an aspect ratio of 5 or less, and the proportion of a major axis of more than 10 ?m being at most 10% by number. A varnish comprises an insulating resin, a curing agent, a flame retardant and an organic solvent. The flame retardant is a flame retardant in particulate form surface-treated with a coupling agent, and the flame retardant particles present in the varnish have a secondary particle diameter of 30 ?m or less.Type: GrantFiled: November 14, 2006Date of Patent: July 8, 2008Assignee: Zeon CorporationInventors: Yasuhiro Wakizaka, Toshiyasu Matsui, Daisuke Uchida, Koichi Ikeda
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Patent number: 7390571Abstract: Disclosed are a varnish for laminate or prepreg, comprising a heat treatment product which is obtained by mixing together (a) an epoxy resin, (b) dicyandiamide, and (c) a compound having an imidazole ring so that the component (c) is present in an amount of 0.001 to 0.03% by weight, based on the weight of the component (a), and subjecting the resultant mixture to reaction for heat treatment in an organic solvent at a temperature of 70° C. to less than 140° C. so that all of the components are compatible with one another in the absence of a solvent; and (d) inorganic filler, a laminate or prepreg prepared using the varnish and a printed wiring board prepared using the laminate and/or prepreg.Type: GrantFiled: February 27, 2006Date of Patent: June 24, 2008Assignee: Hitachi Chemical Co., Ltd.Inventors: Yasuyuki Hirai, Norihiro Abe, Yoshiyuki Takeda
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Patent number: 7383629Abstract: A circuitized substrate in which two conductive layers (e.g., electroplated copper foil) are bonded (e.g., laminated) to an interim dielectric layer. Each of the two foil surfaces which physically bond to the dielectric are smooth (e.g., preferably by chemical processing) and include a thin, organic layer thereon, while the outer surfaces of both foils are also smooth (e.g., preferably also using a chemical processing step). One of these resulting conductive layers may function as a ground or voltage plane while the other may function as a signal plane with a plurality of individual signal lines as part thereof. An electrical assembly and an information handling system utilizing such a circuitized substrate are also provided, as is a method of making the substrate.Type: GrantFiled: November 19, 2004Date of Patent: June 10, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, Voya R. Markovich, Michael Wozniak
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Patent number: 7356916Abstract: A circuit board with reliable electrical connections is provided. An insulated board material, having connections for connecting a layer to another layer, includes a reinforcing member. A thickness of the entire insulated board material is at least equal to and not more than 1.5 times of a thickness of the reinforcing member.Type: GrantFiled: July 16, 2002Date of Patent: April 15, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toshihiro Nishii, Yasuharu Fukui, Kiyohide Tatsumi, Yoshihiro Kawakita, Shinji Nakamura, Hideaki Komoda
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Patent number: 7348080Abstract: The present invention relates to a polyimide adhesive composition having a polyimide derived from an aromatic dianhydride and a diamine component, where the diamine component is preferably about 50 to 90 mole % of an aliphatic diamine and about 10 to 50 mole % of an aromatic diamine. In one embodiment, the aliphatic diamine has the structural formula H2N—R—NH2 wherein R is hydrocarbon from C4 to C16 and the polyimide adhesive has a glass transition temperature in the range of from 150° C. to 200° C. The present invention also relates to compositions comprising the polyimide adhesive of the present invention, including polyimide metal-clad laminate useful as flexible circuit when metal traces are formed out of the metal used in flexible, rigid, or flex-rigid circuit applications.Type: GrantFiled: November 18, 2005Date of Patent: March 25, 2008Assignee: E.I. du Pont de Nemours and CompanyInventor: Kuppusamy Kanakarajan
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Patent number: 7348069Abstract: A first ceramic substrate includes a substrate (2) and a glaze layer (3), wherein the glaze layer has a surface having an Ra of 0.02 ?m or less and a Ry of 0.25 ?m or less. A second ceramic substrate is formed by subjecting a glass layer (24) formed on a surface of a substrate (2) to heating-and-pressurizing treatment, thereby forming a glaze layer (3) on the substrate (2), and planarization-polishing the surface of the glaze layer. A third ceramic substrate includes a substrate (2), a glaze layer (3) containing substantially no pores formed on the substrate (2) and the surface thereof being planarization-polished, and a wiring pattern (21), wherein at least one first end of the wiring pattern is exposed to the glaze layer (3) surface of the substrate (1), and at least one second end is exposed to another surface of the substrate (1).Type: GrantFiled: September 29, 2004Date of Patent: March 25, 2008Assignee: NGK Spark Plug Co., Ltd.Inventors: Seiji Ichiyanagi, Jun Otsuka, Manabu Sato, Masahiko Okuyama
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Patent number: 7332231Abstract: A ceramic substrate for a thin film electronic component, a production method thereof, and a thin film electronic component using the ceramic substrate A first substrate (1) includes a dense glass-ceramic mixed layer (33) containing glass in its surface portion. A second substrate is prepared such that a glass layer (32) formed on a surface of a substrate base portion (2) is subjected to a heat-pressure treatment so as to form or rather partly change the glass portion (32) into a dense glass-ceramic mixed layer (33) in which glass is dispersed into a surface portion of the substrate base portion (2). A surface of the dense glass-ceramic mixed layer (33) is then subjected to grinding or rather polishing to flatten and expose a surface of the dense glass-ceramic mixed layer (32). A third substrate includes a substrate base portion (2) having a dense glass-ceramic mixed layer (33) containing glass on a surface portion in one face side, and a wiring pattern (21) formed inside the substrate base portion (2).Type: GrantFiled: October 6, 2004Date of Patent: February 19, 2008Assignee: NGK Spark Plug Co., Ltd.Inventors: Seiji Ichiyanagi, Jun Otsuka, Manabu Sato
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Patent number: 7332212Abstract: A method of making a circuitized substrate such as a laminate chip carrier in which a polymer, e.g., Teflon, is used as a dielectric layer and a promotion adhesion layer of a polymer is used to securely adhere a conductive layer thereto which is deposited by plating. The resulting product is thus able to provide extremely narrow conductive circuitry for subsequent connections, e.g., to a semiconductor chip. Electroless plating is the preferred plating method with the dielectric immersed in a solution of conductive monomers, e.g., pyrrole monomer, the solution also possibly containing a seed material such as palladium-tin.Type: GrantFiled: October 5, 2005Date of Patent: February 19, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Elizabeth Foster, Gregory Kevern, Anita Sargent
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Publication number: 20080000679Abstract: A wired circuit board has an insulating layer and a conductive pattern formed on the insulating layer and made of a copper alloy in which silver is diffused, wherein a content ratio of the silver contained in the copper alloy is more than 0.50% by weight and not more than 3.Type: ApplicationFiled: June 11, 2007Publication date: January 3, 2008Applicant: Nitto Denko CorporationInventors: Katsutoshi Kamei, Jun Ishii, Yasunari Ooyabu, Visit Thaveeprungsriporn
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Patent number: 7311966Abstract: A porous insulating film comprising a highly heat resistant resin film having a fine porous structure with a mean pore size of 0.01-5 ?m in at least the center of the film, and a porosity of 15-80%. A laminate is prepared by forming a heat resistant adhesive layer or a conductive metal layer or an inorganic or metal substrate on one or both sides of the porous insulating film or by forming an inorganic or metal substrate on one side of the porous insulating film and a conductive metal layer on the other side.Type: GrantFiled: September 6, 2006Date of Patent: December 25, 2007Assignee: Ube Industries, Ltd.Inventors: Shigeru Yao, Yukihiko Asano, Shyusei Ohya, Kenji Fukunaga, Masayuki Kinouchi, Kenji Kawabata
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Publication number: 20070281142Abstract: A resin composition suitable for manufacturing an electrical insulative resin film for a printed wiring board is composed of 80 to 99.5 mass % of a first graft copolymer (a) and 0.5 to 20 mass % of a second graft copolymer (b). In the first graft copolymer (a), 15 to 40 parts by mass of an aromatic vinyl monomer are grafted to 60 to 85 parts by mass of a random or block copolymer composed of monomer units selected from nonpolar ?-olefin monomers and nonpolar conjugated diene monomers. In the second graft copolymer (b), 5 to 30 parts by mass of an aromatic vinyl monomer are grafted to 70 to 95 parts by mass of a random or block copolymer composed of 60 to 90 mass % of a monomer unit, which is selected from nonpolar ?-olefin monomers and nonpolar conjugated diene monomers, and 10 to 40 mass % of an aromatic vinyl monomer unit.Type: ApplicationFiled: May 30, 2007Publication date: December 6, 2007Applicant: NOF CORPORATIONInventors: Toshihiro Ohta, Kensaku Sonoda, Tomiho Yamada
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Die for forming an optical element, and production method as well as regeneration method of the same
Patent number: 7304392Abstract: A die for forming an optical element, comprising: (i) a base member having a base surface which comprises a foundation area including a die surface to form an optical surface of the optical element and a peripheral area provided around the foundation area; (ii) a first layer covering both of the foundation area and the peripheral area and removable by being dissolved in a processing solution; and (iii) a second layer covering a part of the first layer corresponding in position to the foundation area so that a remaining part of the first layer corresponding in position to the peripheral area is not covered by the second layer.Type: GrantFiled: May 23, 2005Date of Patent: December 4, 2007Assignee: Konica Minolta Opto, Inc.Inventors: Shuhei Hayakawa, Shunichi Hayamizu, Kazuyuki Ogura, Naoyuki Fukumoto -
Patent number: 7303811Abstract: A porous insulating film comprising a highly heat resistant resin film having a fine porous structure with a mean pore size of 0.01-5 ?m in at least the center of the film, and a porosity of 15-80%. A laminate is prepared by forming a heat resistant adhesive layer or a conductive metal layer or an inorganic or metal substrate on one or both sides of the porous insulating film or by forming an inorganic or metal substrate on one side of the porous insulating film and a conductive metal layer on the other side.Type: GrantFiled: February 25, 2004Date of Patent: December 4, 2007Assignee: Ube IndustriesInventors: Shigeru Yao, Yukihiko Asano, Shyusei Ohya, Kenji Fukunaga, Masayuki Kinouchi, Kenji Kawabata
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Patent number: 7301228Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.Type: GrantFiled: December 3, 2003Date of Patent: November 27, 2007Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Kojima, Noriaki Sakamoto
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Patent number: 7294389Abstract: In a method of fabricating an array of microstructures, a substrate with an electrically-conductive portion is provided, an insulating mask layer is formed on the electrically-conductive portion of the substrate, a plurality of openings are formed in the insulating mask layer to expose the electrically-conductive portion, and a first plated or electrodeposited layer is deposited in the openings and on the insulating mask layer by electroplating or electrodeposition. A second plated layer is further formed on the first plated or electrodeposited layer and on the electrically-conductive portion by electroless plating to reduce a size distribution of microstructures over the array.Type: GrantFiled: September 1, 2004Date of Patent: November 13, 2007Assignee: Canon Kabushiki KaishaInventors: Takayuki Teshima, Takayuki Yagi, Yasuhiro Shimada, Takashi Ushijima
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Publication number: 20070259160Abstract: A circuit board has a copper foil layer provided on one side thereof, a tin layer provided on a top of the copper foil layer, and a heat radiating sheet provided on the tin layer. When the circuit board is processed in a reflow oven, the tin layer is melted to associate with the copper foil layer and the heat radiating sheet. High amount of heat produced by electronic elements mounted on the circuit board during operation thereof is absorbed by the copper foil layer and then transmitted to the tin layer, which quickly transfers the absorbed heat to the heat radiating sheet that has a large radiating area, so that the heat is more quickly dissipated into air. A heat pipe may be embedded in the tin layer to enhance the radiating efficiency, so that the electronic elements on the circuit board always have a normal operating temperature.Type: ApplicationFiled: November 7, 2006Publication date: November 8, 2007Inventor: Yu Li Huang
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Publication number: 20070259159Abstract: A flexible printed circuit board substrate comprising a conductive layer and a support layer bonded to the conductive layer, in which the support layer comprises a metal layer for structural support, an adhesive layer formed on one side of the metal layer for bonding the metal layer to the conductive layer, and a protective layer formed on the other side of the metal layer. The flexible printed circuit board substrate according to the present invention can avoid the problem of substrate warpage caused by dimension variations frequently encountered by a conventional flexible printed circuit board substrate.Type: ApplicationFiled: August 28, 2006Publication date: November 8, 2007Inventors: Syh-Tau Yeh, Yao-Ming Chen
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Patent number: 7291380Abstract: A method of plating a substrate including coating a substrate surface, laser-treating a region of the coated surface, and plating the region.Type: GrantFiled: July 9, 2004Date of Patent: November 6, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Peter S. Nyholm, Curt Lee Nelson, Niranjan Thirukkovalur, Paul McClelland
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Patent number: 7282255Abstract: The present invention relates to a flexible printed circuit board which has extremely high adhesion performance and on which very fine circuit patterns can be formed by etching, and to a method for producing the same. In the present invention, in the flexible printed circuit board wherein a copper thin film made of copper or an alloy containing primarily copper is directly formed on at least one side of a plastic film substrate, and copper is formed further on the copper thin film by the electrolytic plating method, the above-mentioned copper thin film has a two-layer structure in which a layer including at least a crystalline structure is formed on the surface side thereof, and the X-ray relative intensity ratio between crystal lattice plane indices (200)/(111) in the above-mentioned crystalline structure is 0.1 or less.Type: GrantFiled: April 17, 2003Date of Patent: October 16, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kouichi Hiranaka, Ryuichi Nakagami, Mitsuhiro Fukuoka, Motohiro Yamashita
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Patent number: 7279216Abstract: The invention discloses an identifiable flexible printed circuit board (PCB) and a method of fabricating the same. The identifiable flexible PCB includes a flexible substrate, a conductive layer, and a printing ink layer. First, the conductive layer is formed over a surface of the flexible substrate. Second, the printing ink layer is formed on the surface of the flexible substrate by coating, exposing, and developing to uncover parts of the conductive layer. Also, at least one identifiable area is formed on the printing ink layer and one can easily and correctly identify the cartridge with the flexible PCB.Type: GrantFiled: October 24, 2005Date of Patent: October 9, 2007Assignee: Benq CorporationInventors: Chih-Ching Chen, Yi-Jing Leu
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Publication number: 20070231469Abstract: Compositions and processes for the preparation of printed circuits from epoxy compositions are provided. The epoxy compositions exhibit low viscosity in the uncured state and low coefficient of thermal expansion in the cured state. The low dielectric constant compositions of the invention are well-suited for use in multi-layer printed circuit boards.Type: ApplicationFiled: April 3, 2007Publication date: October 4, 2007Inventors: Pui-Yan Lin, Govindasamy Paramasivam Rajendran, George Elias Zahr
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Patent number: 7273654Abstract: A punched adhesive tape for semiconductor which is made by punching an adhesive tape comprising a base film and an adhesive layer provided on one or each side of the base film to mark the regions in the adhesive tape where contaminants or defects are contained; a method of producing an adhesive tape-bearing lead frame by punching the punched adhesive tape for semiconductor, with the parts containing the punched holes skipped over, and applying the adhesive tape pieces punched out from the punched adhesive tape for semiconductor to a lead frame; a semiconductor device fabricated by using the adhesive-bearing lead frame.Type: GrantFiled: September 19, 2002Date of Patent: September 25, 2007Assignee: Hitachi Chemical Company, Ltd.Inventors: Yoshiyuki Tanabe, Yoshihiro Nomura, Hiroshi Kirihara, Youichi Hosokawa, Shinji Iioka, Satoru Yanagisawa
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Publication number: 20070212529Abstract: A printed circuit board having a metal core is disclosed. A printed circuit board that includes a metal core and an insulation layer stacked on at least one surface of the metal core, where a portion of the insulation layer is removed to expose an edge surface of the metal core to the exterior and thereby form an exposed surface, allows superb heat release through the exposed surface.Type: ApplicationFiled: March 9, 2007Publication date: September 13, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung-Hyun Cho, Sang-Jin Oh, Young-Goo Kim, Kwang-Yune Kim
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Patent number: 7263766Abstract: An insulating substrate (1) has insulative ceramic layers (2, 3) laid one upon another, an intermediate layer (4) made of a material that is different from a material of the ceramic layers and arranged between adjacent ones of the ceramic layers to join the adjacent ceramic layers to each other, a first conductive layer (5) joined to the top surface of a top one of the ceramic layers, and a second conductive layer (6) joined to the bottom surface of a bottom one of the ceramic layers. Even if any one of the ceramic layers has strength lower than design strength and causes a breakage due to, for example, thermal stress, the remaining ceramic layers are sound to secure a specified breakdown voltage for the insulating substrate.Type: GrantFiled: January 27, 2003Date of Patent: September 4, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Yutaka Ishiwata, Kosoku Nagata, Toshio Shimizu, Hiroyuki Hiramoto, Yasuhiko Taniguchi, Kouji Araki, Hiroshi Fukuyoshi, Hiroshi Komorita
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Publication number: 20070202307Abstract: Disclosed herein is a rigid flexible PCB having openings. The rigid flexible PCB includes a flexible section with flexibility and rigid sections being formed at the edges of the flexible section with mechanical stiffness. The flexible section comprises a flexible plane. The flexible plane comprises a base insulating layer; a wire conducting layer being adhered to one of the top side and the bottom side of the base insulating layer; and a plane conducting layer adhered to the other of the top side and the bottom side of the base insulating layer. The plane conducting layer has a plurality of openings being formed as a mesh structure. According to the rigid flexible PCB of the invention, the flexibility of the flexible section and the characteristic impedance of signal wire traces may be improved.Type: ApplicationFiled: December 1, 2006Publication date: August 30, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Ha OH, Jong-Hoon KIM
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Patent number: 7258819Abstract: The present invention provides an improved voltage variable material (“VVM”). More specifically, the present invention provides an improved printed circuit board substrate, an improved device having circuit protection an improved data communications cable having circuit protection and a method for mass producing devices employing the VVM substrate of the present invention. The VVM substrate eliminates the need for an intermediate daughter or carrier board by impregnating conductive particles and possibly semiconductive and/or insulative particles associated with known volatage variable materials into the varnish or epoxy resin associated with known printed circuit board substrates.Type: GrantFiled: October 11, 2001Date of Patent: August 21, 2007Assignee: Littelfuse, Inc.Inventor: Edwin James Harris, IV
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Patent number: 7255925Abstract: The present invention relates to a thermosetting resin composition for a high speed transmission circuit board, more particularly to a thermosetting resin composition having superior dielectric characteristics with low dielectric constant and dissipation factor and having superior glass transition temperature, heat resistance after moisture absorption, dielectric reliability, adhesion to copper film, workability, dispersibility of inorganic filler, electric characteristics, etc., and thus being useful for a copper clad laminate for high speed signal transfer.Type: GrantFiled: September 3, 2004Date of Patent: August 14, 2007Assignee: LG Chem, Ltd.Inventors: Hyuk-Sung Chung, Bong-Jin Jeon, Hyun-Cheol Kim, Eun-Hae Koo
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Patent number: 7252891Abstract: A wiring transfer sheet including a carrier base and a wiring layer formed thereon is produced so that an exposed area of a surface of the carrier base on which the wiring layer is formed has a plurality of concavities. By transferring the wiring layer to an electrically insulating substrate with this wiring transfer sheet, convexities which are complementary to the concavities are formed on the electrically insulating substrate. The convexities improve adhesion between a wiring board and a resin stacked thereon. Therefore, the wiring board thus obtained has surface coplanarity suitable for mounting a semiconductor bare chip and an electronic component as a whole, and a microscopical surface structure which adheres to a material stacked thereon.Type: GrantFiled: January 16, 2004Date of Patent: August 7, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hideki Higashitani
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Publication number: 20070178289Abstract: An electronic system includes a circuit board formed from a composite material. The composite material includes fibers embedded within a substrate and the fibers are oriented substantially orthogonal to one another. A plurality of traces are formed on the board, and the plurality of traces are oriented relative to at least one of the fibers at an angle between about 17.5° and about 27.5° or between about 20.0° and about 25.0°. A pair of the traces are oriented substantially orthogonal to one another, and a pair of the traces are oriented relative to one another at an angle of about 45.0°. The fibers are fiberglass, and the substrate is an epoxy resin. The fibers have a different dielectric constant than the substrate.Type: ApplicationFiled: January 27, 2006Publication date: August 2, 2007Applicant: International Business Machines CorporationInventors: Moises Cases, Daniel N. de Araujo, Bradley D. Herrman, Erdem Matoglu, Pravin Patel, Nam H. Pham, Joffre A. Ratcliffe
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Publication number: 20070148420Abstract: A printed circuit is made with a via-defining substrate including a microelectronic substrate defining via openings therein. Interconnects are provided on the via-defining substrate according to a predetermined interconnect pattern. The interconnects include a conductive layer having a pattern corresponding to the predetermined interconnect pattern. The conductive layer further being made substantially from a first material. The conductive layer further including a second material that is different from the first material. The second material including a metallic seeding material and is present on the via-defining substrate only at regions corresponding to the interconnects. The interconnects are formed by catalyzing the conductive layer with an activator layer to electrolessly plate the via-defining substrate with the first material.Type: ApplicationFiled: December 28, 2005Publication date: June 28, 2007Inventors: Islam A. Salama, Omar J Behir
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Publication number: 20070141310Abstract: Disclosed are a printed circuit board and a method of manufacturing the same, in which a fluorine resin coating layer is formed on a resin substrate, and then a copper layer is formed using a dry process including ion beam surface treatment and vacuum deposition instead of a conventional wet process including surface roughening and electroless copper plating. According to this invention, the interfacial adhesion of the substrate material may be increased without changing the surface roughness thereof, thus realizing a highly reliable fine circuit. As well, a low dielectric constant and a low loss coefficient may be obtained thanks to the formation of the fluorine resin layer. Further, a wet process is replaced with a dry process, whereby the copper plating layer may be formed in an environmentally friendly manner.Type: ApplicationFiled: October 24, 2006Publication date: June 21, 2007Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jong Seok Song, Taehoon Kim
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Patent number: 7224046Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).Type: GrantFiled: June 1, 2005Date of Patent: May 29, 2007Assignee: Fujitsu LimitedInventors: Tomoyuki Abe, Nobuyuki Hayashi, Motoaki Tani
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Patent number: 7217463Abstract: This invention relates to a film comprising a machine direction oriented polymeric film prepared from (A) at least one propylene homopolymer or copolymer or lend of two or more thereof, wherein (A) has a melt flow rate from about 6 to about 30 and (B) an olefin elastomer having a melt flow rate of 0.5 to 10. In one embodiment, the film also contains a nucleating agent. In one embodiment, these films are clear. The films have good stiffness and clarity with low haze. These films are useful in preparing labels and may be used as a monolayer film or in a multilayer film. In one embodiment, the films are printable. Die-cut labels are also described which comprise a composite comprising the extruded, machine-direction oriented polypropylene copolymer films of the present invention in combination with an adhesive associated with said copolymer films for adhering said label to a substrate.Type: GrantFiled: June 26, 2003Date of Patent: May 15, 2007Assignee: Avery Dennison CorporationInventor: Kevin O. Henderson
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Patent number: 7217462Abstract: The metal foil-clad laminate of the present invention comprises at least one polyimide layer made of a polyimide having repeating units represented by the following formula I: wherein R and ? are as defined in the specification, at least one insulating substrate, and at least one metal foil layer. The polyimide is excellent in thermopress-bonding property, solubility in solvents and heat resistance, and exhibits a low dielectric constant. The metal foil-clad laminate having the polyimide layer is suitably applicable to high-frequency printed wiring boards, etc.Type: GrantFiled: May 10, 2004Date of Patent: May 15, 2007Assignee: Mitsubishi Gas Chemical Company, Inc.Inventors: Shuta Kihara, Ko Kedo
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Patent number: 7213334Abstract: A double-sided flexible printed board is manufactured by: (a) forming a polyimide precursor layer on a metal layer; (b) forming an upper circuit layer on the polyimide precursor layer by a semi-additive technique; and (c) imidating the polyimide precursor layer to form a polyimide insulating layer.Type: GrantFiled: December 16, 2003Date of Patent: May 8, 2007Assignees: Sony Corporation, Sony Chemical & Information Device CorporationInventors: Hideyuki Kurita, Masanao Watanabe
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Patent number: RE39615Abstract: The invention relates to an adhesive composition, comprising: (A) at least one phenolic resole resin; and (B) the product made by reacting (B-1) at least one difunctional epoxy resin, with (B-2) at least one compound represented by the formula wherein in Formulae (I) and (II): G, T and Q are each independently functional groups selected from the group consisting of COOH, OH, SH, NH2, NHR1, (NHC(?NH))mNH2, R2COOH, NR12, C(O)NHR1, R2NR12, R2OH, R2SH, R2NH2 and R2NHR1, wherein R1 is a hydrocarbon group, R2 is an alkylene or alkylidene group and m is a number in the range of 1 to about 4; T can also be R1, OR1 or SO2C6H4—NH2; and Q can also be H. The invention also relates to copper foils having the foregoing adhesive composition adhered to at least one side thereof to enhance the adhesion between said foils and dielectric substrates.Type: GrantFiled: October 17, 2002Date of Patent: May 8, 2007Assignee: Nikko Materials USA, Inc.Inventor: Charles A. Poutasse
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Patent number: RE40947Abstract: A multilayer printed wiring board is composed of a substrate provided with through-holes, and a wiring board formed on the substrate through the interposition of an interlaminar insulating resin layer, the through-holes having a roughened internal surface and being filled with a filler, an exposed part of the filler in the through-holes being covered with a through-hole-covering conductor layer, and a viahole formed just thereabove being connected to the through-hole-covering conductor layer. Without peeling between the through-holes and the filler, this wiring board has a satisfactory connection reliability between the through-holes and the internal layer circuit and provides a high density wiring.Type: GrantFiled: October 12, 1990Date of Patent: October 27, 2009Assignee: Ibiden Co., Ltd.Inventors: Motoo Asai, Kenichi Shimada, Kouta Noda, Takashi Kariya, Hiroshi Segawa