Printed Circuit Patents (Class 428/901)
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Patent number: 6927272Abstract: Material of electronics component and electronics components using the same material are provided. The material includes repellent that can withstand severe solder-mounting conditions, and the electronics components such as printed wiring boards can lasts repelling effect for a long period. The material is used in electronics components requiring a soldering process, and includes at least curable resin, filler and the repellent. The repellent has vapor pressure of less than 10,000 nPa at room temperature. Film is formed using the material at a given place of an electronics component such as a printed wiring board.Type: GrantFiled: May 31, 2002Date of Patent: August 9, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazumi Iwasaki
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Patent number: 6923923Abstract: Disclosed are a metallic nanoparticle cluster ink and a method for forming a conductive metal pattern using the cluster ink. The metallic nanoparticle cluster ink comprises colloidal metallic nanoparticles and a bifunctional compound. The conductive metal pattern is formed by forming a metallic nanoparticle pattern on a substrate using a mold made from PDMS (poly(dimethylsiloxane) polymer as a stamp, and heat-treating the substrate. Micrometer-sized conductive metal patterns can be easily formed on various substrates in a simple and inexpensive manner without the use of costly systems, thereby being very useful in various industrial fields.Type: GrantFiled: December 27, 2002Date of Patent: August 2, 2005Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and TechnologyInventors: Jin Woo Cheon, Sung Nam Cho, Jong Il Park, Kyung Bok Lee, Seok Chang, Soon Taik Hwang
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Patent number: 6916527Abstract: A resin molded component, comprising metal coating treatment being provided on the surface by a physical deposition method chosen from among sputtering, vacuum deposition, and ion plating after the surface is activated by plasma treatment, and is produced by forming a resin composition combined a base resin comprising of a thermoplastic resin or a thermosetting resin with a rubber-like elastic material.Type: GrantFiled: November 7, 2001Date of Patent: July 12, 2005Assignee: Matsushita Electric Works, Ltd.Inventors: Naoto Ikegawa, Masahiro Sato, Naoyuki Kondo
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Patent number: 6916539Abstract: A halogen-free, flame-retardant insulating epoxy resin composition which comprises (1) an epoxy resin, (2) a curing agent for the epoxy resin, (3) a phosphate of a resorcinol type, (4) aluminum hydroxide, and (5) a cure accelerator for the epoxy resin. The composition displays necessary flame retardant properties and sufficient insulating properties after the formation of an insulating layer in a circuit board, withstands a plating process, and does not cause the bleedout of the insulation layer formed. A circuit board with flame retardant properties comprising insulation layers formed of the epoxy resin composition is also disclosed.Type: GrantFiled: August 9, 2002Date of Patent: July 12, 2005Assignee: Fujitsu LimitedInventors: Nawalage Florence Cooray, Koji Tsukamoto, Takeshi Ishitsuka
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Patent number: 6913814Abstract: A lamination process and structure of a high layout density substrate is disclosed. The lamination process comprises the following steps. First of all, a plurality of laminating layers are individually formed, wherein each laminating layer has a first dielectric layer, a plurality of first vias and a patterned conducting layer. Next, a bottom layer having a second dielectric layer and a plurality of second vias is formed. Then, the laminating layers and the bottom layer are stacked. Finally, the laminating layers and the bottom layer are laminated simultaneously to form a multiplayer substrate at one time.Type: GrantFiled: November 19, 2003Date of Patent: July 5, 2005Assignee: Via Technologies, Inc.Inventors: Kwun Yao Ho, Moriss Kung
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Patent number: 6908685Abstract: The invention provides a polyimide film manufactured from a polyamic acid prepared from pyromellitic dianhydride in combination with 10 to 60 mol % of phenylenediamine and 40 to 90 mol % of 3,4?-oxydianiline, based on the overall diamine. The polyimide film, when used as a metal interconnect board substrate in flexible circuits, chip scale packages (CSP), ball grid arrays (BGA) or tape-automated bonding (TAB) tape by providing metal interconnects on the surface thereof, achieves a good balance between a high elastic modulus, a low thermal expansion coefficient, alkali etchability and film formability.Type: GrantFiled: August 23, 2001Date of Patent: June 21, 2005Assignees: E. I. du Pont de Nemours and Company, DuPont-Toray Co. Ltd.Inventors: Kenji Uhara, Kouichi Sawasaki, Naofumi Yasuda, Brian C. Auman, John D. Summers
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Patent number: 6903463Abstract: A chip-on-glass (COG) assembly, in which the electrodes of the semiconductor chips (3) are held in direct connection with the corresponding electrodes on the substrate glass circuit board (1), utilizes a layer (5) of a connecting material for bonding and connecting the semiconductor chip (3) with the substrate board (1). The connecting material can provide a reduced stress concentration at the boundaries between the binder layer (5) and the chip (3) and between the binder layer (5) and the glass board (1), even at higher adhesive strengths, bringing about less deformation, such as warping, of the resulting bonded assembly, even when using a thinner substrate glass board, and provides a superior bonding strength and excellent electroconductive performance. The connecting material is made up of, on the one hand, an adhesive component (6) containing a thermosetting resin and, on the other hand, electroconductive particles (7) and has a characteristic feature that a tensile elongation percentage at 25° C.Type: GrantFiled: September 11, 2000Date of Patent: June 7, 2005Assignee: Sony Chemicals CorporationInventors: Motohide Takeichi, Hiroyuki Fujihira
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Patent number: 6896967Abstract: An ultraviolet curable resin composition comprises (A) an ultraviolet curable resin obtained by reacting an epoxy group containing polymer (a), which is prepared by polymerizing an ethylenically unsaturated monomer component including an ethylenically unsaturated monomer (i) having an epoxy group, with an ethylenically unsaturated monomer (b) having a carboxyl group, and then reacting a resultant intermediate product with a saturated or unsaturated polybasic acid anhydride (c); (B) an epoxy compound having at least two epoxy groups in molecule; (C) a photopolymerization initiator; and (D) a diluent The ultraviolet curable resin includes 0.3 to 10 mol of a polymerizable unsaturated group in 1 kg thereof. A photo solder resist ink containing this resin composition has the capability of providing a permanent film with excellent flexibility and solder heat resistance, and is preferably used to manufacture flexible printed circuit boards.Type: GrantFiled: September 14, 2001Date of Patent: May 24, 2005Assignee: Goo Chemical Co., Ltd.Inventors: Hiroko Daido, Soichi Hashimoto
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Patent number: 6890635Abstract: Disclosed are fiber reinforced composite substrates comprising a polymeric matrix and one or more woven or non-woven para-aramid or fiberglass fabrics, sheets, or papers, said polymeric matrix consisting essentially of one or more cross-linked copolymers of monovinyl aromatic hydrocarbons and conjugated dienes useful for printed circuit boards and cards suitable for use in high frequency circuits.Type: GrantFiled: April 25, 2003Date of Patent: May 10, 2005Assignee: E. I. du Pont de Nemours and CompanyInventors: Pui-Yan Lin, Govindasamy Paramasivan Rajendran, George Elias Zahr
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Patent number: 6890618Abstract: An apparatus and method are provided for retaining thermal transfer pins in a spreader plate adapted to transfer thermal energy from an electronic component. The spreader plate includes pin holes that slidably receive the thermal transfer pins. The apparatus includes a retention member located proximate each pin hole. The retention member interferes with a range of motion of an associated pin in order to retain the associated pin within the pin hole.Type: GrantFiled: September 10, 2002Date of Patent: May 10, 2005Assignee: Tyco Electronics CorporationInventor: Craig W. Hornung
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Patent number: 6890617Abstract: A porous adhesive sheet 1 having plural through holes 2 running in about parallel with each other in the thickness direction A of an adhesive organic film 3, wherein the through holes have about congruent sections in the diameter direction from one opening 2a to the other opening 2b and a production method thereof, and a semiconductor wafer with a porous adhesive sheet 31, which includes a semiconductor wafer 32 having an electrode 33, the porous adhesive sheet 1 adhered to the semiconductor wafer, and a conductive part 34 formed by filling a through hole 2 located on the electrode 33 with a conductive material, and a production method thereof are provided.Type: GrantFiled: August 18, 2000Date of Patent: May 10, 2005Assignee: Nitto Denko CorporationInventors: Miho Yamaguchi, Yuji Hotta
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Patent number: 6887560Abstract: A multilayer flexible wired circuit board that can provide high density wiring and also can provide reduction in thickness and size, and a producing method thereof. A four-layered flexible wired circuit board is produced by preparing a double-sided substrate in which a first conductor layer and a second conductor layer are laminated on both sides of a first insulating layer; preparing a first single-sided substrate in which a third conductor layer is laminated on one surface of a second insulating layer and a second single-sided substrate in which a fourth conductor layer is laminated on one surface of a third insulating layer; bonding the first conductor layer and the third conductor layer to each other through a first thermosetting adhesive layer; and bonding the second conductor layer and the fourth conductor layer to each other through a second thermosetting adhesive layer.Type: GrantFiled: July 3, 2002Date of Patent: May 3, 2005Assignee: Nitto Denko CorporationInventors: Kei Nakamura, Satoshi Tanigawa, Hiroshi Yamazaki, Mineyoshi Hasegawa
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Patent number: 6887574Abstract: A curable flame retardant epoxy resin composition including (a) at least one flame retardant epoxy resin; (b) at least one amphiphilic block copolymer; and (c) a curing agent. Such components are present in the curable composition in the appropriate amounts and ratios such that, upon curing, the block copolymer self-assembles into a nano structure morphology, such as a worm-like micelle morphology. The resulting cured product made from the composition of the present invention has a remarkably increased high fracture resistance; and allows the use of flame retardant epoxies in applications where fracture resistance is an issue.Type: GrantFiled: June 6, 2003Date of Patent: May 3, 2005Assignees: Dow Global Technologies Inc., Regents of the University of MinnesotaInventors: Jennifer M. Dean, Frank S. Bates, Ha Q. Pham, Nikhil E. Verghese
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Patent number: 6884655Abstract: A wiring layer for serving as a first electrode layer of a capacitor portion patterned in a predetermined shape on an insulative base member is formed. A resin layer for serving as a dielectric layer of the capacitor portion is formed on a surface of the wiring layer using an electrophoretic process. Another wiring layer for serving as a second electrode layer of the capacitor portion patterned in a predetermined shape by patterning on the insulative base member inclusive of the resin layer is formed.Type: GrantFiled: June 4, 2004Date of Patent: April 26, 2005Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takahiro Iljima, Akio Rokugawa, Noriyoshi Shimizu
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Patent number: 6881293Abstract: The present invention is directed to an inter-laminar adhesive composition containing a liquid epoxy resin, a polyfunctional epoxy resin having a softening point higher than a lamination temperature of the adhesive and with two or more epoxy groups within the molecule; and a latent epoxy curing agent initiating a reaction at a temperature higher than the lamination temperature. The adhesive composition optionally contains a liquid resin other than the liquid epoxy resin and/or an organic solvent and the liquid resin includes the liquid epoxy resin, the organic solvent or both constituting from 10 to 55% by weight of the composition. This inter-laminar adhesive composition allows for the preparation of a multi-layer printed wiring board. The process for preparing the multi-layer printed wiring board is provided.Type: GrantFiled: February 25, 2002Date of Patent: April 19, 2005Assignee: Ajinomoto Co., Inc.Inventors: Shigeo Nakamura, Tadahiko Yokota
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Patent number: 6872436Abstract: The invention provides a method for manufacturing printed wiring substrates which can manufacture printed wiring substrates each having resin dielectric layers of uniform thickness and excellent surface flatness while maintaining favorable cutting performance in a dicing step. A multi-printed wiring-substrate panel is manufactured which includes a metal plate having a first main surface and a second main surface, and resin dielectric layers disposed on the first and second main surfaces. The metal plate has first depression portions and second depression portions. The first depression portions are opened at the first main surface and arranged discontinuously along predetermined cutting lines. The second depression portions are opened at the second main surface and arranged discontinuously along the predetermined cutting lines. The multi-printed wiring-substrate panel is cut along the predetermined cutting lines into a plurality of printed wiring substrates.Type: GrantFiled: January 10, 2003Date of Patent: March 29, 2005Assignee: NGK Spark Plug Co. Ltd.Inventors: Tomoe Suzuki, Shinji Yuri, Kazuhisa Sato, Kozo Yamasaki
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Patent number: 6869665Abstract: A wiring board includes a core layer and a pair of multilayer wiring portions. The core layer, having an upper surface and a lower surface, is formed from a resin composite which contains resin filler and encloses several pieces of carbon fiber cloth. One of the multilayer wiring portions is stacked on the upper surface of the core layer, while the other is stacked on the lower surface of the core layer. Each multilayer wiring portion is composed of a number of insulating layers and wiring patterns stacked alternately with the insulating layers. The wiring patterns of the upper and the lower wiring portions are connected to each other by conductors extending through the entire thickness of the core layer.Type: GrantFiled: August 20, 2003Date of Patent: March 22, 2005Assignee: Fujitsu LimitedInventors: Motoaki Tani, Nobuyuki Hayashi, Tomoyuki Abe, Yasuhito Takahashi, Yoshiyasu Saeki
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Patent number: 6869664Abstract: Prepregs, laminates, printed wiring board structures and processes for constructing materials and printed wiring boards that enable the construction of printed wiring boards with improved thermal properties. In one embodiment, the prepregs include substrates impregnated with electrically and thermally conductive resins. In other embodiments, the prepregs have substrate materials that include carbon. In other embodiments, the prepregs include substrates impregnated with thermally conductive resins. In other embodiments, the printed wiring board structures include electrically and thermally conductive laminates that can act as ground and/or power planes.Type: GrantFiled: December 11, 2001Date of Patent: March 22, 2005Assignee: ThermalWorks, Inc.Inventors: Kalu K. Vasoya, Bharat M. Mangrolia, William E. Davis, Richard A. Bohner
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Patent number: 6866919Abstract: The present invention relates to a heat-resistant film base-material-inserted B-stage resin composition sheet for producing a multilayer printed wiring board which is excellent in copper adhesive strength, heat resistance and insulating reliability particularly in the Z direction and is suitable for use, as a high density small printed wiring board, in a semiconductor-chip-mounting, small-sized and lightweight novel semiconductor plastic package, and to a use thereof.Type: GrantFiled: February 20, 2003Date of Patent: March 15, 2005Assignee: Mitsubishi Gas Chemical Company, Inc.Inventors: Nobuyuki Ikeguchi, Morio Mori
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Patent number: 6866908Abstract: An electromagnetic radiation interference mitigation shield is provided for an electronic circuit component. The shield includes a body formed from an electrically and thermally conductive composite material characterized by a volume resistivity ranging from about 0.1 to about 1,000 ohm-cm and a thermal conductivity ranging from about 10×10?4-cal.-cm./sec.-cm.2-° C. to about 30×10?4-cal.-cm./sec.-cm.2-° C.Type: GrantFiled: March 12, 2003Date of Patent: March 15, 2005Assignee: Parker-Hannifin CorporationInventors: Parker Ross Lichtenstein, Hong Peng
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Patent number: 6867983Abstract: A device, such as a radio frequency identification (RFID) inlay structure for an RFID tag or label, includes a microstructure element, with leads coupling the microstructure element to other electrical or electronic components of the device. The leads may be electroless-plated leads, and may contact connectors of the microstructure element without the need for an intervening planarization layer.Type: GrantFiled: August 7, 2002Date of Patent: March 15, 2005Assignee: Avery Dennison CorporationInventors: Peikang Liu, Scott Wayne Ferguson, Dave N. Edwards, Yukihiko Sasaki
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Patent number: 6863962Abstract: A thermally conductive substrate having a structure in which inorganic filler for improving the thermal conductivity and thermosetting resin composition are included. The thermosetting resin composition has a flexibility in the not-hardened state, and becomes rigid after hardening. The thermally conductive substrate has excellent thermal radiation characteristics. The method of manufacturing the thermally conductive substrate includes: piling up (a) the thermally conductive sheets comprising 70 to 95 weight parts of an inorganic filler, and 4.Type: GrantFiled: December 4, 2002Date of Patent: March 8, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Seiichi Nakatani, Hiroyuki Handa
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Patent number: 6852427Abstract: The present invention is directed to an aqueous, antitarnish and adhesion promoting treatment composition, comprising: zinc ions; metal ions selected from the group consisting of tungsten ions, molybdenum ions, cobalt ions, nickel ions, zirconium ions, titanium ions, manganese ions, vanadium ions, iron ions, tin ions, indium ions, silver ions, and combinations thereof; and optionally, an electrolyte that does not contain potassium or sodium ions; wherein the treatment composition is substantially free of chromium, and wherein the treatment composition forms a coating on a substrate or material that enhances adhesion of a polymer to the material. The present invention is also directed to materials coated with the above treatment composition, and methods of coating materials using the above composition.Type: GrantFiled: September 2, 2003Date of Patent: February 8, 2005Assignee: Olin CorporationInventors: Leonard R. Howell, Szuchain F. Chen
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Patent number: 6846550Abstract: An adhesive film for underfill which relaxes the stress formed in the wiring circuit substrate, semiconductor element and electrode parts for connection. The adhesive film is a quickly hardening type, and forms a highly heat resistant sealing resin layer quickly between the wiring circuit substrate and semiconductor element of a semiconductor device.Type: GrantFiled: November 12, 2003Date of Patent: January 25, 2005Assignee: Nitto Denko CorporationInventors: Akiko Matsumura, Kazuki Uwada, Naoki Sadayori, Yuji Hotta
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Patent number: 6841228Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.Type: GrantFiled: September 3, 2003Date of Patent: January 11, 2005Assignee: International Business Machines CorporationInventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
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Patent number: 6838400Abstract: The glass transmittance of UV light having a wavelength of 365 nanometers is reduced by compounding an oxide or salt of at least one of Fe, Cu, Cr, Ce, Mn and mixtures thereof. The fiberglass cloth can be used for providing reinforced prepregs used in producing printed circuit boards or laminated chip carrier substrates.Type: GrantFiled: March 23, 1998Date of Patent: January 4, 2005Assignee: International Business Machines CorporationInventors: Robert Maynard Japp, Pamela Lulkoski, Jeffrey McKeveny, Jan Obrzut, Kenneth Lynn Potter
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Patent number: 6838164Abstract: A method for manufacturing a printed wiring board, comprising the step of forming a hole by an energy beam such as a laser beam, wherein formation of a resin film by a substrate-material resin oozing to the inner-wall surface of a hole is prevented, by lowering the water-absorption percentage of a substrate material through the dehumidifying step as the preprocess of the hole-forming step for forming a through-hole or non-through-hole for interconnecting circuits formed on both sides or in multiple layers, thereby it is possible to realize high-quality hole-formation by preventing a defective resin film formation and obtain a high-reliability printed wiring board.Type: GrantFiled: April 24, 2002Date of Patent: January 4, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigeru Yamane, Toshihiro Nishii, Shinji Nakamura, Masayuki Sakai
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Publication number: 20040265551Abstract: A resinous material, or a composite material obtained by mixing a resin and a powdery functional material is formed into a thin sheet to make a core substrate 1. A patterned thin-film conductor 2 is formed by thin-film forming technology on at least either of the front and rear surfaces of the core substrate 1. Clothless layers 3a to 3d are super-posed on at least that surface of the core substrate 1 on which the thin-film conductor 2 has been formed. Each clothless layer is formed from a resin-coated metal foil obtained by coating one surface of a metal foil with a resinous material, or a composite material obtained by mixing a resin and a powdery functional material. Conductor layers 4a to 4d obtained by patterning the metal foils are formed on the clothless layers 3a to 3d.Type: ApplicationFiled: April 22, 2004Publication date: December 30, 2004Applicant: TDK CORPORATIONInventors: Minoru Takaya, Toshikazu Endo
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Patent number: 6835443Abstract: In a method of fabricating an array of microstructures, a substrate with an electrically-conductive portion is provided, an insulating mask layer is formed on the electrically-conductive portion of the substrate, a plurality of openings are formed in the insulating mask layer to expose the electrically-conductive portion, and a first plated or electrodeposited layer is deposited in the openings and on the insulating mask layer by electroplating or electrodeposition. A second plated layer is further formed on the first plated or electrodeposited layer and on the electrically-conductive portion by electroless plating to reduce a size distribution of microstructures over the array.Type: GrantFiled: June 2, 2003Date of Patent: December 28, 2004Assignee: Canon Kabushiki KaishaInventors: Takayuki Teshima, Takayuki Yagi, Yasuhiro Shimada, Takashi Ushijima
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Patent number: 6835442Abstract: A flexible printed board contains an unroughened electrodeposited copper foil, a zinc-based metallic layer provided thereon in an amount of 0.25 to 0.40 mg/dm2, and a polyimide resin layer formed through the imidation of a polyamic acid layer provided on the zinc-based metallic layer.Type: GrantFiled: September 12, 2002Date of Patent: December 28, 2004Assignees: Sony Chemicals Corp., Circuit Foil Japan Co., Ltd.Inventors: Noriaki Kudo, Asaei Takabayashi, Akitoshi Suzuki, Shin Fukuda
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Patent number: 6835895Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.Type: GrantFiled: June 11, 1999Date of Patent: December 28, 2004Assignee: IBIDEN Co., Ltd.Inventors: Motoo Asai, Yasuji Hiramatsu
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Publication number: 20040253425Abstract: A wiring board has a substrate, a bank disposed above the substrate and providing a plurality of regions, and a conductive layer and first and second interconnecting lines which are parallel to each other and formed between the bank and the substrate. The first interconnecting line is formed in a position closer to the substrate than the second interconnecting line. The vertical centerline of the first interconnecting line is not coincide with the vertical centerline of the second interconnecting lines. The conductive layer is formed in a position closer to the substrate than the second interconnecting line. The vertical centerline of the conductive layer is not coincide with the vertical centerline of the second interconnecting line. The conductive layer and first interconnecting line have portions which are not located under the second interconnecting line and extend in opposite width directions.Type: ApplicationFiled: January 27, 2004Publication date: December 16, 2004Applicant: SEIKO EPSON CORPORATIONInventor: Koji Aoki
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Patent number: 6831233Abstract: A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.Type: GrantFiled: March 7, 2001Date of Patent: December 14, 2004Assignee: Intel CorporationInventor: Dustin P. Wood
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Patent number: 6828669Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.Type: GrantFiled: December 14, 2000Date of Patent: December 7, 2004Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takahiro Iijima, Shinichi Wakabayashi, Yuichi Matsuda
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Publication number: 20040241401Abstract: Capacitor material for use in forming capacitors, is disclosed. More specifically, the invention is directed to capacitors formed from this material that have one or more discrete electrodes (314), each electrode (314) being exposed to at least two thicknesses of dielectric material (300). These electrodes (314) are surrounded by wider insulative material (312) such that the material can be cut, or patterned into capacitors having specific values. A single electrode can form a small value capacitor while still providing a larger conductive area for attaching the capacitor to associated circuitry. The thin dielectric (310) can be a tunable material so that the capacitance can be varied with voltage. The tunability can be increased by adding thin electrodes that interact with direct current.Type: ApplicationFiled: November 5, 2003Publication date: December 2, 2004Inventors: Andrew T Hunt, Mark G Allen, David Kiesling
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Patent number: 6824857Abstract: Disclosed is a circuit element that includes a thermoplastic substrate and a conductive trace at least partially embedded in the thermoplastic substrate. Also disclosed is a method of forming a circuit element. The method includes the steps of providing a thermoplastic substrate having a softening temperature, printing a conductive ink onto the thermoplastic substrate to form a trace, and embedding the trace into the thermoplastic substrate by heating the thermoplastic substrate to a temperature above about the softening temperature about the trace.Type: GrantFiled: April 1, 2002Date of Patent: November 30, 2004Assignee: Nashua CorporationInventors: Darren Lochun, John J. Ireland
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Patent number: 6824880Abstract: The invention relates to a process to enhance adhesion of resistive foil to laminating materials, including: providing a copper foil; depositing at least one resistive metal layer on at least one side of the copper foil; and applying at least one layer of at least one adhesion-promoting material over and adhered to the resistive metal layer, the adhesion-promoting material being suitable for enhancing adhesion between the resistive metal layer and laminating materials. The resistive metal layer may include NiCr, NiCrAlSi, aluminum, nickel, zinc, titanium, vanadium, chromium, manganese, iron, tantalum, molybdenum, ruthenium, and alloys, oxides, nitrides and silicides thereof. The invention further relates to a multilayer foil and to a laminate, both including the resistive metal layer and adhesion-promoting material.Type: GrantFiled: May 15, 2003Date of Patent: November 30, 2004Assignee: Ga-Tek, Inc.Inventors: Atnaf Admasu, Jiangtao Wang, Sidney Clouser
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Patent number: 6821657Abstract: A solvent-free thermosetting resin composition which comprises an epoxy resin (a) and a product (b) of the reaction of an organosilicon compound, represented by the general formula (1) (where R is an organic group containing a functional group reactive with an epoxy resin by addition reaction; and R1 is a methyl or ethyl group), with water, the product (b) containing organosilicon compound polycondensates formed in the epoxy resin (a) and having a degree of polycondensation of 2 or higher, and which has a low viscosity at a room temperature (25° C.) and gives a cured resin having intact material properties, especially intact high-temperature mechanical properties; a process for producing the resin composition; and a product obtained by applying the composition.Type: GrantFiled: September 25, 2002Date of Patent: November 23, 2004Assignee: Hitachi, Ltd.Inventors: Akio Takahashi, Yuichi Satsu, Harukazu Nakai, Masao Suzuki, Yuzo Ito, Shuichi Oohara
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Patent number: 6820332Abstract: A substrate and a method of making the substrate is provided. The substrate includes a layer of metal with at least one through hole therein, the layer of metal having an adhesion promoting layer thereon. A layer of a partially cured low-loss polymer or polymer precursor is positioned on the adhesion promoting layer and a plurality of conductive circuit lines are positioned on a portion of the partially cured dielectric layer. The substrate can be used as a building block in the fabrication of a multilayered printed circuit board.Type: GrantFiled: July 16, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Robert M. Japp, Voya R. Markovich, Konstantinos I. Papathomas
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Patent number: 6821902Abstract: The present invention relates to an electroless-plating liquid useful for forming a protective film for selectively protecting surface of exposed interconnects of a semiconductor device which has an embedded interconnect structure formed by an electric conductor, such as copper or silver, embedded in fine recesses for interconnects formed in a surface of a semiconductor substrate, and also to a semiconductor device in which surfaces of exposed interconnects are selectively protected with a protective film. The electroless-plating liquid contains cobalt ions, a complexing agent and a reducing agent containing no alkali metal.Type: GrantFiled: February 10, 2004Date of Patent: November 23, 2004Assignee: Ebara CorporationInventors: Hiroaki Inoue, Kenji Nakamura, Moriji Matsumoto
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Patent number: 6822170Abstract: In an embedding resin for embedding electronic parts, after a substrate in which a copper layer is formed on a cured product of the embedding resin is subjected to a pressure cooker test, the copper layer has a peeling strength of at least 588 N/m (0.6 kg/cm), wherein the conditions of the pressure cooker test are 121° C., 100% by mass humidity, 2.1 atm and 168 hours, and the measurement method of the peeling strength is according to JIS C 5012, and the width of the copper layer is 10 mm.Type: GrantFiled: December 26, 2001Date of Patent: November 23, 2004Assignee: NGK Spark Plug Co., Ltd.Inventors: Hiroki Takeuchi, Toshifumi Kojima, Kazushige Ohbayashi, Hisahito Kashima
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Patent number: 6818284Abstract: In a single-sided paper phenolic resin copper-clad laminate composed of a phenolic resin impregnated paper base having copper foils laminated on and resists applied on the face side thereof, resists formed of the same material as the resists on the face side are applied also on the reverse side of the phenolic resin impregnated paper base, so that the face side and the reverse side match approximately with each other in thermal expansibility. The single-sided paper phenolic resin copper-clad laminate warps only slightly even when the peak temperature is raised to a degree suitable for lead-free solder in the reflow process for mounting electronic components.Type: GrantFiled: February 11, 2002Date of Patent: November 16, 2004Assignee: Minebea Co., Ltd.Inventors: Takaaki Ono, Sadayuki Toda
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Patent number: 6818285Abstract: A crosslinked polyarylene material with a reduced coefficient of thermal expansion at high temperatures compared with conventional crosslinked polyarylene materials is provided. In addition, an integrated circuit article containing a crosslinked polyarylene polymer with reduced coefficient of thermal expansion at high temperatures is provided.Type: GrantFiled: December 31, 2002Date of Patent: November 16, 2004Assignee: International Business Machines CorporationInventors: Jeffrey C. Hedrick, Muthumanickam Sankarapandian, Christy S. Tyberg, James P. Godschalx, Qingshan J. Niu, Harry C. Silvis
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Patent number: 6811725Abstract: Described is a compliant and crosslinkable thermal interface material of at least one silicone resin mixture, at least one wetting enhancer and at least one thermally conductive filler, and a method of making and using same; as well as a method of improving thermal conductivity of polymer and resin systems.Type: GrantFiled: May 27, 2003Date of Patent: November 2, 2004Assignee: Honeywell International Inc.Inventors: My N. Nguyen, James Grundy
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Publication number: 20040214006Abstract: A member for a circuit board according to the present invention includes a prepreg and a mold release film that is provided on at lease one side of the prepreg. The mold release film contains or is coated with a heat absorbing substance having a heat absorbing property. A method of manufacturing a member for a circuit board according to the present invention includes allowing a mold release film to adhere to at least one side of a prepreg by heating and pressing. The mold release film contains or is coated with a heat absorbing substance having a heat absorbing property. In the method, the heating is performed at a temperature not lower than a softening point of the prepreg and not higher than an endothermic temperature of the heat absorbing substance.Type: ApplicationFiled: April 12, 2004Publication date: October 28, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kumiko Hirayama, Fumio Echigo, Izuru Nakai, Yoji Ueda
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Patent number: 6808798Abstract: This invention relates to a heat conductive resin substrate which polybenzasol fibers are oriented in a thick direction and/or a direction of a surface of a resin substrate, further to the heat conductive resin substrate and a semiconductor package excellent in heat radiation ability which the semiconductor chips are mounted on the heat conductive resin substrate which the polybenzasol fibers are oriented in the thick direction (the Z direction) and/or the direction of the surface of the resin substrate, the heat conductive resin substance and the semiconductor package being provided with electrical insulation and high thermal conductivity, and being capable of controlling the thermal expansion coefficient.Type: GrantFiled: April 18, 2002Date of Patent: October 26, 2004Assignee: Polymatech Co., Ltd.Inventor: Masayuki Tobita
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Patent number: 6805958Abstract: The present invention provides an epoxy resin composition containing (A) an epoxy resin having two or more epoxy groups in one molecule, (B) a phenolic curing agent, (C) a phenoxy resin containing a bisphenol S skeleton and having a weight average molecular weight of 5,000 to 100,000, and (D) a curing accelerator, wherein the epoxy resin (A) contains a phosphorus atom, and wherein 5 to 50 parts by weight of the phenoxy resin (C) and 0.05 to 10 parts by weight of the curing accelerator (D) are mixed with 100 parts by weight in total of the epoxy resin (A) and the phenolic curing agent (B).Type: GrantFiled: June 10, 2002Date of Patent: October 19, 2004Assignee: Ajinomoto Co., Inc.Inventors: Shigeo Nakamura, Tadahiko Yokota
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Patent number: 6803092Abstract: A composition for electrophoretic deposition of an insulating, protective coating. The composition comprises a cationic resin emulsion; and a curative mixed with the cationic resin emulsion. The composition after electrophoretic deposition and curing provides the protective coating that has a concentration of extractable ionic contaminants less than about 200 nanograms/cm2; and a concentration of labile components less than about 36,000 nanograms/cm2. A coating composition according to the present invention provides an article in the form of a flexible printed circuit, used as an interconnect, comprising a film substrate and a plurality of conductive traces adjacent to a surface of the film substrate to receive the insulating protective coating using electrophoretic deposition techniques.Type: GrantFiled: June 26, 2001Date of Patent: October 12, 2004Assignee: 3M Innovative Properties CompanyInventors: Alphonsus V. Pocius, Rita A. Latourelle
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Publication number: 20040197537Abstract: A class of material having barium, cadmium, and tantalum provides high dielectric constant and low loss for use in electronic and optical applications. The material may also contain an element with valence 2 such as magnesium and zinc. Transition metal dopants can also be added to reduce annealing time and/or to tune the temperature-coefficient of resonant frequency. The dielectric material can be made in ceramic or thin film form. The process begins with a mixture of barium carbonate, zinc oxide, tantalum oxide, and cadmium oxide blended together. The slurry is dried and heated. A sintering agent is added to produce high-density samples. The resulting slurry is dried and an adhesive is added to press the mixture into a solid ceramic samples. Thin film dielectric material is made with a thin film growth technique, such as by exposing the mixture to a laser and growing the material on a substrate.Type: ApplicationFiled: June 30, 2003Publication date: October 7, 2004Inventors: Nathan Newman, Mark van Schilfgaarde, Shaojun Liu, Jihoon Kim
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Publication number: 20040191490Abstract: Composite member 2 consisting of ceramic insulator substrate 3 and two metal layers 4A and 4B such as aluminum sheets is subjected to milling in order to remove the unwanted areas of metal layer 4A (where inter-element spacings are to be formed). In order to suppress cracking due to substrate warpage, a small bottom portion of 4A is left intact as residual metal layer 4Aa which is preferably removed by etching. Milling is performed after thin-film layer of etching resist 5 is applied to the surface of metal layer 4A. By milling in two stages, a step is formed at the bottom of lateral sides of a pattern element to make a skirt which contributes to reducing external stresses.Type: ApplicationFiled: January 29, 2004Publication date: September 30, 2004Inventors: Masahiro Hara, Hideyo Osanai